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Quantum key distribution (QKD) is a technology that allows two users to communicate with theoretically perfect security using standard optical fibres. This is possible by transmitting the key on single photons, meaning a measurement by an eavesdropper disturbs the system in a way observable to the legitimate parties. The technology has advanced since the first protocol proposed in 1984, to the stage where there are now many protocols that can be experimentally implemented. These protocols have allowed secure keys to be generated over distances greater than 400 km and with secure key rates over 10 Mbit/s. In a metropolitan QKD network, it would be desirable for as many users to be connected as possible. Unfortunately, each protocol comes with different requirements on the transmitter and receiver. Even within a single protocol, different clock rates can require individualised transmitter and receiver hardware. This prohibits users from communicating with all receivers, unless they have complex transmitters with hardware for many protocols. This thesis develops a transmitter for practical QKD that is able to adapt to a number of different protocols with no changes to the hardware. The transmitter works using optical injection locking, where a pulse preparation laser adopts the phase of a phase preparation laser. Controlling the phase and intensity of the pulses in this way removes the side channel ordinarily present with direct modulation, in that the phase, intensity and frequency simultaneously change in response to an applied current. The cavity-enhanced electro-optic effect allows for the first demonstration of sub-volt half-wave phase modulation at high clock rates. The transmitter successfully demonstrates phase encoding, intensity encoding and on-demand phase randomisation. This allows for the experimental realisation and direct comparison of different QKD protocols, including one that has never before been implemented due to experimental complexity. A stable intensity modulator is also developed, based on a Sagnac interferometer. This removes a side channel in QKD systems and integrates well with the directly-modulated quantum transmitter. This development also means that the transmitter can implement all current two-party QKD protocols based on weak coherent pulses. The transmitter has the potential to become the standard transmitter for future quantum communication networks due to its stability, versatility and power efficiency. The design could also be demonstrated on a photonic chip, making it compact enough to fit in small transmitter units.

Ever-increasing data generation and transmission demands have been driving great advancements in wireline communications from both electrical and optical approaches for short- and long-distance scenarios, respectively. In the meter range scenario, both electrical and optical approaches face great challenges. That is, the lossy and bandwidth limited channels are the bottlenecks of electrical interconnect. For optical interconnect, the features, such as the required complex fabrication and the high environment sensitivity, increase the power and cost budgets significantly, making it uneconomical for short-distance communications. To mitigate these issues, low-loss dielectric channel-based interconnects have been investigated and demonstrated. However, all the design reported are all for point-to-point configurations, not suitable for multi-drop distributed architectures.Besides CMOS transmitters and receivers, advanced spatial multiplexing schemes are fully investigated and architectures of wireline communication system at sub-THz/THz are selected according to the application scenarios. This dissertation also investigates the most used passive and active, on-chip and off-chip components, circuit modeling, layout optimization, and design strategies, such as neutralization and power maximization methods.Two sub-THz interconnect systems, FDM based dual-band sub-THz interconnect and MDM multi-drop sub-THz interconnect, are proposed and demonstrated.A low-loss and wideband Si DWG coupled with a pair of diplexers is employed to support two highly isolated and low loss sub-channels simultaneously. The proposed sub-THz interconnect achieves the energy efficiency of 1.58 pJ/b with the aggregate data rate of 22.6 Gb/s and BER better than 1e-12. It demonstrates the record bandwidth density of 150.7 Gb/s/mm2. Channelization provides a venue to boost the interconnect key metric of bandwidth density by taking full advantages of the abundant THz spectrum resource.The theory of DWG mode coupler is derived and explained, and it can guide the multi-mode multi-drop waveguide design and provide optimization strategies effectively. Then a multi-drop sub-THz interconnect system is demonstrated, enabling three simultaneous logical channels for E11^y, E21^y and E31^y mode and supporting data rates of 24 Gb/s, 22 Gb/s and 19 Gb/s, respectively, with the BER better than 1e-12. The demonstrated aggregate data rate of the three channels is 65 Gb/s with the energy efficiency of 1.6 pJ/b. To the authors’ knowledge, This is the first time to demonstrate multi-mode multi-drop DWG based interconnect. One note to make is that although the demonstration channel length is 5.2 cm, this is due to the size constraint of the wafer used to fabricate the channel. This interconnect system can be readily extended to the meter range due to the channel ultra-low loss feature. Furthermore, it can also scale to more modes to support more logic channels per physical link and can be extended to multi-dimension, two-/three- dimension, interconnect systems. Besides, with more advanced semiconductor technologies for active circuits, the data rate per channel will be further increased. Therefore, we believe that demonstrated multi-mode multi-drop sub-THz interconnect systems open a new path with high potentials to complement the existing electrical and optical interconnect to address the challenging meter range wireline communication scenarios.

Advanced achievements in the area of RF circuit design led to a significant increase in availability of wireless communications in everyday life. However, the rapid growth in utilizing the RF equipment has brought several challenges in different aspects of RF circuit design. This has been motivating researchers to introduce solution to cope with these challenges and further improve the performance of the RF circuits. In this dissertation, we focus on the improvements in three aspects of the circuit design. High temperature and temperature compensated transmitter design, ultra-low phase noise signal generators, and compact and low complexity polar transmitter design. Increase in the ambient temperature can impact the performance of the entire communication system. However, the RF hardware is main part of the system that is under the impact of the temperature variations in which it can change the characteristics of the individual building blocks of the RF chain. Moreover, transistors are the main elements in the circuit whose performance variation must be consider when the design target is compensating the temperature effects. The influence of the temperature variation is studied on the transistors and the building blocks in order to find the most effective approaches to compensate these variations and stabilize the performance of the RF chain at temperatures up to 220 C. A temperature sensor is designed to sense these variations and adjust the characteristics of the circuit components (e.g. bias voltages), accordingly. Further, a new variable gain phase shifter (VGPS) architecture is introduced toward minimizing the temperature impact on its performance in a phased-array transmitter architecture. Finally, a power amplifier as the last stage in a transmitter chain is designed and the variation in its performance with temperature is compensated through the VGPS stage. The transmitter is prototyped to evaluate its performance in practice. Another contribution of this dissertation is to introduce a novel voltage-controlled oscillator (VCO) structure to reduce the phase noise level below state-of-the-art. The noise to phase noise mechanism in the introduced doubly tuned oscillator is studied using linear time-variant (LTV) theory to identify the dominant noise sources and either eliminate or suppress these noise sources by introducing effective mechanism such as impedance scaling. The designed VCO is fabricated and measurement results are carried out that justified the accuracy of the analyses and effectiveness of the introduced design approach. Lastly, we introduce a compact and simple polar transmitter architecture. This type of transmitters was firstly proposed to overcome the serious shortcomings in the IQ transmitters, such as IQ imbalance and carrier leakage. However, there is still several challenges in their design. We introduce a transmitter architecture that operates based on charge to phase translation mechanism in the oscillator. This leads to significantly reduction in the design complexity, die area, and power dissipation. Further, it eliminates a number of serious issues in the design such as sampling rate of the DACs. comprehensive post-layout simulations were also performed to evaluate its performance.

With the emergence of new IOT and mobile applications, there has been an ever-increasing demand for high-data-rate wireless communication and high-resolution sensing. Researchers have put an extensive e ort to push the operating frequency of the communication and sensing systems. Sub-Terahertz (Sub-THz) band offers a wide unlicensed bandwidth that plays a critical role in the realization of high-speed wireless communication links. In addition, THz waves benefit from short wavelengths putting them at advantage compared to lower frequency bands for sensing and short-range high-resolution radars. Considering that current commercial THz systems are costly and bulky, developing these systems in standard silicon technologies is vital to lower the cost. In addition, this enables the integration of THz systems with other circuit blocks to implement a compact solution. THz generation in standard silicon technologies faces various challenges, including the limited speed of transistors. Since conventional techniques in the RF domain are not practical in the THz band, researchers have proposed new techniques to tackle the limitations of THz generation in silicon. Despite recent advancements, state-of-the-art THz systems still suffer from lower efficiency and low radiated power.This study proposes a novel technique based on PIN diode reverse recovery to improve the power, bandwidth, and efficiency of the generated THz waves. Using the concept of reverse recovery, a PIN-diode-based pulse radiator is introduced that generates pulses with 1.7-ps Full Width at Half Maximum (FWHM). In the frequency domain, the generated pulses correspond to a frequency comb. The tones of the frequency comb are received using a harmonic mixer in the frequency range 220-1125 GHz. On the receiver side, a low-power heterodyne frequency comb receiver using Schottky Barrier Diode (SBD) is demonstrated.The receiver is used in conjunction with the broadband pulse radiator to implement a dual-comb spectroscopy system operating up to 550 GHz. By extending the idea of PIN reverse recovery into Continuous-Wave (CW) domain, a PIN diode-based CW 2�3 array source is designed that radiates at 430 GHz with 18.1-dBm Effective Isotropic Radiated Power (EIRP). Finally, the custom-built THz chips are employed for different applications, including micro-Doppler sensing of sound vibrations, long-distance THz communication, plasma physics characterization, imaging, and gas spectroscopy. My research on THz circuit design and techniques has resulted in innovations and advancements in the THz field by introducing new techniques for broadband efficient THz generation in low-cost silicon technologies. The proposed techniques pave the way for utilizing THz systems for different applications in applied physics, healthcare, and networks.

Abstract: A Gaussian pulse generator circuit is a component of an ultra-wideband transceiver (transmitter and receiver) circuit that generates a narrow pulse for imaging, detecting, and various other applications. In UWB transceivers Gaussian pulse is always converted to a Monopulse to be DC-free and more compatible for transmission via an antenna. This Monopulse is created using Avalanche transistors as discrete switches and a differential CMOS transistor in 65 nm technology as an integrated circuit. Discrete switches generate high amplitude voltage with a moderate pulse width, improving the detection range in UWB transceivers. However, using a 65 nm integrated circuit (IC) instead of a discrete circuit can capture a sharper pulse with less pulse width, increasing the range resolution. The first design is consists of three-stage Avalanche transistors, to increase the amplitude of Gaussian pulse by a factor of three. The final Monopulse is created by a balun that subtracted two Gaussian pulses, which have different phases. In this design, the final Monopulse is connected to the antenna and sent by the transmitter circuit. After receiving the transmitted signal and analyzing the data by the computer, the buried object in 45 cm depth is detected and separated from the sand. The second design consists of a differential pair circuit that generates a sharp pulse due to the voltage difference between its two inputs. The desired Monopulse is formed by sharpening this pulse using an inverter chain and mixing three pulses with different phases. These Gaussian pulse generator systems can be utilized in different applications, such as detecting buried objects, underwater imaging, through-wall imaging, diagnosing cancer glands without using harmful methods like an X-ray beam, etc.

Test and evaluation (TandE) is a critically important step before in-the-field deployment of radio-frequency (RF) hardware in order to assure that the hardware meets its design requirements and specifications. Typically, TandE is performed either in a lab setting utilizing a software simulation environment or through real-world field testing. While the former approach is typically limited by the accuracy of the simulation models (particularly of the anticipated hardware effects) and by non-real-time data rates, the latter can be extremely costly in terms of time, money, and manpower. To build upon the strengths of these approaches and to mitigate their weaknesses, this work presents the development of an FPGA-based TandE tool that allows for real-time pseudo-random aggregate signal generation for testing RF receiver hardware (such as communication receivers, spectrum sensors, etc.). In particular, a framework is developed for an FPGA-based implementation of a test signal emulator that generates randomized aggregate spectral environments containing signals with random parameters such as center frequencies, bandwidths, start times, and durations, as well as receiver and channel effects such as additive white Gaussian noise (AWGN). To test the accuracy of the developed spectrum generation framework, the randomization properties of the framework are analyzed to assure correct probability distributions and independence. Additionally, FPGA implementation decisions, such as bit precision versus accuracy of the generated signal and the impact on the FPGA's hardware footprint, are analyzed.This analysis allows the test signal engineer to make informed decisions while designing a hardware-based RF test system. This framework is easily extensible to other signal types and channel models, and can be used to test a variety of signal-based applications.

Wireless mobile networks are expected to become progressively more prevalent in the future society, connecting billions of populations across the globe and an even higher number of intelligent devices scattered in the environment. Moreover, the supported data rate on mobile devices keeps increasing with the deployment of next generation network infrastructure, e.g. 5G network, and upgrades on existing infrastructures. Consequently, enormous amounts of data traffic will be generated on a daily basis and data exchange between base stations and the backbone network through conventional backhaul links will quickly become a bottleneck. On the other hand, mobile terminals, the elemental building blocks of all mobile networks continue to be hindered by ever-increasing interference blocking problems in a more and more congested environment, both spectrally and spatially. This dissertation aims to study potential solutions for the aforementioned two major issues in mobile networks from a transceiver circuit design perspective.In the first part of this dissertation, a direct modulation high-order QAM transmitter architecture is proposed and analyzed for mm-wave high-speed wireless links, targeting for applications such as wireless backhaul. The daunting and costly task of designing integratedhigh-speed-resolution digital-to-analog interface and complicated digital back-end in conventional architectures is completely avoided. Link performance, cost and level of integration are greatly improved as a result. Prototype transmitter has been designed, fabricated andmeasured to verify the proposed concept. Operating at 115-GHz carrier frequency, the transmitter achieves a 20Gbps data rate in a short-range wireless link using 16QAM modulation. Error vector magnitude (EVM) was measured to be −15.8 dB at a modulated output power of +1 dBm. The transmitter consumes 520 mW of power and occupies 3.17 mm2 of active area in a 180-nm SiGe BiCMOS process.In the second part, the mobile terminal blocking problem is addressed. While benefiting from superior linearity, blocker-tolerance and high-Q programmable selectivity brought forth by N-path filtering technique, the common problem of elevated local oscillator (LO) leakage in prior work is significantly mitigated in the proposed receiver design to comply with cellular standards. The design of the proposed receiver is analyzed in great details. The prototype receiver was measured to be highly linear with low noise figure and LO leakage. Out-of-band 2nd and 3rd order input-referred-intercept-point (IIP2 and IIP3) reaches +60 dBm and +14 dBm, respectively. Small-signal noise figure was measured to be below 2.5 dB and degrades by 4.5 dB in the presence of a 0 dBm blocker at 80 MHz offset. The LO leakage was kept under −80 dBm up to 2 GHz.

Pulse width modulation (PWM) is an attractive signaling method since it can represent an analog signal while using a discrete-level signal, and is hence more robust to amplitude-noise than a purely analog signal. In addition, PWM can be utilized with switching circuits and thus can benefit from performance and area enhancements that result from process scaling. Receiver and transmitter architectures employing PWM are presented in this work. Architectures to generate high-frequency PWM for representing a wide-bandwidth modulated signal are proposed. A harmonic rejection (HR) receiver that utilizes PWM to implement a sinusoidal local oscillator (LO) with intrinsic HR is demonstrated in Chapter 2. The PWM-LO is employed in a switching mixer. The receiver can be configured to provide additional HR by employing multiphase paths, with appropriate baseband gain coefficients. The PWM generator employs parallel delay-locked loops to implement a three-level natural-sampling dual-edge PWM sinusoidal LO signal, with rejection of the third, fifth and seventh LO harmonics. Gain control using LO-path pulse-width control is demonstrated. The design is implemented in a 40-nm CMOS process. The measured receiver gain with HR is 26.4–30.1 dB in a multi-phase LO configuration and 28–31.8 dB in a single-phase configuration. The double-sideband noise figure at peak gain is 5.8 dB. The design demonstrates worst-case HR3 and HR5 ratios of 47 and 49 dB without calibration for f[subscript LO] = 100 MHz in the multi-phase configuration, with a total power dissipation of 41.1 mW. With calibration, a single-phase peak harmonic rejection ratio (HRR) greater than 73 dB for the third, fifth, and seventh LO harmonics is demonstrated. Gain dependence of the HRR on input signal amplitude is studied. In Chapter 3, a HR downconverter that can provide higher PWM-LO frequencies, in the range of approximately a GHz, is proposed. The approach employs current-mode operation, and significantly improves performance for narrow pulse-widths, which allows for high-frequency operation. The use of an input transconductor-cell with switches in the signal-path decreases the sensitivity of the HRR to harmonic power level. The design is simulated in a 65-nm CMOS technology, and shows HRRs of nearly 60-70 dB for the 3rd and 5th harmonics, with a 1 GHz LO, over a range of harmonic power levels, and rise and fall times of the PWM waveform. In Chapter 4, a delay-locked loop (DLL) based RF-PWM generator is proposed that can provide RF-PWM in response to broadband signals. The approach can be utilized in a Cartesian transmitter in combination with a switching output stage. The proposed transmitter architecture is verified in a macro-model simulation, using a signal bandwidth of 40 MHz, at a carrier frequency of 2 GHz. In Chapter 5, a Cartesian quadrature power amplifier (QPA) architecture that employs RF-PWM with a switched-capacitor (SC) class-D output stage is described. IQ combining is performed using the SC output stage. Amplitude modulation is performed using RF-PWM, instead of using capacitor ratios in the switched-capacitor combiner, thereby avoiding quantization noise. Outphasing is utilized to synthesize RF-PWM, which alleviates distortion due to narrow pulse-widths in the switching stage. Loss mechanisms in the SC combiner are identified and analyzed. AM-to-AM distortion in the proposed design arises due to resistance variation of the class-D switches. This distortion mechanism is analyzed and demonstrated by means of simulation in a 65-nm CMOS technology. The final part of the thesis (Chapter 6) introduces a Cartesian transmitter that uses of combination of the DLL-based outphasing modulator and switched-capacitor combiner for implementation of a wideband transmitter. An outphasing signal is generated to implement RF-PWM. Full amplitude modulation is achieved while varying the duty-cycle of the RF-PWM generator from 25%-75%, which significantly relaxes the narrow-pulse limitation observed in PWM signaling. The use of the phase detectors synchronized to the two clocks whose phase difference is in quadrature at the PWM frequency enhances the frequency response of the output of the transmitter. The IQ combiner employs a switched-capacitor design, described in Chapter 5. The Cartesian transmitter is implemented in a 65-nm CMOS process. The measured peak output power of the transmitter is 15.5 dBm and the design is verified with digitally-modulated signals with a bandwidth of up to 160 MHz

Wireless power transfer (WPT) has attracted great attention from industry and academia due to high charging flexibility. However, the efficiency of WPT is lower and the cost is higher than the wired power transfer approaches. Efforts including converter optimization, power delivery architecture improvement, and coils have been made to increase system efficiency.In this thesis, new power delivery architectures in the WPT of consumer electronics have been proposed to improve the overall system efficiency and increase the power density.First, a two-stage transmitter architecture is designed for a 100 W WPT system. After comparing with other topologies, the front-end ac-dc power factor correction (PFC) rectifier employs a totem-pole rectifier. A full bridge 6.78 MHz resonant inverter is designed for the subsequent stage. An impedance matching network provides constant transmitter coil current. The experimental results verify the high efficiency, high PF, and low total harmonic distortion (THD).Then, a single-stage transmitter is derived based on the verified two-stage structure. By integration of the PFC rectifier and full bridge inverter, two GaN FETs are saved and high efficiency is maintained. The integrated DCM operated PFC rectifier provides high PF and low THD. By adopting a control scheme, the transmitter coil current and power are regulated. A simple auxiliary circuit is employed to improve the light load efficiency. The experimental results verify the achievement of high efficiency.A closed-loop control scheme is implemented in the single-stage transmitter to supply multiple receivers simultaneously. With a controlled constant transmitter current, the system provides a smooth transition during dynamically load change. ZVS detection circuit is proposed to protect the transmitter from continuous hard switching operation. The control scheme is verified in the experiments.The multiple-reciever WPT system with the single-stage transmitter is investigated. The system operating range is discussed. The method of tracking optimum system efficiency is studied. The system control scheme and control procedure, targeting at providing a wide system operating range, robust operation and capability of tracking the optimized system efficiency, are proposed. Experiment results demonstrate the WPT system operation.

Metasurfaces are sub-wavelength scale (lambda

Thanks to a small wavelength (large bandwidth) combined with a low loss transmission window around 94 GHz and 120 GHz, the 75-120 GHz frequency band in millimeter wave (mm-wave) provides a promising opportunity for high data rate long range wireless communications and high-resolution imaging systems. Large-scale phased arrays have been exploited in such application for their beam forming and null steering capabilities, resulting in high directivity and improved SNR. But growing DC power consumption (Pdiss) in such large scale arrays has become an on-going concern along with noise, linearity and phase resolution trade-offs in current phased array architectures. To address these issues, we propose a power efficient phase shifter (PS) architecture based on quadrature hybrid coupler, which leverages the benefits of conventional active and passive PSs at mm-wave. The phase shifter has low loss, resulting in low power dissipation and the power domain phase interpolation by the quadrature hybrid gives low phase error and high linearity. We design W-band (90-100 GHz) phased array transmit and receive (T/R) modules in 130 nm SiGe BiCMOS technology based on the proposed PS and our measurements show high power efficiency with the lowest power consumption at W-band to our knowledge (18mW and 26mW power dissipations at receiver (Rx) and transmitter (Tx) front-ends respectively). Rx shows 23 to 25 dB peak gain, 6 to 9.3 dB NF and Tx can deliver upto 7 dBm output power with 18% power efficiency. Moreover, our PS can achieve 5-bit phase resolution with

With increasing data rates and new communication standards owing to substantial advancements in digitizing and signal processing capabilities over the last century, the radio spectrum is increasingly becoming a finite and expensive resource. Furthermore, radar systems and 5G communication systems have revealed the need for gigahertz-frequency signal generation with flexible frequency planning and minimal spurious emissions. Advanced digital-to-analog converters (DACs), along with associated filtering, are critical enablers of these new systems and play a key role in meeting stringent system requirements. In conventional implementations, however, high quality filters are specific to one frequency band thereby limiting their operational agility. Therefore, a DAC architecture that removes undesired image replicas, mixer sidebands, and harmonic nonlinearities is an essential component for flexible frequency synthesis as it allows for reduced filtering requirements while enabling new software-defined transmitter techniques.This dissertation aims to provide a quantitative study and analysis of a poly-phased, time-interleaved Nyquist radio frequency digital-to-analog converter (Poly-TI-RF-DAC) for use in spectrum-agile and software-defined transmitters. Beginning with the fundamental understanding of high-speed DAC capabilities and limitations, the mathematical and behavioral analyses give insight into the signal, sideband, and image replica locations of the proposed architecture. Additionally, the use of a mixing DAC as the core structure is discussed along with how nonlinearities can be canceled with the appropriate choice of frequency planning.

Silicon photonic interconnects hold great promise in meeting the high bandwidth and low-energy demands of next-generation interconnects. System-level driven electronic-photonic co-design is the key to improving the bandwidth density and energy efficiency. In this study, a comprehensive co-optimization framework is developed for high-speed silicon photonic transmitters utilizing compact models and a detailed optical simulation framework. Given technology and link constraints, microring and Mach-Zehnder transmitter designs are optimized and compared based on a unified optical phase shifter model. Non-return-to-zero (NRZ) and pulse-amplitude-modulation-4 (PAM-4) modulation schemes are analyzed and compared for microring-based transmitters. Using the co-design approach, a monolithic 40Gb/s optical NRZ transmitter based on microring modulators is designed and demonstrated in zero-change 45nm CMOS SOI process. Electronic-photonic co-design with the high swing driver enables this transmitter to achieve total energy efficiency of 330fJ/b and the photonics and modulator driver area bandwidth density of 6.7 Tb/s/mm2. This dissertation also discusses the design and demonstration of the first full silicon photonic interconnect on a 3D integrated electronic-photonic platform. These results make the microring-based silicon photonic transceivers an attractive solution for the next-generation inter and intra-rack photonic interconnects. Finally, a short-reach laser-forwarding coherent link architecture is proposed to further improve the energy efficiency of silicon photonic interconnects. The key concepts of the proposed architecture are verified experimentally with microring-based silicon photonic transmitters. The architecture saves the laser power by 6-7.5x and could enable complex modulation schemes for the future short-reach optical links.

In this thesis, circuit techniques pertinent to low power CMOS integrated radio design compatible with IEEE 802.15.6 standard are presented. Low power radios are in increasing demand with the advent of an era of the Wireless Body Area Networks and Internet of Things. The performance of the proposed techniques has been verified by fabricating them in two standard CMOS processes: TSMC's 65nm and IBM's 130nm process. These designs are compatible with all the channels defined in IEEE 802.15.6 standard in the frequency range of 2.36 GHz to 2.484 GHz. First, an IEEE 802.15.6 compliant 2360-2484MHz multiband transmitter is presented that digitally multiplexes the appropriate phases from an 800MHz poly-phase filter output to generate π/4 DQPSK signals at 2.4GHz using injection locking. Modulation at 1/3rd the RF frequency reduces the transmitter power consumption and enables channel selection using an integer N PLL running at 800MHz. The modulation technique does not require phase calibration and resolves the problems of traditional injection lock based modulators. The prototype transmitter implemented in IBM's 130nm technology consumes 2.4mW while delivering -10dBm RF power at the TX output resulting in an energy efficiency of 2.5nJ/bit at 1.2Mbps raw data rate. The measured RMS EVM for π/4 DQPSK modulation is 3.21%. Next, a 2.3-2.5 GHz low-power low-noise 0.7 V mixer-first RF frontend for an IEEE 802.15.6 narrowband receiver is presented which uses frequency translated mutual noise cancellation based on passive coupling. Unlike traditional noise cancelling techniques we perform symmetrical noise cancellation of a fully differential structure where each path cancels the noise of the other at IF. This prototype design realized in TSMC's 65nm CMOS tackles the noise figure and power consumption problems of sub 1V mixers. The figure of merit (FOM) is 10 dB higher and the power consumption is 194 μW which is 0.5X lower than the state of the art. The local oscillator (LO) power used is only -14 dBm. Next, a 0.7V 2.3-2.5GHz ultra low power low noise amplifier (LNA) suitable for WBAN and Internet of Things (IoT) is presented which uses 1:3 balun at the frontend to achieve mutual noise and non-linearity cancellation as well as power reduction. In this technique the mutual coupling between the two secondary coils of the balun enable noise and non-linearity cancellation of both the main and the auxiliary path and therefore power consumption in the auxiliary path can be reduced. The step up balun reduces power by relaxing the transconductance (gm) requirement for matching of the input transistors. The circuit further exploits current reuse and gm boosting to reduce power consumption. This technique improves the noise figure by 2dB and IIP3 by 4dB while consuming 520μW of power. The FOM is 28.5dB which is 8dB better than the state of the art. The design is fully integrated with onchip balun and has been implemented in TSMC's 65nm technology. Finally, we present a fully integrated complete transmitter and receiver system with built in frequency synthesizer compatible with IEEE 802.15.6 standard (2.3-2.4 GHz) which has approximately 3X better energy efficiency than the state of the art in both transmit and receive. The synthesizer uses 7th harmonic injection locking to drastically reduce power. The transmitter uses an energy efficient fully programmable digital power amplifier with onchip matching network. The receiver has a zero IF I/Q architecture with zero power passive front end, energy efficient class AB baseband amplifiers with programmable gain/corner and a one bit comparator based ADC to substantially reduce power. The power consumption of the TX is 590μW, that of RX is 510μW and that of the synthesizer is 840μW. The design has been implemented in IBM's (now GF's) 130nm technology.

Wireless standards for high data-rate communications typically employ complex modulation schemes that have large peak-to-average power ratios (PAPR), along with a significant bandwidth requirement. Transmitters for such applications often employ off-chip power amplifiers (PAs), that are typically operated in back-off, such that the peak output power is less than the output 1-dB compression point (P1dB), in order to minimize distortion. In mobile systems, architectures that can enhance the linearity of the transmit chain are highly attractive since these can reduce the PA's back-off requirement, which helps to enhance efficiency. In this dissertation, linearization techniques for mobile transmitters are explored. A Cartesian feedback-feedforward transmitter is proposed for linearity enhancement. The transmit path in the architecture is placed in a Cartesian feedback loop. The feedback error signal is applied to a Cartesian feedforward path for further linearity improvement. Linearity of the feedback-feedforward system is analyzed by using a Volterra series representation. System simulations using two-tone signals and modulated signals are also presented and are used to verify the linearity enhancement provided by the proposed architecture. A prototype transmitter IC that employs the Cartesian feedback-feedforward approach is implemented in a 0.13 μm CMOS process. Design considerations for critical transmitter circuits are discussed. A proof-of-concept Cartesian feedback-feedforward architecture that includes the prototype IC and external components is demonstrated. The implementation allows for a 8.7 dB improvement in the adjacent channel leakage ratio (ACLR), compared to an open-loop transmitter, for an output power of 16.6 dBm at 2.4 GHz while employing a 16-QAM LTE signal with 1.4 MHz bandwidth. The linearity of the Cartesian feedback-feedforward system is found to depend primarily on the loop gain of the Cartesian feedback and the linearity of the Cartesian feedforward path, which introduces a trade-off with power consumption. To enhance the linearity of the Cartesian feedback-feedforward transmitter even further within the Cartesian feedback loop, two modified Cartesian feedback-feedforward architectures are explored. System simulations show that both modified configurations can help to enhance linearity compared to the above Cartesian feedback-feedforward transmitter.

In recent years, significant improvements in semiconductor technology have allowed consistent development of wireless chipsets in terms of functionality and form factor. This has opened up a broad range of applications for implantable wireless sensors and telemetry devices in multiple categories, such as military, industrial, and medical uses. The nature of these applications often requires the wireless sensors to be low-weight and energy-efficient to achieve long battery life. Among the various functions of these sensors, the communication block, used to transmit the gathered data, is typically the most power-hungry block. In typical wireless sensor networks, transmission range is below 10 meters and required radiated power is below 1 milliwatt. In such cases, power consumption of the frequency-synthesis circuits prior to the power amplifier of the transmitter becomes significant. Reducing this power consumption is currently the focus of various research endeavors. A popular method of achieving this goal is using a direct-modulation transmitter where the generated carrier is directly modulated with baseband data using simple modulation schemes. Among the different variations of direct-modulation transmitters, transmitters using unlocked digitally-controlled oscillators and transmitters with injection or resonator-locked oscillators are widely investigated because of their simple structure. These transmitters can achieve low-power and stable operation either with the help of recalibration or by sacrificing tuning capability. In contrast, phase-locked-loop-based (PLL) transmitters are less researched. The PLL uses a feedback loop to lock the carrier to a reference frequency with a programmable ratio and thus achieves good frequency stability and convenient tunability. This work focuses on PLL-based transmitters. The initial goal of this work is to reduce the power consumption of the oscillator and frequency divider, the two most power-consuming blocks in a PLL. Novel topologies for these two blocks are proposed which achieve ultra-low-power operation. Along with measured performance, mathematical analysis to derive rule-of-thumb design approaches are presented. Finally, the full transmitter is implemented using these blocks in a 130 nanometer CMOS process and is successfully tested for low-power operation.

Switched-mode RF power amplifiers (PAs) under bitstream modulations such as bandpass or envelope delta-sigma modulations have received increasing attentions over the past years. They have been proposed to overcome a trade-off between linearity and efficiency with an idea to discretize analog envelope from a complex modulation signal into discrete driving points for high efficiency operation. Such amplifiers offer enhanced efficiency under power back-off conditions with pulse train waveforms yet maintain linearity in amplification through digital coding and modulations. The quantization noise generated during a discretization process, however, is a challenge to be rejected properly and restore desired signal.This work presents a switched-mode PA based on the pulsed load modulation (PLM) technique with multi-level envelope delta-sigma modulation (EDSM) to realize broadband efficient amplification of non-constant-envelope signals. PLM technique modulated load impedance to be optimized for dynamic power range and maintained optimum efficiency over 6 dB back-off. Multi-level EDSM introduced additional transition levels and reduced quantization noise power with improved signal to noise ratio.In addition, active noise filtering scheme is proposed with a potential to replace an external high-Q passive bandpass filter in delta-sigma modulation. Multiple PA units were driven by identical signal with different phase. Challenged quantization noise power was suppressed by multi-path combining filtering.The proposed transmitters were demonstrated at X-band using GaN devices. Both 2-level and 3-level EDSM techniques were tested and compared. Two channel active noise filtering is also presented with regard to their quantization noise levels and power efficiencies.

A new up/down converter system for LTE-A transmitter was presented. The chosen architecture eliminates the problem of LO-RF feedthrough in heterodyne transmitters. Using passive mixers and high bandwidth circuitry, acceptable gain flatness and linearity is achieved, making this system suitable for polar modulation. The circuit incorporating a number of elements in the system was fabricated in a 0.18um BCD process that provides both high-voltage MOSFETS as well as low-voltage, high-speed MOSFETS, allowing implementation of both the PA and converter onto a single chip.

The last decade has witnessed a tremendous growth in wireless communications. Consumer demands for battery-operated mobile devices with versatile, high data-rate communication capabilities that are of low cost, small form-factor and long operating cycle have motivated the research on fully-integrated, back-off-efficient and coexistence-friendly wireless transceivers in CMOS VLSI technology. However, the full integration of an efficient CMOS power amplifier (PA) into such a transceiver is still among the most difficult challenges towards a true System-On-Chip (SOC) solution. This thesis investigates the PA efficiency enhancement techniques for a complete power transmitter system that is fully-integrated and coexistable. Direct digitally modulated transmitter architecture has been identified as one of the most promising solutions to the above challenges. Within such a transmitter, the PA efficiency is able to back off from a high peak efficiency at least with class-B characteristic; meanwhile, the transmit linearity can be more easily improved by digital predistortion due to the direct digital modulation scheme. To validate such a promising architecture, we have built a fully-integrated CMOS digital power transmitter for the IEEE 802.11g 54Mbps application. System-level considerations and design choices are presented with an aim for low out-of-band noise and good transmit linearity. As the core of the transmitter, the RF switching PA is designed for high efficiency with minimum number of on-chip passives that only exercise an accurate control over fundamental and second-harmonic terminations. The class-B efficiency back-off characteristic is further improved by a dynamic impedance modulator which boosts the PA drain impedance at a low instantaneous envelope level. Open-loop phase interpolator based topology is used for the polar phase modulator, which achieves wideband phase modulation with competitive power consumption. Digital baseband filtering is fully optimized at both the algorithm and the hardware level, which offers larger than 60dB attenuation on the close-in spectral images with reduced filter complexity. The prototype has been implemented in a 65nm bulk CMOS technology and has demonstrated a combination of good output power, overall efficiency and spectral purity with a very high level of system integration.

The objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation.

During past two decades a variety of SAW based wireless sensors were invented and research is still in progress. As different frequencies, varied bandwidths, coding techniques and constantly changing post processing algorithms are being implemented, there is a constant need for a universal and adjustable synchronous communication system able to interrogate new generations of SAW sensors. This thesis presents the design of a multiple FPGA based communication system with an operational frequency range of 450MHz-2.2GHz capable of producing user programmed modulated signal. The synchronous receiver is designed to have interchangeable chip, replacement of which would allow adjustment of the receiver’s bandwidth. Within this paper the performance of the system is only evaluated at 915MHz centered 20MHz bandwidth region. An OFC temperature sensor was interrogated. Post-processing algorithms, measurement results, and proposals for the future use of the system are presented. Detailed overview of the structure and performance of every functional block along with design considerations are analyzed. Previously designed Matlab based software was adapted for post processing of the received signal. New software with simplified GUI was designed for programming of the desired signal.

Remote keyless entry systems gained prominence with the advancement in the wireless communication technological applications. Early remote keyless entry systems operate by transmitting a unique identification key from transmitter to the receiver. Security has become a major concern for these systems due to cloning of the key. Modern keyless entry systems make use of advanced theft control methods that generate rolling codes. The main purpose of this research was to implement a secure wireless encryption protocol that generates rolling codes using cryptography. This implementation makes use of the Advanced Encryption Standard (AES) and its Cipher-based Message Authentication Code (CMAC) mode of operation for transmitter authentication. A minimal implementation of this protocol is done for use in smaller devices. A simple and secure learning method was used for introducing new transmitters to the receiver. The transmitter and receiver are programmed using PIC24 microcontrollers and C30 compiler. Two 16-bit microprocessors are used to implement the hardware. The microcontroller devices are programmed for minimal power consumption. A working implementation of the transmitter and receiver programs written in C language is included in the appendix.

The goal of this thesis is to improve the reliability of a predistortion testbed which was developed for an educational lab in a previous Master thesis. The reliability of a system is one of the main concerns in any engineering design. Good engineers have to be able to provide designs which are both robust and reliable. Moreover, practicality has to be taken into account. It is not sufficient to have a system that can complete the task but is neither reliable nor practical. In Summary the goal for any designer should be to make the system designed robust, reliable, user friendly, easy to set up, and cost efficient. Therefore even though the previous predistortion linearization design was working properly, it lacked in reliability. That is one of the main problems when a design relies solely on analog components. Analog components are bound to exhibit mismatches and to be sensitive to the outside environment. In order to handle all of the problems mentioned, a digital system will be introduced as the solution of the reliability and tuning problem. The advantages of digital electronic systems are legendary. Not only is it easy to manipulate but also is produces very consistent results. One of the goal of this thesis is to replace the dc offset control circuit of a baseband circuit in the educational testbed from analog to digital. However, the robustness will come at a price. The digital system has to be accompanied with controlling software. The control software provided with the circuit blocks acquired was used for the new design to work properly. Two major building blocks were switched to digital control: (1) the variable gain amplifiers for conditioning the baseband signals and (2) the variable digital potentiometers for the LO leakage control. The variable gain amplifiers also perform as BALUN signal converters. That is, they generate differential signals from a single ended signal source. The digital potentiometers were used as a dc offset controller. The dc offset circuit developed rely on the fundamental concept of the voltage divider to generate the tuning voltages required by the IQ modulator. Buffer amplifiers were also implemented to avoid any loading effect as the tuning voltage is also used to bias the IQ modulator. A successful suppression of the LO leakage by up to 42 dB was demonstrated using this programmable dc offset circuitry.

The inability of radio frequency electromagnetic waves to propagate without attenuation in seawater has traditionally limited underwater communications to acoustics or tethered systems. High bandwidth optical communication systems have been demonstrated for terrestrial and space applications. There is growing interest to see if short range high bandwidth optical wireless systems can be made for the underwater environment. In this thesis we demonstrate a 1 Mbps optical wireless system using LEDs and PIN photodiodes that also incorporates capabilities for signal processing of the received data to be performed. Lasers and Photomultiplier tubes offer high performance, and are generally used in most underwater optical communication systems. However, these components are relatively expensive and can have large form factors. As an alternative solution the much cheaper and more compact LEDs and photodiodes are used as transmitters and receiver components. However, compared to a laser and PMT based system, such a system would be strongly disadvantaged in photon limited environments. If one assumes that photons actually reach the receiver, using signal processing techniques, optimized modulation formats, and error-correction coding, one expects that the range of the system can be extended. The development of a prototype system for the experimentation and verification of this proposition is the main motivation of this thesis. Small, compact transmitters using High Power LEDs and receivers using Si Photodiodes where the data can be digitally sampled such that signal processing techniques can be applied were constructed and demonstrated using a 12 foot, 1200 gallon tank that was also constructed for the project. It was shown that the LED and photodiode based system works well for short ranges, and that advantages can be obtained using digital signal processing. The applicability of this strategy to use digital signal processing techniques can be easily extended to higher performance Laser/PMT based systems.

This work presents the design of a low-power wireless transceiver optimized for use in deeply implanted biomedical devices. Potential operating frequencies were analyzed with respect to system limitations of power, size and complexity. It was reasoned that operation using low carrier frequencies provides high power efficiency while slightly increasing the size of off-chip antennas, and 125-kHz OOK and 27.12-MHz FSK were chosen for forward- and reverse-telemetry, respectively. Integrated telemetry circuits were designed to meet the power and data rate requirements for simple biomedical devices and the circuits were fabricated in the AMI 0.5-μm CMOS process. Test measurements have confirmed the functionality of the circuits, and have provided inspiration for future circuit redesign.

In modern high performance VLSI chips high bandwidth and high throughput are becoming increasingly important. Multi-Tb⁄s throughput is the current trend of high performance VLSI chips. This trend demands high speed, high density and low power I⁄Os. AC coupled interconnect (ACCI) has been demonstrated as a systematic approach to provide higher pin density, smaller transceiver design and lower power dissipation for high speed chip-to-chip communications. ACCI utilizes non-contact capacitor plates as signal pins which yields a much higher pin density than traditional solder bump pins. The coupling capacitors provide passive equalization, thus eliminating the need for costly traditional active equalization. This saves both power and area associated with the equalization circuitry used in a traditional transceiver. ACCI also saves significant power on the transmitter by using pulse signaling instead of traditional non-return-to-zero (NRZ) signaling The pulse receiver is one of the most important designs in ACCI. The pulse receiver is used at receiver front end to recover the NRZ signal from the small pulse signal. A complementary low swing pulse receiver was designed to allow greater attenuation and to accommodate smaller coupling capacitors and longer transmission lines (T-Lines). A test chip with a complete capacitively coupled serial link was designed; including random data generator, multi-phase DLL, serializer, transmitter, pulse receiver, clock and data recovery (CDR), deserializer and bit error rate (BER) tester. ACCI chip-to-chip communication was demonstrated through two 150fF coupling capacitors and a single end terminated 15 cm microstrip line on a FR4 board at 3Gb⁄s. A differential pulse receiver is proposed for ACCI bus. The design and measurements of the proposed 36Gb⁄s receiver which operated over the 6-bit wide ACCI bus were reported. Signal integrity issues associated with the ACCI bus, such as crosstalk and switching noise, are discussed. Simulation results demonstrated that a higher data rate over ACCI channel can be achieved with more advanced CMOS technologies.

Motivated by the overwhelming technology imperative to integrate radio frequency (RF) circuits along with digital baseband circuits on the same die, the fundamental objective of this research is to assess the potential of 90 nm CMOS technology for use in the RF transmit section of Wideband Code Division Multiple Access (WCDMA) cellular handsets while still meeting the exacting performance standards for the same. This thesis addresses the specific challenges associated with designing an upconverter for an integrated WCDMA transmitter implemented in 90 nm CMOS. The upconverter simultaneously performs quadrature modulation and direct upconversion of the baseband signal to the WCDMA transmit band located at (1920-1980) MHz. A double balanced mixer topology is used to perform frequency translation, with differential to single-ended conversion of the upconverted signal being effected by a current mirror at RF. To mitigate the crunch for voltage headroom, the upconverter design implements the baseband transconductor as a folded differential pair. This MOS differential pair transconductor is linearized based on ideas borrowed from the multi-tanh concept. At a rated RF output voltage of 60 mV (rms), the upconverter achieves an Adjacent Channel Leakage power Ratio (ACLR at ±5 MHz offset) of -56.1 dBc and an Alternate Channel Leakage power Ratio (ACLR at ±10 MHz offset) of -65.8 dBc. The conversion gain of each I and Q mixer is 0 dB, and the noise level in the WCDMA receive band at a +190 MHz offset is measured to be -139.5 dBc. While delivering this performance, the entire quadrature upconverter consumes a mere 1.7 mA from its nominal 1.2 V supply, thus proving to be an efficient and low-power design.

Orthogonal Frequency-Division Multiplexing (OFDM) is now regarded as a feasible alternative to the conventional single carrier modulation techniques for high data rate communication systems, mainly because of its inherent equalisation simplicity. Transmitter diversity can effectively combat multipath channel impairments due to the dispersive wireless channel that can cause deep fades in some subchannels. The combination of the two techniques, OFDM and transmitter diversity, can further enhance the data rates in a frequency-selective fading environment. However, this enhancement requires accurate and computationally efficient channel state information when coherent detection is involved. A good choice for high accuracy channel estimation is the linear minimum mean-squared error (LMMSE) technique, but it requires a large number of processing operations. In this thesis, a deep and thorough study is carried out, based on the mathematical analysis and simulations in MATLAB, to find new and effective channel estimation methods for OFDM in a transmit diversity environment. As a result, three novel LMMSE based channel estimation algorithms are evaluated: real time LMMSE, LMMSE by significant weight catching (SWC) and low complexity LMMSE with power delay profile approximation as uniform. The new techniques and their combinations can significantly reduce the full LMMSE processor complexity, by 50% or more, when the estimation accuracy loss remains within 1-2 dB over a wide range of channel delay spreads and signal-to-noise ratios (SNR). To further enhance the channel estimator performance, pilot symbol structures are investigated and methods for statistical parameter estimation in real time are also presented.

Bacteria thrive in diverse environments. Their ability to adapt to drastically changing environmental conditions stems in part from their widespread use of Two-component signal transduction systems (TCS). A TCS consists of two proteins, the transmitter and the receiver, that use a conserved phosphoryl transfer mechanism to regulate a biological process in response to environmental signals. Environmental signals control the transmitter's ability to phosphorylate and dephosphorylate its cognate receiver, and the phosphorylation state of the receiver determines its ability to elicit the proper response. Our studies of the paradigmatic NRII/NRI TCS of Escherichia coli revealed the mechanism of signal transduction through the transmitter NRII. Intracellular signals of nitrogen and carbon status control the ability of the PII protein to regulate NRII. PII inhibits the kinase activity and activates the phosphatase activity of NRII. Each subunit of the homodimeric NRII contains three domains; an unconserved N-terminal domain, and a central and C-terminal domain that are conserved among the transmitter family. Cross-linking studies with purified components demonstrated that the binding of PII to NRII depended on small molecule effectors that control the ability of PII to regulate NRII. The purified cross-linked complex, which exhibited phosphatase activity, appeared to consist of a PII trimer linked to a single subunit of the NRII dimer. The isolated C-terminal domain of NRII was sufficient for PII-cross-linking. A genetic selection and screening procedure identified many single amino acid substitutions in NRII that resulted in diminished phosphatase activity, while having little effect on kinase activity. The mutations mapped throughout all three domains of NRII including two regions of the C-terminal domain, the ATP-lid and a surface on the back of this domain. A mutation in the latter surface resulted in severely diminished PII-binding. Using purified components, heterodimers were formed that contained subunits from different phosphatase-deficient NRII proteins. Certain combinations of mutations resulted in trans-intramolecular complementation partially restoring phosphatase activity. The pattern of complementation was consistent with a model where the phosphatase activity utilizes a PII-binding site from one subunit of the NRII dimer, a central domain from the same subunit, and a C-terminal domain ATP-lid from the opposing subunit.

The use of multiple antennas at the transmitter as well as at the receiver can greatly improve the capacity of a wireless link when operating in a rich scattering environment. In such an arrangement all transmitting antennas radiate in the same frequency band so the overall spectral efciency becomes very high. Such a multiple antenna scheme, popularly known as Multiple Input Multiple Output (MIMO) has potential application in wireless local area networks (WLAN) and cellular micro-cells. One reason is that the WLANs and other short range wireless systems often operate in an indoor environment, which offers rich scattering. The other reason is the demand for higher data rates in cellular and WLAN systems to cater for multimedia services. Recently researchers have proposed di erent architectures for materializing the potential of the MIMO scheme. VBLAST (Vertical-Bell Labs Space Time) is a popular architecture that will play an important role in future standardizations. Furthermore, different decoding methods have been proposed for VBLAST. The SVD (Singular Value Decomposition) based system is envisioned as a highly effective MIMO technique in a TDD (Time Division Duplex) framework. Such a system operates by adapting the constellation size across different subchannels. In this work we study the VBLAST and SVD architectures and compare the perfor- mance and computing power requirement of these architectures. Also in this study a new effcient decoding method for the VBLAST architecture is proposed. The original VBLAST decoding method relies on the repetitive computation of the pseudoinverse of the channel matrix. Alternatively, there are methods based on the QR decomposi- tion, the matrix square root etc. Our new decoding method is based on a relatively less known matrix decomposition, the Polar Decomposition. The new method requires less computation and has several other advantages like the possibility of incremental updates, channel rank tracking, etc. We consider three different types of channels: IID random, slow fading and measured channels. The entire work is simulated in the MATLAB environment. The main contribution of this work includes: a comparative study and a head to head comparison of the VBLAST and SVD-based MIMO systems. The application of adaptive modulation in the SVD-based system and the introduction of a new effcient decoding method for the VBLAST system are also included. Simulation results are reported with comments and conclusions.