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Large scale quantum computers will break classical public-key cryptography protocols by quantum algorithms such as Shor’s algorithm. Hence, designing quantum-safe cryptosystems to replace current classical algorithms is crucial. Luckily there are some post-quantum candidates that are assumed to be resistant against future attacks from quantum computers, and NIST is considering standardizing them. Among these candidates, lattice-based cryptography sounds more interesting than others due to the performance results as well as confidence in the security. There are few works in the literature evaluating the performance of lattice-based cryptography in hardware. In this paper, we focus on Cryptographic Suite for Algebraic Lattices (CRYSTALS) key exchange mechanisms known as Kyber and provide an instruction-set hardware architecture and implement on Xilinx Artix-7 FPGA for performance evaluation and testing. Our proposed architecture provides an efficient and high-performance set of components to perform polynomial sampling, number-theoretic transform (NTT), and point-wise multiplication to speed up lattice-based post-quantum cryptography (PQC). This architecture implemented on ASIC outperforms state-of-the-art implementations. [ABSTRACT FROM AUTHOR]

This paper presents a full hardware implementation of the eXtended Merkle Signature Scheme (XMSS), a NIST approved and IETF RFC specified post-quantum cryptography (PQC) algorithm. An optimized node traversal is proposed to enable efficient memory utilization without compromising the computational latency of the L-tree and Merkle tree construction, which are two key components used for the compression of the Winternitz One-Time Signature (WOTS) public key in XMSS. The computation of the authentication path during signature generation has also been significantly sped up by our proposed hardware implementation of the Buchmann, Dahmen, and Schneider (BDS) algorithm. Our implementation has completely avoided the use of block random-access memory, which is known to be vulnerable to side-channel attacks. The memory requirement has been highly optimized for implementation with small flip-flop chains and register counters as pointers for fast data access. To the best of our knowledge, this is the first full hardware implementation of all three key generation, signing and verification operations of XMSS. The design has been prototyped and evaluated on a 28 nm FPGA platform to demonstrate its performance improvements over the most efficient software and hardware/software co-design methods reported to date. Specifically, it increases the computational efficiency of the best reported XMSS implementation for key generation and signature generation by about 20% and 50%, respectively. It can also run at 10% higher clock speed than the fastest hardware implementation of signature verification in FPGA with 8% lower hardware resource utilization. [ABSTRACT FROM AUTHOR]

Deep learning is now being used to translate between languages, predict how proteins fold, analyze medical scans, and play games as complex as Go, to name just a few applications of a technique that is now becoming pervasive. Success in those and other realms has brought this machine-learning technique from obscurity in the early 2000s to dominance today. • Although deep learning's rise to fame is relatively recent, its origins are not. In 1958, back when mainframe computers filled rooms and ran on vacuum tubes, knowledge of the interconnections between neurons in the brain inspired Frank Rosenblatt at Cornell to design the first artificial neural network, which he presciently described as a “pattern-recognizing device.” But Rosenblatt's ambitions outpaced the capabilities of his era—and he knew it. Even his inaugural paper was forced to acknowledge the voracious appetite of neural networks for computational power, bemoaning that “as the number of connections in the network increases…the burden on a conventional digital computer soon becomes excessive.” • Fortunately for such artificial neural networks—later rechristened “deep learning” when they included extra layers of neurons—decades of Moore's Law and other improvements in computer hardware yielded a roughly 10-million-fold increase in the number of computations that a computer could do in a second. So when researchers returned to deep learning in the late 2000s, they wielded tools equal to the challenge. [ABSTRACT FROM AUTHOR]

There is a growing interest in quantum computers and quantum algorithm development. It has been proved that ideal quantum computers, with zero error rates and large decoherence times, can solve problems that are intractable for today’s classical computers. Quantum computers use two resources, superposition and entanglement, that have no classical analog. Since quantum computer platforms that are currently available comprise only a few dozen of qubits, the use of quantum simulators is essential in developing and testing new quantum algorithms. We present a novel quantum simulator based on memristor crossbar circuits and use them to simulate well-known quantum algorithms, namely the Deutsch and Grover quantum algorithms. In quantum computing the dominant algebraic operations are matrix-vector multiplications. The execution time grows exponentially with the simulated number of qubits, causing an exponential slowdown in quantum algorithm execution using classical computers. In this work, we show that the inherent characteristics of memristor arrays can be used to overcome this problem and that memristor arrays can be used not only as independent quantum simulators but also as a part of a quantum computer stack where classical computers accelerators are connected. Our memristive crossbar circuits are re-configurable and can be programmed to simulate any quantum algorithm. [ABSTRACT FROM AUTHOR]

Consumer technology is often a story of revolutionary leaps followed by a descent into familiarity. The first computers advanced so quickly that new models went obsolete while they were still on store shelves. Today, any US $500 laptop will be relevant for a decade. A similar story can be told of smartphones, TVs, even cars. [ABSTRACT FROM AUTHOR]

Differentiable neural computers (DNCs) extend artificial neural networks with an explicit memory without interference, thus enabling the model to perform classic computation tasks, such as graph traversal. However, such models are difficult to train, requiring long training times and large datasets. In this work, we achieve some of the computational capabilities of DNCs with a model that can be trained very efficiently, namely, an echo state network with an explicit memory without interference. This extension enables echo state networks to recognize all regular languages, including those that contractive echo state networks provably cannot recognize. Furthermore, we demonstrate experimentally that our model performs comparably to its fully trained deep version on several typical benchmark tasks for DNCs. [ABSTRACT FROM AUTHOR]

The Supersingular Isogeny Key Encapsulation mechanism (SIKE) is the only post-quantum key encapsulation protocol based on elliptic curves and isogeny maps between them. Despite the quantum security of the protocol, SIKE requires a greater number of clock cycles and hence does not provide competitive timing and energy consumption results. However, it is more attractive offering the smallest public key as well as ciphertext sizes, which considering the impact of the communication costs and storage of the keys could become a good fit for resource-constrained devices. In this work, we present the fastest practical implementation of SIKE, targeting the platform Cortex-M4 based on the ARMv7-M architecture. We performed our measurements on the STM32F407VG microcontroller for benchmarking the clock cycles and on Nucleo-F411RE attached to X-NUCLEO-LPM01A (Power Shield) for measuring the energy consumption of the protocol. The low-level finite field arithmetic operations play main role in determining the efficiency of SIKE. Therefore, we mainly focus on their optimization and apply them to all NIST-required security levels. Our SIKEp434 implementation for NIST security level 1 is about 22.97% faster than the counterparts appeared in Seo et al. (2020), where for the SIKEp503, SIKEp610 and SIKEp751 the speedup reaches 21.10%, 19.21% and 19.08%. Finally, we benchmark energy consumption and report optimization of up to 11.9% depending on the NIST security level implementation. [ABSTRACT FROM AUTHOR]

Think of the many tasks to which computers are being applied that in the not-so-distant past required human intuition. Computers routinely identify objects in images, transcribe speech, translate between languages, diagnose medical conditions, play complex games, and drive cars. [ABSTRACT FROM AUTHOR]

For Yung-Hsiang Lu, improving the energy efficiency of computer technology to provide real-world benefits has been a lifelong focus. [ABSTRACT FROM AUTHOR]

On 12 August 1981, at the Waldorf Astoria Hotel in midtown Manhattan, IBM unveiled its entrant into the nascent personal computer market: the IBM PC. With that, the preeminent U.S. computer maker launched another revolution in computing. Soon the world began embracing little computers by the millions, with IBM dominating those sales. Other companies, including Apple and Tandy Corp., were already making personal computers, but no other machine carried the revered IBM name. IBM's essential contributions were to position the technology as suitable for wide use and to set a technical standard. Rivals were compelled to meet a demand that they had all grossly underestimated. As such, IBM had a greater impact on the personal computer's acceptance than did Apple, Compaq, Dell, and even Microsoft. And yet IBM's lead in this new market would last only a few years, and the eclipse of the IBM PC came to mirror the decline of Big Blue. [ABSTRACT FROM AUTHOR]