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This paper proposes a power-up calibration scheme to mitigate the offset of a capacitive-gain chopper instrumentation amplifier (CCIA), thus suppressing the offset-induced output ripple. In this design, the first stage of the error amplifier is formed by multiple identical slices. Before normal operation, the offset polarity of each slice is determined by reusing the second stage of the amplifier as a comparator. With such polarity information, slices of the first stage are regrouped to achieve a statistical offset reduction. The proposed amplifier has been fabricated in a standard $0.18~\mu \text{m}$ CMOS process with an area of 0.57 mm2, achieving an average peak-to-peak output ripple of 58 mV. The amplifier consumes $1.53~\mu \text{W}$ with a 1.2 V supply. Compared to the state-of-the-art, the calibration time of the proposed scheme is much shorter (14 clock cycles) and the overhead logic consumes no static power after calibration. In addition, the slicing technique provides an extra degree of freedom to the amplifier for bandwidth and noise scaling. [ABSTRACT FROM AUTHOR]

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, −3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with V DD of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area. [ABSTRACT FROM AUTHOR]

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/ƒ noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency (ƒch) same as the sampling frequency (ƒs). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/√Hz input-referred noise density, 1.9 μ V offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mVpp. With −110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique. [ABSTRACT FROM AUTHOR]

A wideband CMOS low-noise amplifier (LNA) with multiple resonant frequencies is demonstrated in this article. A common source (CS) with inductive degeneration topology is widely employed in LNA circuit design to decouple the input impedance from the noise figure (NF). Since CS with inductive degeneration topology only achieves a single resonant frequency, it generally has narrow bandwidth performance. Through impedance transformation analysis of the matching circuit, a shunt resonator combined with inductive degeneration topology employed for input impedance transformation is carefully constructed to form multiple resonant frequencies. By placing resonant frequencies further apart from each other, impedance fluctuations within a wideband frequency range can be alleviated. In addition, the noise performance of this topology is the same as that of a conventional CS source-degenerated structure. The proposed LNA for the whole K/Ka Band is implemented in a commercial 65-nm CMOS process. It occupies 0.28 mm2. Under a 1.0 V voltage supply, the LNA achieves 3-dB gain bandwidth of 28 GHz from 16.5 GHz to 44.5 GHz. Within the whole 3-dB bandwidth, the gain is larger than 15.5 dB, the NF is less than 4.8 dB with a minimal value of 2.72 dB, and the input 1-dB gain compression point (IP1dB) varies from −24 dBm to −12 dBm. [ABSTRACT FROM AUTHOR]

The continuous-time pipeline (CTP) analog-to-digital converter is an emerging technique that combines the benefits of pipelining with continuous-time operation. Prior-art multistage CTP ADCs have employed stages with identical transfer functions. This work proposes the use of non-identical (and appropriately chosen) transfer functions for different stages of the pipeline. We investigate the benefits of this approach when compared with conventional techniques. We also demonstrate that the sharp filtering offered by a multi-stage CTP can be exploited to implicitly decimate the output sequence of the converter. This is accomplished by clocking the back-end ADC at a lower rate, and by appropriately modifying the digital reconstruction filters. The implicit-decimation theory is supported with measurement results from a three-stage CTP designed in a 65nm CMOS process. The converter achieves 70.4dB SNDR in a 100MHz bandwidth with its front-end operating at $f_{s}\,{=}\,800$ MHz, while the back-end samples at $f_{s}/2$. [ABSTRACT FROM AUTHOR]

The influence of coupling of oscillators in phase-locked loops (PLLs) was studied here. Particularly, numerical analyses based on nonlinear differential equations of the self- and mutual coupling systems were performed and compared with the results of the linear approximation model under synchronous conditions. The analysis revealed that coupling using the reference clock caused greater PLL instability than that caused by self-coupling for a given coupling strength. This shows that the phase error of mutual coupling exhibits the same behavior as that of reference-clock coupling in the single PLL under synchronous conditions, and the noise sensitivity of mutual coupling is twice that of the reference-clock coupling. In addition, the phase error of mutual coupling in the quasi-synchronous condition strongly depends on the relationship between the frequency difference of the two PLLs and the PLL bandwidth. We designed and fabricated the test circuits for theoretical verification using the 0.18- $\mu \text{m}$ standard CMOS process. From the measurements, adjustment of the timing difference between the two PLLs is effective in mitigating mutual coupling under synchronous conditions. Moreover, we implemented mutual injections between two oscillators in the test circuit and confirmed their effectiveness. The proposed methods will be useful for achieving the compact and effective cancellation of the mutual coupling between PLLs. [ABSTRACT FROM AUTHOR]