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Primary-side regulation (PSR) flyback topology with discontinuous conduction modulation (DCM) mode has been widely used in low-power application due to its high stability, wide input voltage range, low cost, and low standby power. To improve the output power, continuous conduction modulation (CCM) mode is always introduced. However, in CCM mode, conventional PSR voltage-sampling method cannot realize high precision of output voltage or the voltage sampling method requires complex control of high cost. In this paper, a simple digital voltage sampling scheme with two reference voltages outputted from a digital-to-analog converter (DAC) is put forward to trace the “accurate-point” voltage for DCM and CCM modes. In CCM mode, the sampling voltage error of the “knee-point” voltage can be compensated just by inserting DCM switching cycle to obtain the “accurate-point” voltage. Voltage difference between DCM mode and CCM mode will be eliminated, and high precision is easily realized. The proposed method is verified in a 20V, 65W PSR flyback converter. The sampling method only requires a low speed DAC, three comparators and a digital controller. The output voltage precision is within 0.6% with universal input voltage. [ABSTRACT FROM AUTHOR]

In-memory computing (IMC) is an effective solution for energy-efficient artificial intelligence applications. Analog IMC amortizes the power consumption of multiple sensing amplifiers with an analog-to-digital converter (ADC) and simultaneously completes the calculation of multi-line data with a high parallelism degree. Based on a universal one-transistor one-magnetic tunnel junction (MTJ) spin transfer torque magnetic RAM (STT-MRAM) cell, this paper demonstrates a novel tunneling magnetoresistance (TMR) ratio magnifying method to realize analog IMC. Previous concerns including low TMR ratio and analog calculation nonlinearity are addressed using device-circuit interaction. The TMR is magnified $7500\times $ using a latch structure in combination with the device. Peripheral circuits are minimally modified to enable in-memory matrix-vector multiplication. A current mirror with a feedback structure is implemented to enhance analog computing linearity and calculation accuracy. The proposed design maximumly supports 1024 2-bit input and 1-bit weight multiply-and-accumulate (MAC) computations simultaneously. The proposal is simulated using the 28-nm CMOS process and MTJ compact model. The integral nonlinearity is reduced by 57.6% compared with the conventional structure. 9.47-25.4 TOPS/W is realized with 2-bit input, 1-bit weight, and 4-bit output convolution neural network (CNN). [ABSTRACT FROM AUTHOR]

In recent decades, the performance of binary computers has escalated through transistor scaling. However, due to the impotent forecasts of transistor scaling, ternary systems are regaining attention. Among many ternary device candidates, a passive device called memristor that is based on resistance switching is considered a good candidate when integrated with MOSFETs. Therefore, in this paper, we design various terna-ry logic based on memristors and MOSFETs from primitive logic to sequential logic and perform a thorough diagnosis for circuit design. We highlight design issues that should be resolved (e.g., signal distortion and high static current) and present practical solutions such as “Strength Design.” Then, we report a proper design methodology of sequential circuits considering the spike phenomena of memristor-based gates. We present 16 novel ternary logic cells and circuitry, including the design of the first balanced ternary full-adder (TFA) and memristor-based ternary pulsed-latch (MTPL). By our TFA, we emphasize that it is possible to design the most practical ternary circuits using memristors and MOSFETs. Our TFA uses 97 transistors and 87 memristors, which is the most reasonable TFA design that has the highest potential to be implemented in the near future. Besides, the proposed MTPL uses 16 transistors and 10 memristors, and it occupies only 72.7% of the silicon area, compared to the master-slave ternary flip-flop. [ABSTRACT FROM AUTHOR]

This paper presents the design of tunable CMOS pseudo-resistors aimed at achieving large and predictable resistance values. Instrumental to the proposed pseudo-resistor is the design of current sources of extremely low currents and transistors operating in subthreshold. The effects of the leakage currents of reverse-biased pn-junctions on the pseudo-resistor resistance are also evaluated. The proposed pseudo-resistor circuit was validated while in use as part of a filter integrated in a 180 nm CMOS process. Pseudo-resistors with resistances between 180 $\text{G}\Omega $ and 700 $\text{G}\Omega $ were employed to obtain low-frequency poles of a band-pass filter adjustable from 0.6 Hz to 2 Hz. [ABSTRACT FROM AUTHOR]

The reduction of the nominal supply voltage of CMOS technologies with scaling comes with the decrease of the maximum tolerable voltage of the devices. This poses challenges in implementing circuit blocks that are compliant with standardized communication protocols or deal with off-chip signals in voltage domains larger than the nominal supply (e.g., 1.8 V, 3.3 V, 5 V). Design techniques such as cascoding, voltage shifting and adaptive biasing are effective at removing the need for customized voltage resistant input/output (I/O) devices since they prevent intolerable voltage drops. However, at the input of multiple-channel blocks, the design of switches of multiplexers results critical as the input and the output nodes can assume values beyond the signal range, causing harmful biasing configurations. This paper presents the architecture of a switch for input channel multiplexers able to handle signals up to twice the nominal supply voltage of the employed devices. Its effectiveness has been proved by implementing a 1.6V switch with the core MOS transistors of the 28nm CMOS technology with 0.96V nominal supply voltage. The comparison with a benchmark switch based on 1.8V I/O devices showed that both a larger area (slightly more than twice) and static current consumption ($40\mu \text{A}$) are required. [ABSTRACT FROM AUTHOR]

Non-volatile memory (NVM) such as RRAM and PCM has become the key component in high energy efficiency computing-in-memory (CIM) architectures. However, the computing accuracy and energy efficiency improvement of conventional 1T1R RRAM array based current sensing CIM scheme is hindered by device variation and large output current. In this work, we propose a voltage sensing differential column architecture (VSDCA) based on 1T2R RRAM array for binary memory and CIM applications. The memory mode of VSDCA macro can improve $1.12\times $ to $5.29\times $ relative read margin compared to conventional 1T1R current sensing memory. The computing mode supports 8-bit input, 9-bit weight and 18-bit output high precision and rows fully parallel computing. The VSDCA macro design is evaluated under SMIC 40 nm technology node, the energy efficiency for the high precision CIM reaches 39.52 TOPS/W. The CIFAR10 inference accuracy of the simulated VGG16 and ResNet18 model is 85.91% and 89.32% respectively. [ABSTRACT FROM AUTHOR]

A novel Resistive random access memory (ReRAM)-based Compute-in-memory (CIM) macro is proposed to overcome the limited accuracy and throughput of a conventional ReRAM-based CIM macro that results from to the low R-Ratio and large variation of ReRAM. The proposed structure consists of 1T2R1C bit-cells and 4-kb ReRAM-based nvCIM architecture with ternary weight and ternary input. Ternary multiplication is implemented with voltage division between paired ReRAM devices within a bit-cell to make the output voltage variation tolerant and less sensitive to low R-ratios. An accumulation operation is realized with capacitive coupling so that linearity can be guaranteed for a large number of operands, allowing accurate and fast multiply-and-accumulate (MAC) operations. For comprehensive validation of the proposed CIM macro, the Verilog-A models for ReRAM devices with an adjustable R-ratio and adjustable variations are adopted to perform simulation on various R-ratio and variation conditions. With the peripheral circuits designed in 180-nm CMOS technology, the proposed CIM macro is confirmed to have high variation tolerance, high throughput, and less sensitivity to a low R-ratio, resulting in a high ternary DNN accuracy of 99.07% (0.01% drop) for the MNIST and 83.79% (0.38% drop) for the CIFAR-10 data sets with an R-ratio as low as 38 and 20%/40% low/high resistance variation. [ABSTRACT FROM AUTHOR]

A sneak current compensation scheme with offset cancellation sensing circuit (SCC-OCSC) adopting dummy bitline and wordline is proposed to resolve sneak current problem in the cross-point memory array. The sneak current degrades sensing yield because it disturbs read operation for high resistance cell, especially, by contaminating read current. Since the sneak current increases proportionally to the array size, the array size is limited to achieve the target sensing yield, which makes it hard to implement high density memory. The proposed SCC-OCSC cancels-out the sneak current through two phases. In first phase, the sneak current is sampled by connecting dummy BL or WL to the sensing circuit. In the second phase, the sneak current is compensated by subtracting the current sampled in the first phase. Furthermore, sensing yield is enhanced by applying the offset cancellation technique, sharing the same sensing circuit in the two phases. The proposed SCC-OCSCs with dummy BL and WL effectively improve read margin with generally used biasing schemes, floating and half-VDD schemes, respectively. In Monte-carlo simulation including post-layout sensing circuit with 65nm CMOS technology, it is verified that sensing yield is significantly improved. Thus, the array size assigned to single sensing circuit is extended up to 8-times with SCC-OCSC, leading 88% area reduction with reduced number of required sensing circuit. Performance is improved as 66% and 25% while power consumption is improved as 47% and 37%, by SCC-OCSC with dummy BL in floating scheme and SCC-OCSC with dummy WL in half-VDD scheme, respectively. [ABSTRACT FROM AUTHOR]

Locally-active memristor (LAM) is one of the promising candidates of artificial neurons, indicating it has potential applications in neuromorphic computing. Quantitative theoretical analysis on LAMs can provide benefits for designing related oscillator circuits and systems. This study begins with the aim of assessing the importance of DC V-I characteristic in the performance of LAMs by using small-signal analysis method. The DC V-I curve of the LAM is specified by two parameters involving resistance (conductance) and differential resistance (differential conductance). In addition to these two static parameters, we extract a crucial dynamic parameter to describe the behavior of the LAM. Theoretical analysis demonstrates that the performance of generic current-controlled and voltage-controlled LAMs is closely associated with three crucial parameters, i.e., the above two static and one dynamic parameters. Hence, only based on these three parameters, can one derive the small-signal equivalent circuit of LAMs and determine the oscillation frequency range and condition for simple LAM-based oscillators. By applying the presented universal dynamics analysis results, we further propose a modified mathematical model with higher accuracy to mimic the quasi-static and oscillating behaviors of a real Nb2O5 device, and provide some fundamental guidance for the design of LAM-based high-frequency oscillators. [ABSTRACT FROM AUTHOR]