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This paper presents fully integrated switched-capacitor boost-buck power converters with conversion ratios 5, 7, and 1/5. Such converters operate over a voltage range extended beyond the device ratings due to a low-voltage-stress configuration, accumulation-mode NMOS capacitors, and a circuit technique for switch bootstrapping. After modeling the simple and the symmetrical ladder converters, we determined methods for assessing the device working voltages and for optimizing the sizes of capacitors and switches. The key performance parameters were compared and the losses due to non-linear parasitic capacitances were calculated. The characterization of the prototypes in a 1.8–3.3-V, 0.18- $\mu \text{m}$ CMOS process demonstrated a 15 V range, a 5.4 mW/mm2 output power density, and good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]

This paper proposes a low power area-efficient multi-mode voltage clamper circuit called pseudo differential pair and applies it into an error amplifier (EA) which can be used in DC-DC converters as a practical design example. In addition to a normal amplifying mode, the error amplifier has two extra operation modes with the help of the voltage clamper, which can limit the maximum output voltage and the maximum sink current, respectively. By inserting this pseudo differential pair of only three transistors in the intermediate stage of the amplifier, a voltage-current feedback is introduced to achieve the voltage limiting function without bringing resistive load to the output stage or unwanted effects to the input stage. The frequency compensation of the EA is also reused in the voltage limiting loop to make the whole block more compact. The circuit is implemented in a $0.35~\mu \text{m}$ BCD process. The verification results match the theoretical analysis very well, which proves that the proposed voltage clamper can effectively enhance transient response of the converter control loop and improve system reliability. Only additional 0.001689 mm2 active area is occupied for about 2X transient speed improvement with fair open loop amplifying performance. [ABSTRACT FROM AUTHOR]

This paper describes the design of an integrated sensor interface for dopamine detection. The sensor interface circuit fabricated in 65 nm CMOS technology utilizes a time-based analog-to-digital conversion circuit built around a ring oscillator. The circuit supports a wide input current range of ± 1.2 μA and sampling rate of 1 - 20 kHz, enabling sub-second detection of neurochemicals within the supported current range. Measured results with physiologically relevant dopamine concentration of 500 nM demonstrate the ability of the sensor interface circuit to detect oxidation and reduction current peaks, which provides information about the release times and redox potentials of the neurochemical. This chemical information is essential in neurostimulation treatment of neurological and neurodegenerative diseases. [ABSTRACT FROM AUTHOR]

This paper presents a process, voltage, and temperature (PVT)-insensitive dynamic amplifier (DA) with gain enhancement for a pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The gain shift due to temperature and process variation is attenuated through the counteraction of input transconductance and delay-based integration time. Furthermore, based on charge conservation, a gain-folding technique is proposed to improve the gain limit of conventional DA, tripling the gain amplitude. The proposed DA is incorporated in a design of a 12-bit 100 MS/s SAR ADC. In 65 nm CMOS process, at 100 MS/s, the prototype ADC achieves an SNDR (signal-to-noise plus distortion ratio) of 65.7 dB and a Walden FoM of 12.06 fJ/conversion-step for a near-Nyquist input. The power dissipation is less than 1.9 mW. No more than 1.65 dB SNDR variations are obtained for supply voltage varying from 1.15 to 1.25 V and temperature varying from −20 °C to 125 °C with various process corners, respectively. [ABSTRACT FROM AUTHOR]

This paper presents an IC that extends the voltage capability of a low voltage battery charger to 100V for accurately and reliably charging lithium ion (Li-Ion) battery stacks of up to 18 cells. The IC interfaces with a buck converter battery charger that utilizes external nFET control and an external inductor current sensing resistor. The voltage extender IC provides voltage level translation for the nFET control signals and the current sensing function while supporting an input power supply voltage of up to 100V and output battery voltage of up to 80V. The inductor current sense voltage is translated with a ping-pong amplifier capable of driving a bi-directional input voltage to a fully differential output with a maximum load current of 10 mA at 20 MHz bandwidth and less than $500~\mu \text{V}$ offset. The combined system of the voltage extender IC and battery charger achieved 97% efficiency at a 4-A charging current. The battery charging voltage accuracy was better than ± 0.5% at 80V. [ABSTRACT FROM AUTHOR]

This paper presents experimental results from a system that comprises a fully autonomous energy harvester with a solar cell of 1 mm2 as energy transducer and a Power Management Unit (PMU) on the same silicon substrate, and an output voltage regulator. Both chips are implemented in standard $0.18~\mu \text{m}$ CMOS technology with total layout areas of 1.575 mm2 and 0.0126 mm2, respectively. The system also contains an off-the-shelf 3.2 mm $\times2.5$ mm $\times0.9$ mm supercapacitor working as an off-chip battery or energy reservoir between the PMU and the voltage regulator. Experimental results show that the fast energy recovery of the on-chip solar cell and PMU permits the system to replenish the supercapacitor with enough charge as to sustain Bluetooth Low Energy (BLE) communications even with input light powers of 510 nW. The whole system is able to self-start-up without external mechanisms at 340 nW. This work is the first step towards a self-supplied sensor node with processing and communication capabilities. The small form factor and ultra-low power consumption of the system components is in compliance with biomedical applications requirements. [ABSTRACT FROM AUTHOR]

This paper presents a self-biased subthreshold CMOS voltage reference for low-power and low-voltage applications. To achieve near-zero line sensitivity and high PSRR, a compensation structure utilizing the drain-induced-barrier-lowering (DIBL) effect is proposed to sink a supply dependent current from the output branch of a self-biased CMOS reference, which cancels the bias current’s dependence on the supply voltage due to the DIBL effect. Fabricated in a 0.18- $\mu \text{m}$ CMOS technology, the measurement results demonstrate that the proposed circuit could operate under a minimum supply voltage of 0.34 V and generate a reference voltage of 147 mV, while consuming only 48 pW power. The PSRRs measured at 1 Hz and 10 kHz are −70.6 dB and −50.2 dB, respectively. For 39 measured samples, the mean line sensitivity is 0.019%/V in a supply voltage range from 0.34 to 1.8 V, and the average temperature coefficients before and after trimming are 64.81 and 10.06 ppm/°C in 0 ~ 100 °C temperature range, respectively. The total area of the voltage reference circuit is 0.0332mm2. [ABSTRACT FROM AUTHOR]

Energy harvesting is the process of capturing the local ambient energy and converting it into useful energy. Piezoelectric energy harvesters (PEHs) are one of the solutions to convert vibration energy to electrical energy. An electrical interface is needed to bridge between the piezoelectric energy harvester and the energy storage element. A high-efficient AC/DC converter is designed for a low vibration power harvester with the milli- or micro-watt range power. This paper reports a novel self-powered high-efficiency interface to rectify the AC voltage generated by a vibration energy harvester to DC voltage. The reported interface consists of a triggering circuit and a Negative Voltage Converter (NVC) combined with a Parallel Synchronized Switch Harvesting on Inductor (PSSHI) forming the NVC-PSSHI. The analytical model and simulation of the designed NVC-PSSHI interface were derived and performed, respectively. The targeted input voltage, frequency and DC loading conditions were 3 Vpp to 7 Vpp, 100 Hz to 500 Hz and 5 $\text{k}\Omega $ to 30 $\text{k}\Omega $ , respectively. Experiments with a PEH were also performed to validate the analytical and simulation results. The maximum efficiency of the designed NVC-PSSHI interface reached 82.1% from the PEH experiment. The NVC-PSSHI interface efficiency was higher than the traditional PSSHI interface by up to 23.4%. [ABSTRACT FROM AUTHOR]

A single-inductor dual-supply dc–dc converter with bidirectional energy flow is proposed for the Internet-of-Things applications. This paper combines two dc–dc converters into one by sharing a single inductor, and it is capable of storing energy and powering output load by using the bidirectional inductor current. Besides, the voltage of the energy storage element is continuously monitored in the proposed converter, which eliminates the possibility of overcharging. Furthermore, the variations on the output voltage are typically negligible when the input voltage changes. In addition, a novel two-step startup procedure that does not require any on-chip/off-chip startup auxiliary circuit is proposed, which can significantly reduce the chip area. The proposed converter is fabricated by a 0.18- $\mu \text{m}$ CMOS mixed-signal process. The voltage range of the storing element is 1.2–1.4 V, and the maximal output power of the proposed converter is 18 mW with its output voltage setting at 1.8 V. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and high-precision voltage and current reference (VCR) in one simple circuit. The voltage reference is derived from the threshold voltage difference between an I/O (i.e., 3.3-V NMOS) and standard (i.e., 1.8-V NMOS) transistors with temperature-independent bias current, and the current reference is the voltage reference divided by a temperature-insensitive resistor. The resistor is made up by series connection of a proportional-to-absolute-temperature (PTAT) NWELL resistor and a complementary-to-absolute-temperature (CTAT) high-resistance poly resistor in series. Implemented in a standard 0.18- $\mu \text{m}$ CMOS process, the proposed VCR circuit takes an active area of only 0.055 mm2. The measured voltage and current references ($\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$) at room temperature are 368 mV and 9.77 nA, respectively. The measured average temperature coefficient (TC) of $\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$ are 43.1 ppm/°C and 149.8 ppm/°C over a temperature range of −40~125°C with one-time trimming and the variation coefficients are 0.35% and 1.6%, respectively. The measured voltage and current line sensitivities are 0.027%/V and 0.6%/V, respectively. The minimum supply voltage is 0.7 V with a total power consumption of 28 nW. The measured power supply ripple rejection (PSRR) of $\text{V}_{\mathrm {ref}}$ is −65 dB @DC and −39.4 dB at frequencies higher than 1 Hz. [ABSTRACT FROM AUTHOR]

In this paper, a generic, low-noise, negative-voltage generator with wide tuning range and moderate driving capacity is presented. The highly integrated solution, incorporating a fully-integrated charge-pump and a regulator block, requires only one off-chip capacitor that can be shared with the supply decoupling capacitors. The fully integrated charge-pump operation is analyzed quantitatively, and a closed-form expression of its output impedance is derived. Powered from a single 3.3-V dc input, the output has a tuning range from −4.4 to +2.1 V for biasing applications, while the design supports a maximum load current of 250, 550, and $800~\mu \text{A}$ for the regulated output voltage at −3.0, −1.5, and 1.5 V, respectively. The measured steady-state ripple is under 3 mVPP, while the noise voltage at the charge-pump operating frequency harmonics is below 130 $\mu \text {V}_{\mathrm{ rms}}$ and the noise floor is under $5~\mu \text {V}_{\mathrm{ rms}}$. The design is also the application verified with a gallium nitride power amplifier, thus further confirming its low-noise performance. Implemented in CMOS 180-nm process, the prototype chip occupies an area of 0.55 mm2. [ABSTRACT FROM AUTHOR]

For ultra-low-power Internet of Things (IoT) devices powered by batteries or energy harvesting, a nonvolatile flip-flop (NV-FF) operating in the near-threshold voltage (NTV) region has been widely studied to save both standby and active power. However, in the NTV region, the NV-FF suffers from restore yield and performance degradation due to the increase in process variation combined with the decrease in supply voltage. This paper presents a comparative analysis of the previous NV-FFs according to supply voltage scaling and suggests the design directions for implementing the NV-FF that can operate with compact area and high performance even in the NTV region. Through the comparative analysis, a novel offset-cancellation sensing-circuit (OCSC)-based NV-FF, which adopts a separate latch and sensing circuit structure and an offset-cancellation technique, is proposed. The Monte Carlo HSPICE simulation results using industry-compatible 65-nm model parameters show that the proposed NV-FF satisfies a target restore yield with 32% area, 88% speed, and 82% energy savings in comparison with a representative NV-FF of the merged latch and sensing circuit structure. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of eight MOS transistors to control one unit capacitor, the 3-bit LSB MDAC is realized by a MOS string with four native MOS transistors to control two unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared to a Vcm-based 10-bit pure CDAC with the same unit capacitance. Under the sampling rate of 200 kS/s, the prototype 10-bit SAR ADC implemented in a 0.18- ${\mu }\text{m}$ CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes $1.76~{\mu }\text{W}$ at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/−0.21 LSB and +0.43/−0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm2. [ABSTRACT FROM AUTHOR]

This paper presents two new line-coding schemes, integrated pulse width modulation (iPWM) and consecutive digit chopping (CDC) for equalizing lossy wireline channels with the aim of achieving energy efficient wireline communication. The proposed technology friendly encoding schemes are able to overcome the fundamental limitations imposed by Manchester or pulse-width modulation encoding on high-speed wireline transceivers. A highly digital encoder architecture is leveraged to implement the proposed iPWM and CDC encoding. Energy-efficient operation of the proposed encoding is demonstrated on a high-speed wireline transceiver that can operate from 10 to 18 Gb/s. Fabricated in a 65-nm CMOS process, the transceiver operates with supply voltages of 0.9 V, 1 V, and 1.1 V. With the help of the proposed iPWM encoding, the transceiver can equalize over 27-dB of channel loss while operating at 16 Gb/s with an efficiency of 4.37 pJ/bit. The design occupies an active die area of 0.21 mm2. [ABSTRACT FROM AUTHOR]

The performance of resonant piezoelectric vibration energy harvesters (RPVEHs) is strongly affected by the characteristics (shape, amplitude, spectrum, and so on) of the vibrations from which energy is harvested. In particular, the estimation of the power that can be harvested by a given RPVEH fed by a specific vibration source is of great importance for design purposes. A fast estimation of the extractable power allows an effective and proper sizing of the harvesting devices. This paper addresses this issue for non-sinusoidal vibration sources, filling the gap in the existing literature. To this end, an accurate and efficient analysis tool for RPVEH systems loaded by bridge rectifiers is provided. The estimation of the average extracted power as a function of the bridge rectifier dc output voltage is carried out for both weakly and non-weakly electromechanically coupled RPVEHs. A closed-form expression is provided for the case of amplitude-modulated vibrations, whereas an analytical-numerical expression is given in case of vibrations with a non-sinusoidal slowly varying envelope. Experimental tests, obtained by using a commercial RPVEH, validate the theoretical results. [ABSTRACT FROM AUTHOR]

The conventional MOS current mode logic (MCML)-based multiplexer needed for serializer application has various limitations, such as low voltage-swing, substantial power consumption, and large area overhead. In the circuit arrangement of a serializer using the MCML-based mux-tree concept, the output of one mux at any stage is used to feed another mux at the next stage through some latch circuits, which are basically used for timing synchronization giving away penalty in terms of delay and area. The increase in number of stages of the Serializer may lead to further reduction in output swing (if common mode is not properly set), thereby causing signal integrity issues and finally loss of data. To address the same, a latency combined current mode multiplexer incorporating pMOS-based dual cross-coupled latch circuit is unearthed in this paper to further outline an area and energy efficient high-speed serializer capable of maintaining uniform peak-to-peak swing and signal quality at differential outputs. The simulations of new serializer are performed for 90-nm CMOS in the Cadence Virtuoso platform, where the average power and delay are found to be $471.6~\mu \text{W}$ and 93.9 ps, respectively, to provide a power delay product of 43.8 fJ only at a power supply of 1 V. An improved output swing of 904 mV is also noticed along with a data rate of 50 Gb/s and a BER of <10−12. The entire design is proved to be a robust one after simulating it through Monte Carlo at five different process corners and also validated at lower process nodes such as 28-nm UMC. [ABSTRACT FROM AUTHOR]

This paper presents a 60 mV input voltage start-up system for thermoelectric energy harvesting. A new process tolerant inverter cell is proposed, which is functional at supply voltages as low as 60 mV. Using the proposed unit cell, a ring oscillator has been implemented. The ring oscillator is followed by 40 charge-pump stages, an ultra-low-power level detector, and a boost converter. The energy harvesting system can generate an output voltage of 1 V and delivers a maximum power of $4.5~\mu \text{W}$ from a 60 mV supply. This system has been implemented in a standard $0.18~\mu \text{m}$ CMOS technology, uses neither zero-threshold voltage (normally-on) negative-channel metal-oxide semiconductor nor microelectromechanical systems switches and occupies 3.3 mm2. [ABSTRACT FROM AUTHOR]

Radix- $2^{k}$ delay feed-back and radix-K delay commutator are the most well-known pipeline architecture for FFT design. This paper proposes a novel radix-22 multiple delay commutator architecture utilizing the advantages of the radix-22 algorithm, such as simple butterflies and less memory requirement. Therefore, it is more hardware efficient when implementing parallelism for higher throughput using multiple delay commutators or feed-forward data paths. Here, we propose an improved input scheduling algorithm based upon memory to eliminate energy required to shift data along the delay lines. A 1024-point FFT processor with two parallel data paths is implemented in 65-nm CMOS process technology. The FFT processor occupies an area of 3.6 mm2, successfully operates in the supply voltage range from 0.4–1 V and the maximum clock frequency of 600 MHz. For low voltage, high performance applications, the processor is able to operate at 400 MHz and consumes 60.3 mW or 77.2 nJ/FFT generating 800 Msamples/s at 0.6 V supply. [ABSTRACT FROM AUTHOR]

Computationally-secure cryptographic algorithms implemented on a physical platform leak significant “side-channel” information through their power supplies. Correlational power attack is an efficient power side-channel attack (SCA) technique, which analyzes the statistical correlation between the estimated and the measured supply current traces to extract the secret key. The existing power SCA countermeasures are mainly based on reducing the SNR of the leaked information, power balancing, or gate-level masking, each of which introduces significant power, area or performance overheads, which calls for an efficient generic countermeasure. This paper presents ASNI: Attenuated Signature Noise Injection, which is an energy-efficient generic countermeasure, and shows SCA resistance on the AES-128 encryption as an application. ASNI uses a shunt low-drop-out (LDO) regulator to suppress the AES current signature by ${>}200 \times $ in the supply current traces. The shunt LDO has been fabricated and validated in 130 nm CMOS technology. System-level implementation of the ASNI, with the AES-128 core operating at 40 MHz, shows that the system remains secure even after 1 M encryptions, with $\sim 25 \times $ reduction in power overhead compared to that of noise addition alone. [ABSTRACT FROM AUTHOR]

This paper presents a low-voltage low-phase-noise LC voltage-controlled-oscillator (VCO) with a novel two-tank transformer-feedback topology. The flicker noise up-conversion is suppressed by making the drain impedance of the cross-coupled transistors to be a real number at the second harmonic of the oscillation. The loaded quality factor is boosted and the noise contribution from the transconductor of the VCO is reduced by introducing a negative source impedance. A prototype VCO based on this topology is demonstrated in a 65 nm digital CMOS process. The VCO is operated from 23.9 to 26.9 GHz at a low supply voltage of 0.6 V, while achieving an ultra-low 1/ $f^{3}$ phase noise corner from 170 to 240 kHz across the tuning range. The phase noise is −110 dBc/Hz at 1 MHz frequency offset. The power consumption is 4.8 mW. The measurement results demonstrate that the VCO achieves a state-of-the-art phase noise performance in both the 1/ $f^{2}$ region and the 1/ $f^{3}$ region. [ABSTRACT FROM AUTHOR]

Body bias control is one of the most efficient means to reduce leakage power, adjust process variation, and apply performance boost. However, such control incurs a certain power overhead that has to be reduced, especially in ultra low-power systems. In order to exploit the advantages of body bias control while guaranteeing power efficiency, an on-chip control scheme is required. Conventionally, on-chip body bias control relies on the use of digital–analog converters. However, such analog circuits require a high power supply voltage and an additional power source, resulting in a considerable power overhead and an increased system cost. In this paper, an on-chip “Digitally assisted Automatic Body-bias Tuning” (DABT) scheme for ultra low-power systems is proposed and evaluated. The proposed scheme controls the body bias voltage so as to meet the timing constraints of a given target system. Since DABT is based on “Digitally assisted” circuitries, it can decrease the power supply voltage to near-threshold region and, therefore, a significant amount of power overhead can be reduced. The proposed system is fabricated with the 65-nm silicon on thin box (SOTB) process, a fully depleted silicon on insulator technology. We demonstrate that the chip can achieve the expected functionality, even with 0.35 V of power supply voltage, and with only a few micro watts of power overhead. Moreover, the efficiency of the proposed system is evaluated with a MIPS processor, adopted as a case study. According to the obtained evaluation results, the proposed system can enable 80% of leakage reduction while maintaining the frequency required to meet the timing constraints of the adopted target MIPS processor. [ABSTRACT FROM AUTHOR]

This paper proposed a high efficiency boost converter targeting thermoelectric generator energy harvesting. The proposed converter adopts the critical conduction mode rather than the discontinuous mode to reduce the conduction loss, which can improve the peak efficiency at high input power. To reduce the minimum input voltage, an adaptive on-resistance switch, which can automatically change the high side and low side on-resistance according to the input voltage, is used. To maximize the output power, a maximum power point tracking circuit is designed to track the internal source resistance. Radio frequency (RF) kick-up and low voltage startup are used to improve the cold start voltage. The proposed converter is implemented in a 0.18- $\mu \text{m}$ standard CMOS process, which occupies a chip area of about 0.48 mm2. Measurement results show that the peak efficiency of the converter can be up to 90.8% and 60% at 180 and 20 mV of the open-circuit voltage, respectively. Owing to the cold startup circuit, the proposed converter can start successfully with 260-mV open-circuit voltage or −16-dBm RF input. Moreover, the open-circuit voltage can be further lowered to 12 mV with 1.5- $\mu \text{W}$ output power after startup. [ABSTRACT FROM AUTHOR]

Spiking neural P (SN P) systems are a class of parallel computation models inspired by neurons, where the firing condition of a neuron is described by a regular expression associated with spiking rules. However, it is NP-complete to decide whether the number of spikes is in the length set of the language associated with the regular expression. In this paper, in order to avoid using regular expressions, two major and rather natural modifications in their form and functioning are proposed: the spiking rules no longer check the number of spikes in a neuron, but, in exchange, a polarization is associated with neurons and rules, one of the three electrical charges −, 0,+. Surprisingly enough, the computing devices obtained are still computationally complete, which are able to compute all Turing computable sets of natural numbers. On this basis, the number of neurons in a universal SN P system with polarizations is estimated. Several research directions are mentioned at the end of this paper. [ABSTRACT FROM AUTHOR]

This paper presents a novel control technique for a wide output voltage range digitally controlled SIDO boost converter. It employs minimum phase conditions reported in refid="ref1"/ , refid="ref2"/ and extends the same to SIDO boost converter to eliminate the effect of RHP zero. Further, the proposed work employs input-output linearization technique refid="ref3"/, refid="ref4"/ to linearize the control-to-output transfer function across different operating points to achieve improved stability under unbalanced loads and a wide output voltage range on each output of the proposed SIDO boost power converter. The SIDO boost regulator was verified experimentally for an input voltage of 3.3 V and a maximum simultaneous load current of 350 mA on each output. Measurement results demonstrate that the proposed design achieves a wide output voltage range of 4.8 V–13.75 V, with ability to dynamically transition across these different output voltages in both small and big voltage steps. [ABSTRACT FROM AUTHOR]

A CMOS $4\times $ subharmonic mixer (SHM) with an internal phase error correction mechanism operating at mm-wave frequencies is proposed in this paper. The SHM operates with a 81-GHz RF input signal and a 20-GHz local oscillator (LO) signal to produce a 1-GHz output. The single ended input is converted into octet-phase, through an active input balun, an active polyphase filter, and certain phase adders. A phase calibration technique is employed, to compensate the phase deviations due to the circuit mismatches, offering a ±5° phase adjustment between the generated phase shifts. By this technique, a close to optimal performance can be obtained, especially in terms of conversion gain and LO-IF isolation, which can be improved by 1.5 to 7.5 dB and by 5 to 17 dB, respectively. Fabricated in a 65-nm CMOS low-power technology, the prototype exhibits a conversion gain of −8 dB (without using an IF amplifier), a 1 dB compression point ( $\text{P}_{\mathrm {1dB}}$ ) of −10 dBm, a third-order intercept point (IIP3) of 1 dBm, and a noise figure of 15 dB. The power consumption is 213 mW, and port-to-port isolation is >70 dB. The achieved performance compares well with the state of the art at these high frequencies despite the use of a slower CMOS process. [ABSTRACT FROM AUTHOR]

This paper proposes a novel approach to enhance the STT-MRAMs read margin based on the concept of dynamic reference (DR). Our dynamic reference scheme dynamically adjusts the sense amplifier reference voltage according to the bitline voltage, aiming to widen the difference between the bitline and the reference voltage (i.e., the read margin). As a result, larger variations can be accommodated, thus improving the read robustness and substantially reducing the read failure rate. This DR scheme does not require any change in the bitcell and requires minimal modifications of conventional arrays, hence it can be jointly used with existing assist techniques enhancing the read robustness. From Monte Carlo simulations in 65 nm, the proposed DR scheme improves the read bit error rate by two orders of magnitude across a wide range of voltages (0.75–1.2 V) compared with the conventional voltage sensing scheme. This is achieved at 0.3% area overhead, less than 15% performance degradation, and less than 25% energy penalty. Furthermore, the joint adoption of the DR approach and switched-cap bitline boosting further reduces the sense amplifier area by 25% at iso-failure rate, and reduces the energy by 6–10% compared with the standalone DR. [ABSTRACT FROM AUTHOR]

New tradeoff metric of the energyn-delay product (EnDP, n>1) for energy efficiency design is proposed in this paper. Compared with the conventional energy-delay product metric, the new metric puts more weight on energy than delay, more suitable for those power-critical mid/low-speed applications. We first establish the theoretical model, and then provide comprehensive optimum design points for various processes and applications as energy-efficient design guidelines. We also find that the optimum EnDP operation coincides with the well-known near-threshold methodology, and discuss the challenges and possible design methods. An enhanced hierarchical bit-line structure along with 8T-SRAM cell and local read/write assist circuits is introduced for robust operation and energy efficiency improvement, facilitating EnDP methodology. Finally, an 8-kb SRAM macro in 180-nm CMOS technology for ultra-low-power applications is designed and fabricated to validate the methodology, where a supply voltage of 1.54 \textV\mathrm {TH} is applied to obtain maximum energy efficiency based on E2DP metric. The minimum E2DP of 610 pJ2/GHz is obtained at 0.65 V, fitting the theoretical analysis accurately. Power consumption at 0.65 V is 14.89~\mu \textW , only 2.6% of that at nominal voltage, 1.8 V. The test chip can operate correctly from 1.8to 0.6 V with frequency scaling from 400 to 15.5 MHz. [ABSTRACT FROM PUBLISHER]

Nonvolatile memory (NVM) based neural network can directly perform in situ computation in memory to significantly reduce energy consumption resulting from the data movement. However, the energy consumption by the analog-to-digital converter (ADC) restricts the efficiency of the mixed-signal in-memory computing macro. The rate coding spike-driven in-memory computing macro can increase the energy efficiency via eliminating the ADC, but the improvement is limited because substantial energy is consumed for the coding of multiple spikes. In this work, we propose a discrete temporal coding spike-driven in-memory computing macro, including input coding scheme, weight mapping method, and improved leaky integrate-and-fire (LIF) neuron circuit, to perform the efficient forward inference of deep neural networks based on NVM array. We then optimize the designment of the proposed in-memory computing macro to mitigate the neural network accuracy loss due to the nonlinearity of the LIF neuron and voltage drop caused by interconnect resistance. Because the temporal coding scheme reduces spike numbers and the improved-LIF circuit simultaneously integrates two bit-lines current corresponding to positive and negative weight, the proposed macro achieves 46.63TOPS/W energy efficiency and 1.92TOPS throughput for 3bit temporal coding precision. [ABSTRACT FROM AUTHOR]

This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-b length to improve variation tolerance and performance, and to reduce disturb while maintaining manufacturability. The design employs threshold power gating to facilitate lower NAP (Sleep) mode voltage/power and faster wake-up for the cell array, and low-swing global read bit-line (GRBL) with integrated low-swing voltage precharger to improve read performance and reduce the dynamic read power. A cell Vtrip-tracking write-assist (VTWA) lowers the selected sub-array supply to cell inverter trip voltage to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected sub-array. The 256-kb test chip is implemented in UMC 28-nm high- $\kappa $ metal-gate (H \kappa $ MG) CMOS technology with macro area of 1058.22\times 374.76~\mu \text{m}^{2} . Error-free full functionality is achieved from 0.9 down to 0.5 V (limited by read VMIN without redundancy. The low-swing GRBL reduces dynamic power by 6.5% (8.0%) at 0.9 V (0.6 V). The VTWA improves the write VMIN by 75 mV (from 0.525 to 0.45 V). The measured maximum operation frequency is 735 MHz (20 MHz) at 0.9 V (0.5 V), TT corner, 25°. [ABSTRACT FROM AUTHOR]

In this paper, the classical CMOS Schmitt trigger (ST) operating in the subthreshold regime is analyzed. The complete DC voltage transfer characteristic of the CMOS ST is determined. The metastable segment of the characteristic is explained in terms of the negative resistance of the NMOS and PMOS subcircuits of the ST. Small-signal analysis is carried out to determine the minimum supply voltage at which the hysteresis appears and to obtain a rough estimation of the hysteresis width. It is shown that the theoretical minimum supply voltage required to obtain hysteresis is 2ln( $2+\surd 5$ )kT/q = 75 mV at room temperature. A test chip with CMOS Schmitt triggers was designed and fabricated in a 180 nm technology in order to study their operation at supply voltages between 50 mV and 1000 mV. [ABSTRACT FROM AUTHOR]

Nonvolatile processor (NVP) attracts more and more attentions for its immunity to power loss in energy harvesting scenarios. The overall performance of an NVP is determined by its sleep and wake-up speeds, which refer to how fast the NVP can turn itself off and on when a sudden power failure occurs. To the best of our knowledge, this paper is the first work to improve the system-level sleep/wake-up speed of an energy harvesting NVP. A hybrid CMOS/ferroelectric nonvolatile flip-flop (nvFF) and a high-speed voltage detector are designed and integrated in the proposed NVP to jointly minimize its sleep and wake-up time. Measurement results demonstrate 46~\mu \text s wake-up time and 14~\mu \text s sleep time, which is up to 18 and 24 times speedup over existing works. This approach not only improves the robustness of the NVP to power fluctuations but also brings significant advantages for better utilization of harvested energy. [ABSTRACT FROM AUTHOR]

This paper presents a physics-based mathematical model for anionic memristor devices. The model utilizes Poisson- Boltzmann equation to account for temperature effect on device potential at equilibrium and comprehends material effect on device behaviors. A detailed MATLAB based algorithm is developed to clarify and simplify the simulation environment. Moreover, the provided model is used to simulate and predict the effect of oxide thickness, material type, and operating temperatures on the electrical characteristics of the device. The parameters of the proposed model are tuned and validated using experimental data of a fabricated wire based NbO1–x junction. This device is attractive for neuromorphic and computing applications, where multilevel state is desirable. The value of this contribution is to provide a framework intended to simulate anionic memristor devices using correlated mathematical models. In addition, the model can be used to explore device materials and predict its performance. [ABSTRACT FROM PUBLISHER]

In this paper the stability and sensitivity function of three basic dc-dc converter with the consideration of circuit parasitics has been analyzed for analog and digital controller implementation. The steady state and small-signal analysis has been used to derive the mathematical expressions for uniformly sampled voltage-mode controlled converters. The effect of digital controller using the ratio of sampling to carrier frequency has been analyzed. The sampling frequency limits the voltage gain in the stepped manner and also affects the stability of the digitally controlled converter. The sensitivity function has been defined for voltage gain with respect to various system parameters. The maximum affected regions on duty ratio scale with corresponding parasitic variable have been discussed. The detailed stability analysis has been carried out for digitally implemented three basic dc-dc converters, i.e., buck, boost, and buck-boost circuits. The analytical results are verified with the simulations performed in PSCAD/EMTDC. An FPGA controller is considered as digital controller for the dc-dc converter and verification of the results through experiment. [ABSTRACT FROM PUBLISHER]

This paper presents a micropower audio delta-sigma (\Delta\Sigma) modulator for mobile applications. This work employs power-efficient integrators based on the dynamic bias inverter, which consists of a cascode inverter, a floating current source and two offset-storage capacitors. The quiescent current of the inverter is copied from the floating current via offset-storage capacitors and the speed limitation caused by the cascode transistors in the inverter is resolved by using active parasitic compensation. This maximizes both {g}_{m}/{I}_{D} ratio and slew rate of the inverter-based integrator, while compensating process, voltage, and temperature (PVT) variations. To verify the effectiveness of the proposed technique, a single-bit third-order \Delta\Sigma modulator is implemented in a 0.18 \mu\text{m} CMOS technology. The prototype modulator achieves 97.7 dB SNDR, 98.6 dB SNR, and 100.5 dB DR in a 20-kHz signal bandwidth, while consuming only 300-\mu\text{W}$ from a 1.8 V supply. This corresponds to a state-of-the-art Schreier's FoM of 178.7 dB. The results are fully verified under variable supplies and temperatures. [ABSTRACT FROM PUBLISHER]

This paper presents a rigorous dc solution of 3-D Partial Element Equivalent Circuit models. Despite the decoupling of magnetic and electric fields at dc, the correct solution is not trivial. The proposed one is based on a two-step process where first the magnetostatic problem is solved; then, the electrostatic problem is faced by using the solution of the magnetostatic problem as boundary conditions and enforcing the neutrality of disconnected objects. A systematic partition computation is presented which is based on graph algorithms. Applications to the dc analysis of multiple connected and/or disconnected conductors demonstrate the accuracy of the proposed method when compared to the steady state analysis under step excitation. [ABSTRACT FROM AUTHOR]

This paper presents a novel charge-recycling SRAM assist circuit to reduce the dynamic power consumption of SRAM assist technique. By collaboratively combining the read and write assist schemes, the wasted charge in conventional read assist circuit can be efficiently recycled in write assist technique. In order to compare the dynamic power consumption at ISO minimum operating voltage (V\mathrm{MIN}) condition, the most probable failure point (MPFP) simulations are performed using 14 nm FinFET technology model. Compared to the conventional assist schemes, thanks to the charge-recycling, 41% power saving, and 2.3% area reduction can be achieved by using the proposed SRAM assist circuit. [ABSTRACT FROM PUBLISHER]

This paper introduces a push-pull class-EM power amplifier for achieving low harmonic contents and high output power. By applying the push-pull configuration of the class-EM power amplifier, the proposed amplifier achieves an extremely lower total harmonic distortion (THD) and about four times higher output power than the conventional single class-EM power amplifier. Design curves of the proposed amplifiers for satisfying the class-EM ZVS/ZDVS/ZCS/ZDCS conditions are given. A design example is shown along with the PSpice-simulation and experimental waveforms for 1-MHz amplifier, considering the MOSFET drain-to-source nonlinear parasitic capacitances, MOSFET switch-on resistances, and equivalent series resistance of the inductors. The waveforms from the PSpice simulation and circuit experiment satisfied all the switching conditions, which has shown the accuracy of the design curves given in this paper and validated the effectiveness of the push-pull class-EM power amplifier. [ABSTRACT FROM PUBLISHER]

On-chip process monitor/sensor circuits capture the process corner of a chip in the postfabrication stage. Logic-NMOS and logic-PMOS based sensors, however, fail to capture the process corners for memories, as bitcells have a different implant from logic cells. In this paper, a novel on-chip bitcell-based process monitor (BPMON) circuit is implemented that distinguishes between and detects the standard global corner of memories in any chip. It leverages a current-mirror and a near-threshold biased bitcell array structure that changes the output voltage of the circuit in accordance with changes in the process corner. BPMON separately tracks bitcell NMOS and bitcell PMOS process corners. Silicon data from over 100 chips from five wafers in 28 nm CMOS shows correct bitcell process corner predictions. These predictions show the expected strong correlation with read and write vccmin, enabling vccmin to be lowered below specifications while still achieving a 100% yield. [ABSTRACT FROM PUBLISHER]

Although near-threshold voltage (NTV) operation is an attractive means of achieving high energy efficiency, it can degrade the circuit stability of static random access memory (SRAM) cells. This paper proposes an NTV 7T SRAM cell in a 14 nm FinFET technology to eliminate read disturbance by disconnecting the path from the bit-line to the cross-coupled inverter pair using the transmission gate. In the proposed 7T SRAM cell, the half-select issue is resolved, meaning that no write-back operation is required. A folded-column structure is applied to the proposed 7T SRAM cell to reduce the read access time and energy consumption. To reduce the standby power, the proposed 7T SRAM cell uses only a single bit-line for both read and write operations. To achieve proper “1” writing operation with a single bit-line, a two-phase approach is proposed. Compared to the conventional 8T SRAM cell, the proposed 7T SRAM cell improves the read access time, energy, and standby power by 13%, 42%, and 23%, respectively, with a 3% smaller cell area. [ABSTRACT FROM PUBLISHER]

Two important drawbacks of parallel coupled LC quadrature oscillators (P-QOSC) which have not heretofore been addressed thoroughly in the literature are obviated simultaneously in this paper. The first, has to do with the inevitable off-tune operation of the tank which results in quality factor (Q) degradation, and hence, phase noise deterioration. The other, stems from process, voltage, and temperature (PVT) variations which exacerbate quadrature accuracy. Here, a feedback loop is presented which generates a control signal by mixing the quadrature outputs and tunes the injection strength in the coupled oscillators autonomously. A complex coupling factor is implemented which compensates the phase error to prohibit phase noise degradation. The operation of proposed loop is comprehensively studied mathematically. Measurement results of a 0.18 \mu{\text m} CMOS prototype with an active area of 0.5 {\text{mm}}^{2}$ and an overall power consumption of 5 mW corroborate the functionality of the proposed method. Finally, experimental results prove FoM of 185 dB for the core oscillator and a quadrature phase error of less than 0.8^{\circ}. [ABSTRACT FROM PUBLISHER]

Noise shaping digital quantizers, most commonly digital delta-sigma $(\Delta\Sigma)$ modulators, are used in fractional- $N$ phase-locked loops (PLLs) to enable fractional frequency tuning. Unfortunately, their quantization noise is subjected to nonlinear distortion because of the PLL's inevitable non-ideal analog circuit behavior, which induces spurious tones in the PLL's phase error. Successive requantizers have been proposed as $\Delta\Sigma$ modulator replacements with the advantage that they reduce the power of these spurious tones. However, the quantization noise from previously published successive requantizers is only first-order highpass shaped, so it usually causes more PLL phase noise than that from the second-order and third-order $\Delta\Sigma$ modulators commonly used in PLLs. This paper presents second-order and third-order successive requantizers to address this limitation. Additionally, successive requantizer design options are presented that result in either lower-power spurious tones or lower phase noise compared to $\Delta\Sigma$ modulators when used in PLLs. [ABSTRACT FROM PUBLISHER]

This paper employs a time-variant model to determine the exact small-signal loop transmission of second-order charge-pump phased-locked loops. The model predicts that a loop bandwidth of close to half the input frequency can be achieved. The large-signal behavior is also analyzed and two modes of oscillation are identified. The results are confirmed by means of circuit simulations. [ABSTRACT FROM PUBLISHER]

Proposed in this paper is a general parasitic-compatible LCR matching method suitable for $N$-path filter. Analysis of a conventional $L$-type matching is extended to accommodate the case of the $N$- path filter, where the different impedances of the band limited input matching network at multiple local oscillation (LO) harmonic frequencies have to be taken into consideration. Compared to the ideally wideband transformer matching technique, the proposed LCR method has advantages of smaller size and better harmonic folding rejection ratio, while keeping the same properties, such as impedance matching, in-band voltage gain, noise figure and ultimate rejection. Based on the derived equations, the procedure to determine the values of the matching components for given rejection specs has been described using design examples. [ABSTRACT FROM PUBLISHER]

The extension and size of the power grid is expected to increase in the near future. Managing such a system presents challenging control problems that, so far, have been approached with classical control techniques. However, large scale systems of interconnected nodes fall within the framework of the emerging field of complex networks. This paper models multi-terminal VSC-HVDC systems as a complex dynamical network, and derives conditions ensuring bounded synchronization of its trajectories for a family of controllers. The obtained results are validated via numerical simulations. [ABSTRACT FROM PUBLISHER]

Field Programmable Gate Arrays (FPGAs) can benefit non-volatility and high-performance by exploiting Resistive Random Access Memories (RRAMs). In RRAM-based FPGAs, the memories do not only replace the SRAMs and store configurations, but they can also replace the transmission gates and propagate datapath signals. The high-performance achievable by RRAM-based FPGAs comes from the fact that the on-resistance of the memory devices R_\mathrmLRS is smaller than the equivalent resistance of a transmission gate. Efficient programming structures for RRAMs should provide high current density with a small area footprint, to obtain a low R_\mathrmLRS. In this paper, we first examine the efficiency of the widely-used 2Transistor/1RRAM (2T1R) programming structure and identify four major limitations of the 2T1R structure. To overcome these limitations, we propose a 2Transmission-Gates/1RRAM (2TG1R) and a 4Transistor/1RRAM (4T1R) programming structures. We perform both theoretical analysis and electrical simulations on the evaluated programming structures. 4T1R programming structure is the best in terms of current density with 1.4 \times and 1.1 \times as compared to 2T1R and 2TG1R counterparts, respectively. We also investigate the effect of boosting the programming voltage V_\mathrmprog of the programming structures. Experimental results show that boosting V_\mathrmprog for all the programming structures improves driving current of the evaluated programming structures by 3 $\times$ and area efficiency by 1.7 $\times$ on average. [ABSTRACT FROM AUTHOR]

This paper presents comprehensive analyses of power-performance tradeoffs in current-mode logic (CML)-based transmitters via equation-based optimization and provides practical design guidelines that can help achieving optimum power efficiency. An accurate equation-based optimization framework was developed for this purpose, and using this framework, key circuit-level design parameters were found with specific design specifications and process technologies. The proposed optimization framework can determine optimum clock edge-rate (i.e., ratio of rise/fall time to clock period) and inter-stage voltage swings that enable significant power savings without affecting performance. Various transmitter design tradeoffs were analyzed for 45-nm, 65-nm, and 90-nm technologies considering data rate, clock edge-rate, and inter-stage swing optimization. Based on the analysis results, we determined the most energy-efficient data rate that can be achieved with acceptable power overhead for each technology node. Also, we identified the optimal clock edge-rate and inter-stage voltage swings in CML gates that achieved minimum transmitter power dissipation. Our analysis results indicate that, when properly optimized, overall transmitter power consumption can be reduced by up to 43% with inter-stage swing optimization with all other design constraints held constant. [ABSTRACT FROM AUTHOR]

A disturbance observer-based control (DOBC) approach is proposed in this paper for control design and qualitative robustness analysis of PWM-based DC-DC buck power converters. A disturbance compensation gain is constructed for the composite control algorithm to cancel the unmatched uncertainties in the output voltage channel. Rigorous criterion is provided to show the quantitative robustness between controller parameters and circuit uncertainties. The DOBC approach delivers not only a promising disturbance rejection performance but also a superior property of tracking performance recovery. The feasibility and efficiency of the proposed approach is validated by experimental results based on LabVIEW real-time control test setup. [ABSTRACT FROM AUTHOR]

We present in this paper an ultra low power ISM band RF receiver intended for implantable biomedical devices. The proposed circuit, which represents the reception part of a new energy-efficient RF FSK transceiver, consist of an FSK receiver (Rx) with OOK fully passive wake-up device (WuRx). This WuRx is batteryless with energy harvesting technique which plays an important role in making the RF transceiver energy-efficient. This proposed receiver is achieved with a reduced hardware architecture which does not use an accurate local oscillator, high Q external inductor and I/Q signal path. The circuit is base on a dual injection locked FSK-to-ASK conversion technique. The circuit is implemented in IBM 0.13 \mum CMOS technology with 1.2 V supply voltage. This WuRx achieves a data rate of 100 kbps for 0.2 \muW power dissipation at -53 dBm input signal. The Rx shows -78 dBm sensitivity for 8 Mbps data rate while consuming 639 \muW power. [ABSTRACT FROM PUBLISHER]

In the applications of biometric authentication and video surveillance, the image sensor is expected to provide certain degree of trust and resiliency. This paper presents a new low-cost CMOS image sensor based physical unclonable function (PUF) targeting a variety of security, privacy and trusted protocols that involves image sensor as a trusted entity. The proposed PUF exploits the intrinsic imperfection during the image sensor manufacturing process to generate unique and reliable digital signatures. The proposed differential readout stabilizes the response bits extracted from the random fixed pattern noises of selected pixel pairs determined by the applied challenge against supply voltage and temperature variations. The threshold of difference can be tightened to winnow out more unstable response bits from the challenge-response space offered by modern image sensors to enhance the reliability under harsher operating conditions and loosened to improve its resiliency against masquerade attacks in routine operating environment. The proposed design can be classified as a weak PUF which is resilient to modeling attacks, with direct access to its challenge-response pair restricted by the linear feedback shift register. Our experiments on the reset voltages extracted from a 64 \times 64 image sensor fabricated in 180 nm 3.3 V CMOS technology demonstrated that robust and reliable challenge-response pairs can be generated with a uniqueness of 49.37% and a reliability of 99.80% under temperature variations of 15\sim 115~^\circC and supply voltage variations of 3\sim 3.6\ V. [ABSTRACT FROM AUTHOR]