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A continuous-time (CT) second-order $\Delta \Sigma $ current-to-digital converter (CDC) is presented in this paper. The proposed CDC uses two current-controlled ring oscillators as phase-domain integrators to achieve second-order quantization noise shaping. The proposed CDC uses a current-reuse architecture in which the feedback digital-to-analog converter (DAC) is used to bias the first integrator which results in significant power and noise reduction compared to previous prototype. Excess loop delay in the proposed CDC is countered through judicious selection of loop parameters and no auxiliary DAC is used for loop delay compensation. A prototype CDC is implemented in 65nm CMOS and achieves 76dB dynamic range at a bandwidth of 0.2MHz from 1V supply with a walden FoM of 48fJ/step which is $9\times $ improvement on the state-of-the-art. [ABSTRACT FROM AUTHOR]

This work presents a low-power all-digital approach to multiphase delay locked loop (DLL) design by the use of a scalable phase-to-digital converter (PDC) based on asynchronous sampling. The PDC is used as a linear phase detector (PD) with the ability to measure any phase difference leading to a shorter delay line with less power consumption. Two different approaches for the delay cell implementation are investigated. The digitally controlled shunt-capacitor inverter (SCI) delay cell leads to an extremely small design with the delay line being the only analog component, while the voltage controlled current-starved inverter (CSI) delay cell has a lower power consumption and less jitter. The proposed design procedure of the SCI based DLL allows fast simulation using Verilog based models since no analog low pass filter is required. Using the proposed modeling technique for the PDC, the behavior of the DLL can be estimated based on input clock jitter specifications. The SCI and CSI based multiphase DLL designs are fabricated in a 65nm CMOS process operated from a 1.2V supply. The proposed SCI based DLL occupies only 0.0048mm2 of active area and consumes 2.25mW at 2.5GHz input frequency with a 622.6MHz sample clock. The RMS jitter of the circuit is 1.2 ps and 1.4 ps for the DLL loop and the phase shifter loop, respectively. The RMS jitter is significantly reduced with the CSI based DLL to 0.86 ps and the power consumption of 2.64mW at 4GHz input frequency with a 996.1MHz sample clock provides an improved power efficiency compared to the SCI based DLL. As a trade-off, the area is increased to 0.0085mm2 due to the use of a $\Delta \Sigma $ modulator and an analog low pass filter. [ABSTRACT FROM AUTHOR]