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This paper proposes a novel all-digital background calibration of timing mismatch for a time-interleaved analog-to-digital converter (TIADC). For two different calibration strategies, the absolute calibration and the relative calibration, the inductive expressions of modulation matrices are derived from the coefficient matrices provided by different estimation methods. Based on the modulation matrix, we develop a digital calibration architecture, which enables the output of TIADC to be modulated firstly before being corrected, so the costly matrix multiplication processing can be avoided. This calibration architecture also enables the estimation process of each channel to be independent and can be executed simultaneously, which accelerates the convergence speed of the timing mismatch. We show the efficiency of the calibration structure by simulations, including examples from the literature. Numerical simulation demonstrates that the convergence speed of the timing mismatch has been improved by at least 27%, compared with the estimation method depending on the specified reference channel. The result of FPGA-based hardware implementation shows that the spurious-free dynamic range (SFDR) is improved by 37.63dB. [ABSTRACT FROM AUTHOR]

With the quick expansion of signal bandwidth in communication systems, time-interleaved Analog-to-Digital Converters (TI-ADC) provide quick pathway to very high sampling speed. Nonetheless, mismatches among the sub-ADC channels are major performance limiting factors for TI-ADCs. With the scaling of CMOS processes, all-digital background calibration techniques with blind estimation have been actively pursued in recent years to compensate for the mismatches from TI-ADCs. In this paper, a new all-digital background calibration technique is introduced. The technique achieves blind estimation by exploiting the correlation difference between the signal component and the mismatch spurs. This method can process wideband signals and can be implemented with low calibration overhead. The technique is verified with extensive simulations over a 2GS/s 12bit 16-channel ADC. Simulation shows that, with ADC mismatch spurs over −40dBc, the new technique can reliably suppress the spurs to be lower than −80dBc within the duration of about $1.2\times 10^{6}$ samples with a typical wideband OFDM (orthogonal frequency-division multiplexing) signal. [ABSTRACT FROM AUTHOR]

Time-interleaving (TI) is a major trend for high-speed ADC designs. The major limitation of TI-ADC is the mismatches among ADC channels. Calibration techniques have been actively pursued to compensate the mismatches. In this paper, we present a new spectral calibration technique for TI-ADC. Although the technique does not run in the background, it does not need external calibration signals and has no constraint on the input signal, which is similar to blind estimation. Compared to benchmark designs, the new technique involves much less calibration hardware overhead, and calibrates all mismatches with much less time. In practice, this efficient technique can run repetitively to track the environment changes. It addresses the needs from practical TI-ADCs well. The technique is verified with extensive simulations on a 2GS/s 12-bit 16-channel ADC. With mismatch spurs over −40dBc, the technique can reliably suppress the spurs to be lower than −80dBc within about 4000 samples without the need of iteration. [ABSTRACT FROM AUTHOR]