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This paper presents a self-biased subthreshold CMOS voltage reference for low-power and low-voltage applications. To achieve near-zero line sensitivity and high PSRR, a compensation structure utilizing the drain-induced-barrier-lowering (DIBL) effect is proposed to sink a supply dependent current from the output branch of a self-biased CMOS reference, which cancels the bias current’s dependence on the supply voltage due to the DIBL effect. Fabricated in a 0.18- $\mu \text{m}$ CMOS technology, the measurement results demonstrate that the proposed circuit could operate under a minimum supply voltage of 0.34 V and generate a reference voltage of 147 mV, while consuming only 48 pW power. The PSRRs measured at 1 Hz and 10 kHz are −70.6 dB and −50.2 dB, respectively. For 39 measured samples, the mean line sensitivity is 0.019%/V in a supply voltage range from 0.34 to 1.8 V, and the average temperature coefficients before and after trimming are 64.81 and 10.06 ppm/°C in 0 ~ 100 °C temperature range, respectively. The total area of the voltage reference circuit is 0.0332mm2. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and high-precision voltage and current reference (VCR) in one simple circuit. The voltage reference is derived from the threshold voltage difference between an I/O (i.e., 3.3-V NMOS) and standard (i.e., 1.8-V NMOS) transistors with temperature-independent bias current, and the current reference is the voltage reference divided by a temperature-insensitive resistor. The resistor is made up by series connection of a proportional-to-absolute-temperature (PTAT) NWELL resistor and a complementary-to-absolute-temperature (CTAT) high-resistance poly resistor in series. Implemented in a standard 0.18- $\mu \text{m}$ CMOS process, the proposed VCR circuit takes an active area of only 0.055 mm2. The measured voltage and current references ($\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$) at room temperature are 368 mV and 9.77 nA, respectively. The measured average temperature coefficient (TC) of $\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$ are 43.1 ppm/°C and 149.8 ppm/°C over a temperature range of −40~125°C with one-time trimming and the variation coefficients are 0.35% and 1.6%, respectively. The measured voltage and current line sensitivities are 0.027%/V and 0.6%/V, respectively. The minimum supply voltage is 0.7 V with a total power consumption of 28 nW. The measured power supply ripple rejection (PSRR) of $\text{V}_{\mathrm {ref}}$ is −65 dB @DC and −39.4 dB at frequencies higher than 1 Hz. [ABSTRACT FROM AUTHOR]

A novel virtual reference concept is introduced in this paper to design accurate, mostly digital, software-defined, process-supply-and-temperature (PVT)-independent voltage references suitable to replace conventional analog reference circuits in present day, low voltage, aggressively scaled, mainly digital integrated systems. The operation and the performance of references based on the proposed approach are tested by computer simulations and experiments carried out on a proof-of-concept, microcontroller-based prototype, reporting a measured thermal drift of 16 ppm/^\circC in a range from -\10~^\circC to 100 ^\circC and a line regulation of 0.15%/V. The advantages in terms of costs and performance of the proposed digital references in comparison with state-of-the-art analog solutions are finally discussed. [ABSTRACT FROM AUTHOR]

In this article, a digitally controlled voltage-mode buck converter with embedded transient improvement using delay line-based control techniques is presented. Two voltage-controlled delay lines (VCDL’s) are used to convert the difference between the feedback and reference voltages to a delay time difference. The delay difference is then fed to the multiple-outputs bang-bang phase detector (MOBBPD), which converts the input delay difference to multiple-bits digital codes in a simple nonlinear way. The MOBBPD scheme leads to high resolution for small output ripple and improved response when large load transient happens in a low-cost way. A digital loop filter (DLF) accumulates the MOBBPD output codes to control the duty cycle through a novel digital pulse width modulator (DPWM) to regulate the output voltage. By designing the coefficients of the DLF, a type-II compensator can be achieved through the integral and proportional paths to make the loop stable. The proposed DPWM, which consists of a divide-by-8 frequency divider, two delay lines and a few simple digital logics, achieves a wide tunable range of duty cycle under various process corners and supply voltages. A proof-of-concept design of the proposed buck converter was fabricated in a standard $0.18~\mu \text{m}$ CMOS technology. The measured results show that it achieves a very wide output voltage range from 0.1 V to 3.5 V for a input supply range from 2.4 V to 3.6 V. With a 400 mA step in the load current, the overshoot/undershoot is less than 87 mV and the 1% settling time is less than $16~\mu \text{s}$. The peak efficiency is 95.2% with 250 mA load current at 2.4 V output voltage with 3.3 V input voltage. [ABSTRACT FROM AUTHOR]

A programmable voltage detector (PVD) for battery management is proposed to achieve the programmability of the detection voltage ($V_{\mathrm {DETECT}}$). Thanks to the programmability, users can set an appropriate $V_{\mathrm {DETECT}}$ for battery management considering the operating voltage of the battery. For batteries including Li-ion and NiMH batteries, a PVD is required to achieve wide programmed $V_{\mathrm {DETECT}}$ range from 1.0 to 4.35 V with a fine voltage step of ±42 mV. Furthermore, the power consumption of the PVD must be minimized since the PVD is always operating in battery management. To achieve both the target programmability of $V_{\mathrm {DETECT}}$ and the low power consumption of the PVD, a programmable voltage reference (PVREF) using a fine voltage-step subtraction (FVS) method is proposed. The FVS is a combination of fine and coarse programming for the output of the PVREF, which achieves a fine voltage step and a wide programmable range of $V_{\mathrm {DETECT}}$ achieving both a low temperature coefficient of $V_{\mathrm {DETECT}}$ and low power consumption of the PVD. The measurement results of the PVD fabricated in a 250-nm CMOS process show a current consumption of the PVD of 1.2 nA at 3.5 V and a temperature coefficient of $V_{\mathrm {DETECT}}$ of 0.28 mV/°C. The PVD enables the widest programmable range of $V_{\mathrm {DETECT}}$ from 0.90 to 4.39 V, fine $V_{\mathrm {DETECT}}$ resolution of ±31.5 mV, and 56-level linear, monotonic programmability of $V_{\mathrm {DETECT}}$. [ABSTRACT FROM AUTHOR]

A galvanic isolated amplifier based on SAR converters architecture is presented which realizes chip level isolation in both the power and signal domains. The compact IC package contains an integrated isolated power converter which includes on-chip transformer, oscillator and rectifier, digital isolators based on on-chip transformers, a front-end programmable gain amplifier, a SAR ADC, a complementary charge redistribution DAC, and post filters to reconstruct and smooth the linear signal. The symmetric implementation of the SAR ADC and DAC realizes the charge balance between the input side and the output side, where an inherent linear transfer function is achieved. The sampling clock comes from an on-chip oscillator of poor jitter performance which limits the SNR performance of the ADC. With the correlated clock for the DAC reconstruction, the close-in phase noise from the clock generator is attenuated so that the SNR performance of the overall isolated amplifier is not sensitive to the jitter from the sampling clock. This fully integrated solution displaces the traditional bulky hall-effect sensors, and enables precise and fast isolated voltage or current sensing applications such as photovoltaic inverters. The isolated amplifier, with the ability to measure both large currents and small dc injection currents in a single solution, can contribute compactly and efficiently to smart grid integration circuitry. The system-in-package achieves less than 1 mV total offset and 71.9 dBFS SNR in a bandwidth of 200 kHz. It achieves an isolation working voltage rating of 600 Vrms and 5 kVrms over 1 min duration. [ABSTRACT FROM PUBLISHER]