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Nonvolatile memory (NVM) based neural network can directly perform in situ computation in memory to significantly reduce energy consumption resulting from the data movement. However, the energy consumption by the analog-to-digital converter (ADC) restricts the efficiency of the mixed-signal in-memory computing macro. The rate coding spike-driven in-memory computing macro can increase the energy efficiency via eliminating the ADC, but the improvement is limited because substantial energy is consumed for the coding of multiple spikes. In this work, we propose a discrete temporal coding spike-driven in-memory computing macro, including input coding scheme, weight mapping method, and improved leaky integrate-and-fire (LIF) neuron circuit, to perform the efficient forward inference of deep neural networks based on NVM array. We then optimize the designment of the proposed in-memory computing macro to mitigate the neural network accuracy loss due to the nonlinearity of the LIF neuron and voltage drop caused by interconnect resistance. Because the temporal coding scheme reduces spike numbers and the improved-LIF circuit simultaneously integrates two bit-lines current corresponding to positive and negative weight, the proposed macro achieves 46.63TOPS/W energy efficiency and 1.92TOPS throughput for 3bit temporal coding precision. [ABSTRACT FROM AUTHOR]

This paper presents a low-power compact analog circuit for processing time varying signals. The proposed circuit implements temporal differentiation, amplification and rectification, i.e., separation of outputs into on and off pathways. It is based on a hysteretic differentiator circuit, commonly used in neuromorphic vision sensors to implement temporal edge detection. This paper presents a thorough analysis of the original circuit and identifies the source of the problems and limitations it has for processing real-world sensory signals. The steps required to solve this problem are presented as well as an extended circuit with tunable gain and adaptable threshold that allows thresholding of small temporal changes (noise) and high-pass filtering of large temporal changes. The new circuit proposed is particularly suited for focal plane implementation of both gradient based and token based motion algorithms that require robust detection of temporal discontinuities. The circuit has been designed and successfully integrated into a 64 × 1 test prototype motion chip, fabricated in standard 350 nm CMOS technology. The paper provides extensive experimental characterization results. [ABSTRACT FROM PUBLISHER]

This paper addresses the global stabilization of fractional-order memristor-based neural networks (FMNNs) with time delay. The voltage threshold type memristor model is considered, and the FMNNs are represented by fractional-order differential equations with discontinuous right-hand sides. Then, the problem is addressed based on fractional-order differential inclusions and set-valued maps, together with the aid of Lyapunov functions and the comparison principle. Two types of control laws (delayed state feedback control and coupling state feedback control) are designed. Accordingly, two types of stabilization criteria [algebraic form and linear matrix inequality (LMI) form] are established. There are two groups of adjustable parameters included in the delayed state feedback control, which can be selected flexibly to achieve the desired global asymptotic stabilization or global Mittag–Leffler stabilization. Since the existing LMI-based stability analysis techniques for fractional-order systems are not applicable to delayed fractional-order nonlinear systems, a fractional-order differential inequality is established to overcome this difficulty. Based on the coupling state feedback control, some LMI stabilization criteria are developed for the first time with the help of the newly established fractional-order differential inequality. The obtained LMI results provide new insights into the research of delayed fractional-order nonlinear systems. Finally, three numerical examples are presented to illustrate the effectiveness of the proposed theoretical results. [ABSTRACT FROM AUTHOR]

This paper explores the possibility of constructing two-terminal mechanical devices (one-ports) which are lossless and adjustable. To be lossless, the device must be passive (i.e., not requiring a power supply) and nondissipative. To be adjustable, a parameter of the device should be freely variable in real time as a control input. For the simplest lossless one-ports, the spring and inerter, the question is whether the stiffness and inertance may be varied freely in a lossless manner. We will show that the typical laws which have been proposed for adjustable springs and inerters are necessarily active, and that it is not straightforward to modify them to achieve losslessness, or indeed, passivity. By means of a physical construction using a lever with moveable fulcrum, we will derive device laws for adjustable springs and inerters which satisfy a formal definition of losslessness. We further provide a construction method which does not require a power supply for physically realizable translational and rotary springs and inerters. The analogous questions for lossless adjustable electrical devices are examined. [ABSTRACT FROM AUTHOR]

The series-capacitor boost converter (SCBC) requires a duty cycle ($D) \ge0.5$ control, otherwise has issues of power switch overstress and inductor currents imbalance. Then, we cannot use the SCBC in wide conversion ratio (CR) applications that require CR < 4. Meanwhile, the $D \ge0.5$ control does not allow $D$ to increase smoothly from 0 during start-up, causing severe inrush inductor currents. As a solution, we propose two control schemes on the capacitor-cross-connected (CCC) boost converter, which is the symmetric version of the SCBC. With the proposed hard-charging control, the CCC converter allows $D < 0.5$ without overstress or imbalance issues, thus extending the CR range and facilitating a soft start-up. In addition, we propose a soft-charging control that enhances the efficiency for 3< CR < 4. We study the output impedance and CR expressions under these two types of controls. Finally, we propose a compact centrosymmetric floorplan that reduces the switching nodes’ ringing, verifying the proposed schemes with a 2.8-to-8.4-V input / 24-V output prototype converter. It exhibits a soft start-up with the proposed control. Under an 8-V input voltage and 1.5-A output current, the peak efficiency of the proposed hard-charging and soft-charging control is 94.7% and 96.3%, respectively. [ABSTRACT FROM AUTHOR]

This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable reference ripple tolerance, thus significantly relaxing the reference settling requirement. To verify the proposed technique, a prototype 10-bit 100-MS/s SAR ADC is fabricated in a 40-nm CMOS process. Equipped with the proposed technique, it only requires a 0.5-pF decoupling capacitor and an on-chip low-power reference buffer consuming 0.26-mW static power. The proposed technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL) and differential non-linearity (DNL) by 15 times. Overall, the prototype ADC achieves an SNDR of 56.3 dB at Nyquist rate while consuming 1.4 mW, including on-chip reference buffers. [ABSTRACT FROM AUTHOR]

In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with ‘memimpedace’ elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at $100^{o}C$ across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance’s quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses). [ABSTRACT FROM AUTHOR]

A charge amplifier incorporates digital circuits as an alternative to the classic analog amplifier to achieve a high open-loop gain to maintain a consistent closed-loop gain over input capacitance variations. The digital-assisted charge amplifier employs a comparator, digital control logic, differential charge pump, current sources, common-mode feedback, and clock generator. A detailed analysis studies the amplifier stability and trade-off between ripple voltage and settling speed. A novel two-step reset scheme and tri-state charge pump minimize the output offset due to ripple residues. Fabricated in a 180-nm CMOS process, the digital-assisted amplifier achieves an open-loop gain of 101 dB, closed-loop gain of $15.0~\mu \text{V}$ /e-, input-referred noise of 221 $\text{e}^{-}$ rms, and output swing of 3 V while consuming 2.19 mW. The amplifier also demonstrates the ability to amplify a dynamic input current using a custom opto-electronic test setup. The amplifier maintains a consistent closed-loop gain across parasitic input capacitance from 6 pF to 94 pF. [ABSTRACT FROM AUTHOR]

This paper presents a 5-GS/s 12-way 10-b time-interleaved successive approximation register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along the multiple channels are utilized to mitigate interchannel bandwidth and timing mismatches. A digitally assisted calibration is introduced to remove the interchannel offset, gain, and timing mismatch. The T-type bootstrapped sampling switches minimize the interchannel crosstalk among top-plate sampling SAR channels and the signal-dependent leakage current during SAR conversion cycles. The power efficiency of this ADC is significantly improved by many design techniques. The merged capacitor switching algorithm leads to high switching efficiency and a smaller area. The modified reference voltage scheme optimizes input common-mode voltage of the comparators. The optimal subradix-2 capacitive DAC results in low-power reference buffers and higher conversion speed. This ADC achieves 49-dB SNR, 52-dB THD, and 42-dB SNDR up to Nyquist frequency at 5 GS/s, consumes 76 mW from 1 V supply, and occupies 0.57 mm $^{{ {2}}}$ in 28 nm CMOS technology. The implemented architecture also demonstrates high scalability to advanced CMOS technology nodes and has even higher power efficiency potential. [ABSTRACT FROM AUTHOR]

Noise analysis of the ramp reference voltage and its projection at the output of a conventional single-slope ramp analog-to-digital converter (ADC) is presented. This paper gives insight on the reference voltage noise origins during the continuous-time ramping phase of column-parallel CMOS image sensor ADCs, as well as its effect on the final ADC output noise. Theoretical modeling of an occurring random walk noise on continuous-time-based ramp references is presented first. Noise on the ramp does not directly add to the output noise of the ADC, but it is modulated and projected subject to given ramp rise time conditions. Test measurements show that the signal-dependent output noise is consistent with the rate of noise increase by the proposed random walk noise model. [ABSTRACT FROM AUTHOR]

This paper presents a nonlinear state-space model (SSM) for a low power 28-nm complementary metal–oxide–semiconductor switched-capacitor digital-to-analog converter. The proposed model utilizes current–voltage (I-V) input and output relationships for passive devices, which are described by a set of first-order differential equations. The proposed model significantly increases accuracy when compared with the state-of-the-art models. The SSM simulation results have been verified using SpectreRF transistor-level simulations and validated by on-chip measurements. [ABSTRACT FROM AUTHOR]

A low-noise high-linearity switched capacitor interface implemented in a 0.35 \mu \text m 3.3 V/15 V CMOS process is presented in this paper for a ±50g capacitive micro-accelerometer. The sensing element is enclosed in an optimized closed loop with proportional-integral compensation, improving the linearity significantly. In order to suppress the flicker noise of the front-end at the lowest cost, a novel switched capacitor PI controller combined with a charge sensitive amplifier using correlated double sampling is proposed. Furthermore, a detailed noise analysis of the proposed CSA-PIC combination with a final goal of achieving 120 dB dynamic range is also presented. The theoretical analysis is verified by the consistency between calculated results and PNoise simulation results. The sensor output can be read in analogue domain from a sample-and-hold buffer or in digital domain from a back-end 2–1 MASH $\Sigma$ - \Delta$ ADC. The fabricated prototype circuit measures 11.75 mm2 and operates under 15-V and 3.3-V supplies at a sampling clock of 111 KHz. Meanwhile, a sensitivity of 99.7 mV/g is achieved with a dynamic range of 112.4 dB over a 200-Hz bandwidth. The accelerometer has a DC nonlinearity of 0.623 in the range of −18 g to +14 g measured in self-test mode and the bias instability is 200 \mu \text {g} . [ABSTRACT FROM AUTHOR]

This paper studies the passive network synthesis problem of biquadratic impedances as five-element bridge networks. By investigating the realizability conditions of the configurations that can cover all the possible cases, a necessary and sufficient condition is obtained for biquadratic impedances to be realizable as two-reactive five-element bridge networks. Based on the types of the two reactive elements, the discussion is divided into two parts, and a canonical form for biquadratic impedances is utilized to simplify and combine the conditions. Moreover, the realizability result for the biquadratic impedance is extended to the general five-element bridge networks. Some numerical examples are presented for illustration. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel level shifter circuit converting subthreshold signal levels to super-threshold signal levels at high-speed using ultra low-power and a small silicon area, making it well-suited for low-power applications such as wireless sensor networks and implantable medical devices. The proposed circuit introduces a new voltage level shifter topology employing a level-shifting capacitor contributing to increase the range of conversion voltages, while significantly reducing the conversion delay. Such a level-shifting capacitor is quickly charged, whenever the input signal detects a low-to-high transition, in order to boost internal voltage nodes, and quickly reach a high output voltage level. The proposed circuit achieves a shorter propagation delay and a smaller silicon area for a given operating frequency and power consumption compared to other circuit solutions. Measurement results are presented for the proposed circuit fabricated in a 0.18- \mu \text m TSMC technology. The proposed circuit can convert a wide range of the input voltages from 330 mV to 1.8 V, and operate over a frequency range of 100 Hz to 100 MHz. It has a propagation delay of 29 ns and a power consumption of 61.5 nW for input signals 0.4 V, at a frequency of 500-kHz, outperforming previous designs. [ABSTRACT FROM AUTHOR]

In this paper, we propose a method to broaden a tuning range of a CMOS LC-tank oscillator without sacrificing its area. The extra tuning range is achieved by forcing a strongly coupled transformer-based tank into a common-mode resonance at a much higher frequency than in its main differential-mode oscillation. The oscillator employs separate active circuits to excite each mode but it shares the same tank, which largely dominates the core area but is on par with similar single-core designs. The tank is forced in common-mode oscillation by two injection locked Colpitts oscillators at the transformer’s primary winding, while a two-port structure provides differential-mode oscillation. An analysis is also presented to compare the phase noise performance of the dual-core oscillator in common-mode and differential-mode excitations. A prototype implemented in digital 40-nm CMOS verifies the dual-mode oscillation and occupies only 0.12 mm2 and measures 56% tuning range. [ABSTRACT FROM AUTHOR]

This paper presents the design and implementation of a 10-bit ultra-low voltage energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). The proposed first 2-bit guess (F2G) scheme reduces the DAC switching energy by 90% and improves the DNL and INL by \sqrt 3 /2 in theory compared with the conventional approach. By employing majority-vote comparison at the conversions of LSBs, the noise requirement of comparator can be relaxed by half. With the segmented and bundled routing, the parasitic capacitors of bottom-plates of DAC array are reduced to improve power efficiency and speed. Implemented in 90-nm CMOS technology, the test chip occupied a core area of 0.03 mm2. The prototype consumes 67.3 nW at 150 kS/s from a single 0.3 V supply voltage and achieves an ENOB of 8.85 bits and an SFDR of 70.7 dB at Nyquist input, respectively. The resultant Walden’s FoM and Schreier’s FoM are 0.97 fJ/conv.-step and 175.5 dB, respectively. [ABSTRACT FROM AUTHOR]

A constant on time variable frequency one-cycle control technique (CVFOCC) for switched-capacitor (SC) converters is presented in this paper. It is designed to accomplish the continuous variable conversion ratio and fast dynamical response to reject the external disturbance. A proper regulation can be obtained by controlling the related “off time” of a transistor with the constant “on time” which is less than the time constant $\tau $ of the charge loop. A unique large-signal dynamic capacitor ampere-second balance (CASB) model for SC converters is applied in this research study. It is implemented to instantaneously estimate transient values of the equivalent circuits. The proposed modeling method and analysis have been verified by comparing the modeling expressions with simulation and experiment results for different input voltages, load currents and switching frequencies. The simulation and experiment results show that the external disturbance of a single-stage SC converter could be immediately rejected by the proposed control method. The good line and load regulation are demonstrated. The proposed control method is stable and global. It can work in a wide operation range with a simple control circuit for general SC converters. [ABSTRACT FROM AUTHOR]

This paper presents a piezoelectric energy harvesting circuit, which integrates a Synchronized Switch Harvesting on Inductor (SSHI) circuit and an active rectifier. The major design challenge of the SSHI method is flipping the capacitor voltage at optimal times. The proposed SSHI circuit inserts an active diode on each resonant loop, which ensures flipping of the capacitor voltage at optimal times and eliminates the need to tune the switching time. The diodes of the SSHI circuit are also used as a rectifier to further simplify the controller. The key advantage of the proposed circuit is a simple controller, which leads to low power dissipation of the proposed circuit to result in high efficiency. The proposed circuit is self-powered and capable of starting even when the battery is completely drained. The circuit was fabricated in BiCMOS 0.25~\mu \text m technology with a die size of 0.98 \times 0.76 mm2. Measured results indicate that the proposed circuit increases the amount of power harvested from a piezoelectric cantilever by 2.1 times when compared with a full bridge (FB) rectifier and achieves a power conversion efficiency of 85%. The proposed circuit dissipates about 24~\mu \text {W} while the controller alone only 1.5~\mu \text {W}$ . [ABSTRACT FROM AUTHOR]

Nonvolatile processor (NVP) attracts more and more attentions for its immunity to power loss in energy harvesting scenarios. The overall performance of an NVP is determined by its sleep and wake-up speeds, which refer to how fast the NVP can turn itself off and on when a sudden power failure occurs. To the best of our knowledge, this paper is the first work to improve the system-level sleep/wake-up speed of an energy harvesting NVP. A hybrid CMOS/ferroelectric nonvolatile flip-flop (nvFF) and a high-speed voltage detector are designed and integrated in the proposed NVP to jointly minimize its sleep and wake-up time. Measurement results demonstrate 46~\mu \text s wake-up time and 14~\mu \text s sleep time, which is up to 18 and 24 times speedup over existing works. This approach not only improves the robustness of the NVP to power fluctuations but also brings significant advantages for better utilization of harvested energy. [ABSTRACT FROM AUTHOR]

In this paper, conditions for checking the realizability of fractional-order impedance functions by passive networks composed of a fractional element (either a fractional capacitor or a fractional inductor) and some RLC components are derived. To this end, at first the newly obtained conditions for realizability of fractional-order impedance functions by a passive network composed of a fractional capacitor and some RLC components are extended to include the case that the polynomials involving in the impedance function can have roots on the imaginary axis. Then, the necessary and sufficient conditions are found on a fractional-order impedance function to be realized by a passive network composed of a fractional element and some RLC components. Furthermore, a procedure for finding the realization in the realizable cases is proposed. Finally, the realizability conditions for a special class of fractional-order impedance functions are simplified. [ABSTRACT FROM AUTHOR]

This paper proposes a linearity calibration algorithm of a capacitive digital-to-analog converter (CDAC) for successive approximation register (SAR) analog-to-digital converters (ADCs) based on a normalized-full-scale of the DAC. Since the capacitor weight errors are represented as the difference between the real and ideal weights with respect to the normalized-full-scale, the calibrated digital representation of CDAC does not have gain error. A model of a 14-bit-format SAR ADC with a segmented CDAC by a bridge capacitor is simulated to demonstrate the performance of the proposed calibration algorithm. The effective number of bits (ENOB) and spurious-free dynamic range (SFDR) of the 14-bit-format ADC model are improved to 13.2 bits and 94.0 dB from 8.4 bits and 54.8 dB, respectively, at a standard deviation of a unit capacitor of 2%. The gain-error-free characteristic of the proposed linearity calibration algorithm is verified with a 2-channel time-interleaved (TI) SAR ADC model. [ABSTRACT FROM PUBLISHER]

Passive mixers have become an essential component of SAW-less communication receivers in the last few years, this has encouraged many researchers to study their impedance characteristics. When observed from the input radio frequency (RF) port of the passive mixer, the impedance exhibits bandpass filtering characteristics centered around the frequency of the local oscillator (LO) signal. The theory of baseband impedance up-conversion is widely accepted in the analysis of passive mixer circuits as well as in describing the origin of this bandpass impedance characteristics. In this paper, we revisit this theory and show that it is not always accurate since it does not account for switching transients. We begin our work by showing that the most commonly used single-balanced mixer is not the right choice for a half-circuit used in analyzing the input impedance of a fully-balanced passive mixer. We propose an alternative half-circuit, and proceed with a novel analysis that accounts for switching transients. This switching-aware analysis allows capturing the switched-capacitor behavior of the passive mixer. We then derive closed-form equations for the mixer impedance using purely-capacitive loads as well as resistive-capacitive (RC) loads. We also discuss the impact of finite LO rise and fall times on the mixer impedance. Simulation results of quadrature passive mixers using ideal and MOSFET switches show very close match with the proposed theoretical analysis. [ABSTRACT FROM PUBLISHER]

This paper presents an analytical model for power harvester circuits used in Ultra-low power applications. Assuming that the MOS devices of the circuit fully operate in the Sub-threshold regime in both forward and reverse regions, closed-form equations for important properties of the rectifier circuit such as output voltage, efficiency and input resistance are derived. The model includes the effect of the compensation voltage on the circuit behavior. There is a good agreement between the simulation results and the model. In addition, the contour plots needed to simultaneously optimize the matching network and the rectifier circuit are derived by the resulting equations. A 50-Stage rectifier was fabricated in a 180-nm standard CMOS Process. The proposed model is verified with the measurement results. The model has a maximum error of 10% in comparison with the circuit simulation, and a maximum error of 12% with the measured values. [ABSTRACT FROM PUBLISHER]

High step-up conversion is an indispensable feature for the power processing of low voltage renewable sources in grid-connected systems. Motivated by this necessity, this paper presents a study on non-isolated dc-dc converters based on the conventional Boost converter that can provide such feature with high efficiency. By the topological variation and gain cell concepts, it is demonstrated that these converters can be treated as a unique generalized converter, called Boost Converter with Gain Cell (BCGC). The operating principle, the key waveforms and the components stresses of the BGCG are analyzed for the continuous-conduction mode, independently of the employed gain cell. A methodology to create the gain cells is developed from the combination of coupled inductors and voltage multiplier techniques. In order to verify the realized analysis, a 150 W prototype concerning to the proposed generalized converter and able to operate with several different gain cells is developed for the comparison between theoretical and experimental static gain results. [ABSTRACT FROM PUBLISHER]

This paper presents an efficient numerical methodology to obtain the frequency response of switched-capacitor filters based on the circuits' differential equations. This methodology uses a non-hierarchical approach in which the non-ideal effects of the transistors (in the switches and in the amplifier) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. The accuracy is demonstrated by comparing the results obtained using the proposed methodology with those obtained using transient electrical simulation results for three different SC circuits: a first order SC passive filter, a second order SC lowpass filter, and a second order SC bandpass filter, showing that the results are in good agreement with the more time consuming electrical simulation of the circuits. [ABSTRACT FROM PUBLISHER]

This paper presents a new family of conditioning circuits used in electrostatic kinetic energy harvesters (e-KEHs), generalizing a previously reported conditioning circuit known as the Bennet's doubler. The proposed topology implements a conditioning scheme described by a rectangular charge-voltage cycle (QV-cycle) of tunable aspect ratio. These circuits show an exponential increase of the converted energy over operation time if studied in the sole electrical domain. The QV-cycle's aspect ratio can be set to values that were previously inaccessible with other exponential conditioning circuits. After a brief intuitive presentation of the new topology, its operation is rigorously analyzed and its dynamics are quantitatively derived in the electrical domain. In particular, the aspect ratio of the rectangular QV-cycle describing the biasing scheme of the transducer is expressed as a function of the circuit's parameters. Practical considerations about the use of the reported conditioning circuits in actual e-KEHs are also presented. These include a discussion on the applications of the proposed conditioning, a description of the effects of electrical nonidealities, and a proposition of an energy extracting interface. [ABSTRACT FROM PUBLISHER]

This paper presents a two-step prediction method for the design of low-power column-parallel analog-to-digital converters (ADC) in CMOS image sensors. The proposed prediction method takes advantage of the spatial likelihood of natural scenes, which shows strong correlations between neighboring pixels in the image. Based on this property, the proposed method predicts the MSBs of the selected pixel using quantization results of the neighboring pixels in the previous row, which enables a significant power reduction of the A/D conversions. The simulation results show that up to 20∼30% power saving can be achieved for most natural scenes. A 384 \times 256-pixel prototype chip was fabricated using a 0.35 \mu\text{m} CMOS technology with a pixel footprint of 15\ \mu\text{m} \times 15\ \mu\text{m}$. The fill factor is 49%. 10-bit successive approximation register (SAR) ADCs are used in the column-parallel ADC array. [ABSTRACT FROM AUTHOR]

This paper presents a low-voltage and power-efficient 10 bit successive-approximation register (SAR) analog-to-digital converter (ADC). The input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive digital-to-analog convertor (DAC) by 91% compared with the conventional approach. By utilizing the comparator as a voltage-to-time converter (VTC) with a time-domain quantizer, the implemented early-late (E/L) detection circuit, the input range is detected to eliminate the unnecessary DAC switching power efficiently. A prototype ADC chip is fabricated in 90 nm CMOS technology with an active area of 0.038 mm2. At 0.35-to-0.5 V supply voltage and 0.3-to-2 MS/s sampling rate with a Nyquist input, the ADC achieves a signal-to-noise-plus-distortion ratio (SNDR) of 55.5 dB to 56.3 dB and a corresponding effective number of bits (ENOB) of 8.92 bit to 9.06 bit respectively with a power consumption of 0.3~\mu \text W to 2.5~\mu \text W and a resulting figure of merit (FoM) from 1.94 fJ/conversion-step to 2.32 fJ/conversion-step. [ABSTRACT FROM PUBLISHER]

Mixed-signal current-mode control (MCMC) implementation has been gaining popularity, because of the tuning flexibility using the digital voltage controller Gc(z) along with the fast-changing analog current controller. Generally a continuous-time frequency-domain approach is adopted for the design of Gc(z); however, this method often fails to capture sub-harmonic, more generally the fast-scale instability due to finite discretization effects. This paper derives approximate discrete-time models and proposes a unified framework to derive closed-form stability conditions and discrete-time small-signal models of a synchronous buck converter under MCMC. Considering the effects due to finite output-voltage sampling and the effective series resistance (ESR) of the output capacitor, the stability boundary in MCMC is found to be significantly restricted compared to its analog counterpart. Further, design methods are proposed to enhance stability boundary with improved transient performance by tuning the controller directly in the digital domain. A buck converter prototype is made, and the MCMC technique is realized using an FPGA device. Analytical predictions are verified experimentally. [ABSTRACT FROM PUBLISHER]

This paper presents a micropower audio delta-sigma (\Delta\Sigma) modulator for mobile applications. This work employs power-efficient integrators based on the dynamic bias inverter, which consists of a cascode inverter, a floating current source and two offset-storage capacitors. The quiescent current of the inverter is copied from the floating current via offset-storage capacitors and the speed limitation caused by the cascode transistors in the inverter is resolved by using active parasitic compensation. This maximizes both {g}_{m}/{I}_{D} ratio and slew rate of the inverter-based integrator, while compensating process, voltage, and temperature (PVT) variations. To verify the effectiveness of the proposed technique, a single-bit third-order \Delta\Sigma modulator is implemented in a 0.18 \mu\text{m} CMOS technology. The prototype modulator achieves 97.7 dB SNDR, 98.6 dB SNR, and 100.5 dB DR in a 20-kHz signal bandwidth, while consuming only 300-\mu\text{W}$ from a 1.8 V supply. This corresponds to a state-of-the-art Schreier's FoM of 178.7 dB. The results are fully verified under variable supplies and temperatures. [ABSTRACT FROM PUBLISHER]

A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and the matching requirement for capacitors in SAR ADCs. The switching energy (including switching energy and reset energy), total capacitance and static performance (INL & DNL) of the proposed scheme are reduced by 98.08%, 75%, and 75%, respectively, compared with the conventional architecture. Based on analysis of the non-linear errors caused by comparator input parasitic capacitance, an improved comparator with push-pull pre-amplifier and output offset storage (OOS) strategy is proposed to diminish non-linearity in the input parasitic capacitance. The offset cancellation signal for the comparator can be generated by asynchronous timing automatically, without any extra clock. Additionally, an SFDR enhancement bootstrap switch is proposed to eliminate the distortion induced by parasitic capacitance and threshold voltage that results in insufficient precision for medium-speed 12-bit ADCs. The proposed ADC was fabricated in a 0.18 \mu\textm 1P6M CMOS process, and the measured results show that the ADC achieves an SNDR of 66.9 dB and an SFDR of 75.8 dB with a 10 MS/s sampling rate and consumes 0.82 mW, resulting in a figure of merit (FOM) of 44.2 fJ/conversion-step. The peak DNL error is +0.36/−0.33 LSB, and the peak INL error is +0.55 LSB/−0.6 LSB. The ADC core occupies an active area of only 630\ \mu\textm\! \times\! 570\ \mu\textm^2. [ABSTRACT FROM PUBLISHER]

This paper demonstrates an asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) architecture with an embedded passive gain technique for low-power and high-speed operation. The proposed passive gain technique relaxes the noise requirement of the comparator and reuses the existing capacitor DAC in SAR for minimal overhead. An additional time-out scheme is adopted to advance the SAR conversion whenever the comparator takes longer time to resolve, which improves the overall conversion rate. To prove the concept, an 11-bit ADC prototype was fabricated in 65 nm CMOS technology. The prototype measured a peak effective number of bits (ENOB) of 10.2 and a spurious-free dynamic range (SFDR) of 75.2 dB at a 95-MS/s sampling rate with 1.36-mW power consumption from a 1.1 V supply. The measured static differential nonlinearity (DNL) and integral nonlinearity (INL) were less than ± 0.84 LSB with a differential input swing of 1.6 \mathbfV\boldsymbol{pp}. [ABSTRACT FROM PUBLISHER]

A frequently occurring subcircuit consists of a loop of a resistor (R), a field-effect transistor (FET), and a capacitor (C). The FET acts as a switch, controlled at its gate terminal by a clock voltage. There may be many such identical circuits connected in parallel, each driven by a different phase of the clock. This subcircuit may be acting as a sample-and-hold (S/H), as a passive mixer (P-M), or as a bandpass filter or bandpass impedance. In this work, we will present a useful analysis that leads to a simple signal flow graph (SFG), which captures the FET-R-C circuit's action completely across a wide range of design parameters. The SFG dissects the circuit into three filtering functions and ideal sampling. This greatly simplifies analysis of frequency response, noise, input impedance, and conversion gain, and leads to guidelines for optimum design. The analysis is extended to multi-path realizations common in RF applications. Part I of this paper focuses on the analyses of a single-path FET-R-C circuit's signal transfer characteristics. Part II extends these analyses to multi-path FET-R-C circuit configurations, which is followed by the noise and driving-point impedance analyses. [ABSTRACT FROM AUTHOR]

This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a high-speed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step. [ABSTRACT FROM AUTHOR]

This paper introduces a new effective single-Miller capacitor compensation topology for three-stage amplifiers with very large capacitive loads, realized through an active-feedback capacitor together with an inner half-feedforward stage. Moreover, an optimized design strategy which profitably exploits the two left half-plane zeros is presented. To improve the amplifier large signal transient response, the topology also includes an external feedforward path, that only marginally affects the frequency compensation, and a novel slew-rate enhancer section. To validate the solutions presented, a three-stage OTA driving a 10-nF load has been designed and implemented in a standard 0.35-\mu\textm CMOS technology. The amplifier occupies less than 0.003-mm2 of die area, provides 2.7-MHz gain-bandwidth product and 0.55-V/\mu\texts average slew-rate, while consuming only 25-\mu\textA quiescent current. [ABSTRACT FROM AUTHOR]

A high-precision capacitance-to-digital converter (CDC) that is configurable to interface with unipolar or push-pull-type capacitive sensors is presented in this paper. In the conventional switched-capacitor CDC, it is well known that clock feedthroughs and charge injections from top-plate switches can be eliminated by a bottom-plate sampling scheme. However, those charge errors from the bottom-plate switches depend on the digital output and the varying value of the sensing capacitor itself. They will thus affect the overall CDC linearity. When the varying range of the sensing capacitor is wide, the nonlinearity becomes more pronounced. This paper proposes new switching and calibration schemes to reduce these non-idealities. A prototype of a second order CDC employing the proposed techniques in a 0.18 μm CMOS process achieves a 53.2 aF RMS resolution with a 1 ms conversion time. The proposed calibration technique improves the linearity of the CDC from 9.3 bits to 12.3 bits and from 10.1 bits to 13.3 bits in the unipolar and push-pull-type sensing modes, respectively, with a sensing capacitance varying from 0.5 to 3.5 pF. The CDC is also demonstrated with a real-life pressure sensor. [ABSTRACT FROM AUTHOR]

This paper investigates the simplified realization problem of a special class of positive-real admittances similar to biquadratic functions but with an extra pole at the origin, which is widely used in the analysis of suspension systems. The results in this paper are motivated by passive mechanical control with the inerter. The concept of strictly lower complexity is first defined, whose indices in this paper are the total number of elements, the number of resistors (dampers), and the number of capacitors (inerters). We then derive a necessary and sufficient condition for this class of admittance to be realized by the networks that are of strictly lower complexity than the canonical realization by the Foster Preamble method. To solve this problem, it is shown that it suffices to consider the following: 1) networks with at most four elements, 2) irreducible five-element resistor-inductor (RL) networks, and 3) irreducible five-element resisitor-inductor-capacitor (RLC) networks. Other cases are shown to be impossible. By finding their corresponding network configurations through a series of constraints and deriving the corresponding realizability conditions, the final condition can be obtained. Finally, the U-V plane and numerical examples are provided to illustrate the theoretical results. [ABSTRACT FROM PUBLISHER]

This work presents a 25 MHz adaptive on/off-time-controlled three-level buck converter with a fast reference tracking speed and high light load efficiency. The self-balancing scheme of the flying capacitor voltage is revised and extended for a broad conversion ratio range from 0.17 to 0.833. To reduce the error of the self-balancing scheme when applied to a high frequency three-level buck converter with an on-chip flying capacitor, a real-time calibration loop on the flying capacitor voltage is introduced, effectively reducing the balancing error from 340 mV to 20 mV. A turning-point output voltage prediction for the three-level buck converter is presented to achieve near-optimal reference tracking with a fast tracking speed and negligible output voltage undershoot or overshoot. The up- and down-tracking takes 81 ns and 72 ns, respectively, for a 1-V step with an inductor of 47 nH and an output capacitor of 47 nF. The three-level converter achieves a precise discontinuous conduction mode (DCM) operation with an adaptive switching frequency at light load by means of a feedback loop-based method. An approximately 28.2% increment in efficiency is achieved with a load of 10 mA. The three-level buck converter has a peak efficiency of 92.8% and an over 85% efficiency in most of the operation regions. [ABSTRACT FROM AUTHOR]

We introduce a circuit topology based on a simple triple-ladder circuit realized with lumped reactive components that provides a sixth order degenerate band-edge (6DBE). The 6DBE is a special kind of sixth-order exceptional point of degeneracy in a lossless and gainless periodic ladder. This degeneracy provides a very flat band edge in the phase-frequency dispersion diagram. The proposed topology exhibits unique structured resonance features associated with a high loaded Q-factor. We investigate the Floquet-Bloch modes in an infinite-length periodic triple-ladder and their dispersion relation using the S parameter formalism. We also provide the approximate analytic expressions of the eigenmodes and dispersion relation around the degenerate point based on the Puiseux series expansion. We investigate the filtering characteristics of a finite-length structure terminated with loads to highlight the special properties of the 6DBE compared to ladders with regular band edge (RBE) and fourth order degenerate band edge (DBE). The circuit framework introduced here with a 6DBE can be exploited in designing novel high Q-factor oscillators, filters, sensors, and pulse shaping networks. [ABSTRACT FROM AUTHOR]

The object of this paper is to give a complete treatment of the realizability of positive-real biquadratic impedance functions by six-element series-parallel networks comprising resistors, capacitors, and inductors. This question was studied but not fully resolved in the classical electrical circuit literature. Renewed interest in this question arises in the synthesis of passive mechanical impedances. Recent work by the authors has introduced the concept of a regular positive-real functions. It was shown that five-element networks are capable of realizing all regular and some (but not all) nonregular biquadratic positive-real functions. Accordingly, the focus of this paper is on the realizability of nonregular biquadratics. It will be shown that the only six-element series-parallel networks which are capable of realizing nonregular biquadratic impedances are those with three reactive elements or four reactive elements. We identify a set of networks that can realize all the nonregular biquadratic functions for each of the two cases. The realizability conditions for the networks are expressed in terms of a canonical form for biquadratics. The nonregular realizable region for each of the networks is explicitly characterized. [ABSTRACT FROM PUBLISHER]

This paper presents a very low-complexity all-digital IR-UWB transmitter that can generate pulses in the band 0–5 GHz, requiring a silicon area lower than a PAD for signal I/O. The transmitter, suited to non-standardized low data rate applications, is prototyped in a 130 nm RFCMOS technology and includes analog control signals for frequency and bandwidth tuning. Center frequency is linearly selected with voltage supply, 0.5 V for the range 0–960 MHz and 1.1 V supply for the higher 3.1–5 GHz range. The architecture is based on the same delay cell for both baseband and radio frequency signal generation and pulses fractional bandwidth remains constant when voltage supply and control voltages scale. At 420 MHz center frequency, the transmitter achieves 7 pJ/pulse, and for 4 GHz center frequency pulses, it achieves 32 pJ/pulse active energy consumption. The OOK/S-OOK transmitter occupies an area of 0.004 mm^2. For ASK modulation, the system includes a separate on-chip capacitor bank connected to the output of the transmitter for an overall size of 0.024 mm^2. For pulse rates below 100 kpps, the generated pulses meet the FCC indoor mask with an off-chip DC block capacitor. The paper also presents over-the-air measurements using a planar monopole antenna operating in the 1.5–3.7 GHz frequency range. [ABSTRACT FROM AUTHOR]

This paper presents a mutual capacitive touch screen panel (TSP) readout IC (ROIC) with a differential continuous-mode parallel operation architecture (DCPA). The proposed architecture achieves a high product of signal-to-noise ratio (SNR) and frame rate, which is a requirement of ROIC for large-sized TSP. DCPA is accomplished by using the proposed differential sensing method with a parallel architecture in a continuous-mode. This architecture is implemented using a continuous-type transmitter for parallel signaling and a differential-architecture receiver. A continuous-type differential charge amplifier removes the common-mode noise component, and reduces the self-noise by the band-pass filtering effect of the continuous-mode charge amplifier. In addition, the differential parallel architecture cancels the timing skew problem caused by the continuous-mode parallel operation and effectively enhances the power spectrum density of the signal. The proposed ROIC was fabricated using a 0.18-$\mu$m CMOS process and occupied an active area of 1.25 \text{mm}^{2}. The proposed system achieved a 72 dB SNR and 240 Hz frame rate with a 32 channel TX by 10 channel RX mutual capacitive TSP. Moreover, the proposed differential-parallel architecture demonstrated higher immunity to lamp noise and display noise. The proposed system consumed 42.5 mW with a 3.3-V supply. [ABSTRACT FROM PUBLISHER]

Noise shaping digital quantizers, most commonly digital delta-sigma $(\Delta\Sigma)$ modulators, are used in fractional- $N$ phase-locked loops (PLLs) to enable fractional frequency tuning. Unfortunately, their quantization noise is subjected to nonlinear distortion because of the PLL's inevitable non-ideal analog circuit behavior, which induces spurious tones in the PLL's phase error. Successive requantizers have been proposed as $\Delta\Sigma$ modulator replacements with the advantage that they reduce the power of these spurious tones. However, the quantization noise from previously published successive requantizers is only first-order highpass shaped, so it usually causes more PLL phase noise than that from the second-order and third-order $\Delta\Sigma$ modulators commonly used in PLLs. This paper presents second-order and third-order successive requantizers to address this limitation. Additionally, successive requantizer design options are presented that result in either lower-power spurious tones or lower phase noise compared to $\Delta\Sigma$ modulators when used in PLLs. [ABSTRACT FROM PUBLISHER]

This paper employs a time-variant model to determine the exact small-signal loop transmission of second-order charge-pump phased-locked loops. The model predicts that a loop bandwidth of close to half the input frequency can be achieved. The large-signal behavior is also analyzed and two modes of oscillation are identified. The results are confirmed by means of circuit simulations. [ABSTRACT FROM PUBLISHER]

Proposed in this paper is a general parasitic-compatible LCR matching method suitable for $N$-path filter. Analysis of a conventional $L$-type matching is extended to accommodate the case of the $N$- path filter, where the different impedances of the band limited input matching network at multiple local oscillation (LO) harmonic frequencies have to be taken into consideration. Compared to the ideally wideband transformer matching technique, the proposed LCR method has advantages of smaller size and better harmonic folding rejection ratio, while keeping the same properties, such as impedance matching, in-band voltage gain, noise figure and ultimate rejection. Based on the derived equations, the procedure to determine the values of the matching components for given rejection specs has been described using design examples. [ABSTRACT FROM PUBLISHER]

A new approach to augment existing noise models in a relaxation oscillator by including noise spikes during state change, an important aspect hitherto not covered in existing noise models, is proposed. Such noise spike is due to regeneration at the jump and this paper attempts to offer an explanation by viewing state change as a physical phase change in a thermodynamic system, which is also due to regeneration. The connection is established by viewing the relaxation oscillator as a combination of bistable circuit (exhibits metastablility) and a timing capacitor. Similarly the thermodynamic system exhibits physical phase change (metastability). Formula is derived to predict the “magnitude” of the noise spike, as a function of regeneration parameter, and hence design parameter such as gm, R, {I}_{0}. Simulations (Eldo) on circuits and simulations (Metropolis) on thermodynamic system as well as measurements on circuits fabricated in 0.13 \mu$m CMOS technology are consistent with theory. [ABSTRACT FROM PUBLISHER]

In this paper, a printed audio amplifier, which is a new application for organic electronics, is suggested. The amplifier consists of several fully-printed bendable components including: a loudspeaker, organic field effect transistors (OFETs), capacitors, and resistors. All components are fabricated on polyethylene terephthalate (PET) substrate by means of high-throughput printing techniques. A complete self-biased circuit is reported consisting of large multi-finger OFETs with channel length of 20 \mu\textm and total width of 0.475 meter. The amplifier provides a peak voltage gain of 18 dB at 400 Hz, can reproduce sound pressure level of 36–60 dBA over 700 Hz to 12.5 kHz at one meter distance, and has a unity-gain-bandwidth of 17.7 kHz/5.2 kHz when driving 0 nF/ \sim39 nF load at \text{V}_{\mathrm{DD}}=80\ \text{V}, respectively. The impact of bias-stress effects on the amplifier performance is measured to be \sim$ 3 dBA sound loss after 5 hours of continuous operation. The whole circuit is packaged and laminated on a separate PET sheet. In addition, the intrinsic electrical impedance of the printed PVDF-TrFE piezoelectric polymer used in the loudspeaker is characterized, and is modeled by a complex dielectric constant. [ABSTRACT FROM PUBLISHER]

Small metal-oxide-metal (MOM) capacitors are essential to energy-efficient mixed-signal integrated circuit design. However, only few reports discuss their matching properties based on large sets of measured data. In this paper, we report matching properties of femtofarad and sub-femtofarad MOM vertical-field parallel-plate capacitors and lateral-field fringing capacitors. We study the effect of both the finger-length and finger-spacing on the mismatch of lateral-field capacitors. In addition, we compare the matching properties and the area efficiency of vertical-field and lateral-field capacitors. We use direct mismatch measurement technique, and we illustrate its feasibility using experimental measurements and Monte Carlo simulations. The test-chips are fabricated in a 0.18 \mu\textm CMOS process. A large number of test structures is characterized (4800 test structures), which improves the statistical reliability of the extracted mismatch information. Despite conventional wisdom, extensive measurements show that vertical-field and lateral-field MOM capacitors have the same matching properties when the actual capacitor area is considered. Measurements show that the mismatch depends on the capacitor area but not on the spacing; thus, for a given mismatch specification, the lateral-field MOM capacitor can have arbitrarily small capacitance by increasing the spacing between the capacitor fingers, at the expense of increased chip area. [ABSTRACT FROM PUBLISHER]

This paper presents a systematic analysis of integrated 3-level buck converters under both ideal and real conditions as a guidance for designing robust and fast 3-level buck converters. Under ideal conditions, the voltage conversion ratio, the output voltage ripple and, in particular, the system's loop-gain function are derived. Design considerations for real circuitry implementations of an integrated 3-level converter, such as the implementation of the flying capacitor, the impacts of the parasitic capacitors of the flying capacitor and the 4 power switches, and the time mismatch between the 2 duty-cycle signals are thoroughly discussed. Under these conditions, the voltage conversion ratio, the voltage across the flying capacitor and the power efficiency are analyzed and verified with Cadence simulation results. The loop-gain function of an integrated 3-level buck converter with parasitic capacitors and time mismatch is derived with the state-space averaging method. The derived loop-gain functions are verified with time-domain small signal injection simulation and measurement, with a good match between the analytical and experimental results. [ABSTRACT FROM AUTHOR]

This work reveals and analyzes an unfamiliar bifurcation in weakly-coupled inductive wireless power transfer systems (IWPT) employing diode rectifier. This paper firstly provides a local analysis calculating the required RF source power, based on the rectifier ac-dc conversion gain and the two-port analysis of the coupled coils. The local analysis is supported by measured results on silicon. Successively, we demonstrate that if the secondary coil and the diode rectifier have a high quality factor, the rectifier diode varactor can create a turning-point bifurcation in the solution curve of the output dc voltage versus the RF source power. With the bifurcation, the local analysis becomes invalid and a higher source power is required. Bifurcation analysis based on large-signal capacitor modeling and conversion matrix analysis are provided, substantiating the results. The introduced bifurcation analysis is verified by three IWPT examples on PCB. A proposed design with an auxiliary nonlinear varactor is proposed to mitigate the bifurcation with improved performance. [ABSTRACT FROM AUTHOR]