Search

This paper presents an analytical solution to characterize harmonic behavior of digitally controlled H-bridge inverter output with two nonlinear effects: sample delay and dead-time. The effect of sampling frequency in uniformly sampled pulse-width modulation (PWM) is discussed, including spectral analysis and compared with the analog modulated PWM. The effect of dead-time on the rising and falling edge of digitized PWM inverter error output is derived in time-domain. The double Fourier integral solution is used to develop the accurate mathematical expressions for the switched output waveforms. The integral solutions are obtained using Jacobi–Anger expansions. The analytical results are verified with simulation using PSCAD and experimental results. [ABSTRACT FROM AUTHOR]

Linear periodically time-varying (LPTV) circuits are finding increased prominence in reconfigurable transceiver applications. Impedance matching of such circuits to the antenna impedance is essential for fully on-chip receiver topologies. However, deriving the $S_{11}$ of an LPTV circuit is non-trivial in general. Moreover, reflections at harmonic offsets from input frequencies can also be expected due to the time-varying nature of the circuit. This paper utilizes the conversion matrix-based analysis technique to compute the $S_{11}$ of a general LPTV circuit. Furthermore, it is shown that signal reradiation at harmonic shifts from input frequencies is also obtained as a natural consequence of this analysis. Examples related to mixer-first receivers, switched-capacitor receiver front-ends (with reset), and Filtering-by-Aliasing (FA)-based receivers are considered to verify the analysis. Design guidelines are provided to attain optimal $S_{11}$ in a few such scenarios. Explicit analytical expressions are derived for reradiation in ideal $N$ -path mixer-first receivers and FA-based receivers, while guidelines are provided for proper choice of conversion matrix expressions/sizes in case of numerical computation. [ABSTRACT FROM AUTHOR]

In Part I of this paper, we introduce useful analysis that leads to a simple signal flow graph (SFG), which captures the FET-R-C circuit's action completely across a wide range of design parameters. Part I focuses on the analysis of a single-path FET-R-C circuit's signal transfer characteristics and gives us guidelines for sample-and-hold (S/H) and passive sampling mixer (P-M) designs. Part II extends the analysis to multi-path FET-R-C circuit configurations, e.g., a complex $I$-$Q$ passive mixer that is common in RF applications. Then the noise and driving-point impedance analyses are carried out to provide valuable insights of practical S/H and P-M designs. [ABSTRACT FROM AUTHOR]

This paper presents analytical expressions for the class-EM power amplifier, taking into account the fundamental-frequency and harmonic components of output currents in the main and auxiliary circuits. By using the proposed expressions, design values for satisfying not only the class-EM ZVS/ZDVS/ZCS/ZDCS conditions of the main circuit, but also the ZVS condition of the auxiliary circuit can be achieved without applying any tuning process. The analytical predictions agreed with experimental and PSpice-simulation results quantitatively, which showed the validity of analytical expressions given in this paper. [ABSTRACT FROM AUTHOR]

This paper introduces a push-pull class-EM power amplifier for achieving low harmonic contents and high output power. By applying the push-pull configuration of the class-EM power amplifier, the proposed amplifier achieves an extremely lower total harmonic distortion (THD) and about four times higher output power than the conventional single class-EM power amplifier. Design curves of the proposed amplifiers for satisfying the class-EM ZVS/ZDVS/ZCS/ZDCS conditions are given. A design example is shown along with the PSpice-simulation and experimental waveforms for 1-MHz amplifier, considering the MOSFET drain-to-source nonlinear parasitic capacitances, MOSFET switch-on resistances, and equivalent series resistance of the inductors. The waveforms from the PSpice simulation and circuit experiment satisfied all the switching conditions, which has shown the accuracy of the design curves given in this paper and validated the effectiveness of the push-pull class-EM power amplifier. [ABSTRACT FROM PUBLISHER]

This paper analyzes the effect of operational amplifier (OPAMP) input offset on continuous-time (CT) delta-sigma (\Delta\Sigma) modulators with current-mode feedback digital-to-analog converters (DAC). Our analysis shows that the input offset leads to either increased harmonics or increased noise floor of the modulator, depending on whether a DAC shuffling scheme, such as data-weighted averaging (DWA), is applied or not. Analysis and mathematical derivation are given and verified by transistor-level simulations. An input-offset cancellation scheme is proposed and demonstrated by simulation results. [ABSTRACT FROM AUTHOR]

It has been studied that, an N-path switched-capacitor (SC) branch driven by an N-phase non-overlapped local oscillator (LO), is equivalent to a tunable parallel-RLC tank suitable for radio-frequency (RF) filtering. This paper proposes a gain-boosted N-path SC bandpass filter (GB-BPF) with a number of sought features. It is based on a transconductance amplifier (Gm) with an N-path SC branch as its feedback network, offering: 1) double RF filtering at the input and output of the Gm in one step; 2) customized passband gain and bandwidth with input-impedance match; and 3) reduced physical capacitance thanks to the loop gain offered by Gm. All have been examined using a RLC model of the SC branch before applying the linear periodically time-variant (LPTV) analysis to derive the R, L, and C expressions and analytically study the harmonic selectivity, harmonic folding, and noise. The latter reveals that: 1) the noise due to the switches is notched at the output, allowing smaller switches to save the LO power and 2) the noises due to the source resistance and Gm are narrowband at the output, reducing the folded noise during harmonic mixing. To study the influence of circuit non-idealities, an intuitive equivalent circuit model is also proposed and verified. The design example is a four-path 0.5–2-GHz GB-BPF simulated with the 65-nm CMOS. It exhibits >11 dB gain, <2.3 dB NF, and +21-dBm out-of-band IIP3 at 150-MHz offset, while consuming just 7 mW of power. [ABSTRACT FROM PUBLISHER]

This paper considers near-time-optimal setpoint tracking of a second-order oscillator. First, the time-optimal setpoint tracking feedback law is derived by recasting the problem as a regulator problem in the error coordinates with shifted control limits. This result is used to construct a derated approximation of the optimal control. Initially, the control law is derived as a regulator controller. This result is then extended to include setpoint tracking. Global stability is proven for the setpoint tracking controller in the zero-damping case. A scaling method is developed, which allows an efficient implementation of the control laws using a single lookup table. Both the damped and undamped controllers are validated experimentally. [ABSTRACT FROM AUTHOR]

In this paper, a switched load harmonic rejection mixer (HRM) structure with one single mixer core and a pair of switched load resistors is proposed. Different from the traditional three-phase HRM which is widely used in DTV tuners, this HRM performs the harmonic rejection function by vector multiplication rather than superposition. Sharing most of its parts with an ordinary Gilbert mixer, the proposed HRM shows greater simplicity in structure. The single mixer-core structure is also more power efficient than a traditional three-phase HRM. In order to verify the effectiveness of this approach, a proof-of-concept prototype is designed and fabricated in 0.18-\mum RFCMOS technology. Measurements indicate that 38 dB for 3rd and 34.5 dB for 5th harmonic rejection ratio can be achieved. The HRM including a buffer stage consumes a low bias current of 3 mA under 1.8 V supply voltage and has equivalent performance such as CG, NF, and IIP3 to an ordinary Gilbert mixer. With the load switch inactivated, this HRM can be easily transformed into an ordinary Gilbert mixer, which increases its flexibility for different applications. [ABSTRACT FROM AUTHOR]

This paper presents a new Class-E power amplifier (PA) with a \pi-matching output network. The PA is targeted at low output power wireless applications. Analytical formulae are derived to aid the PA design, characterization and optimization. A fully integrated 2.4-GHz PA for short distance communications has been implemented in 0.13 \mu\ m CMOS technology to verify the proposed design method. The measured output power levels vary from -3.2 to 5.7 dBm while achieving maximum overall efficiency of 55%. [ABSTRACT FROM AUTHOR]

The harmonic signal rejection capability and the rejection schemes of polyphase downconverters are discussed. An analysis of a simple model of a polyphase downconverter shows that n-phase converter can reject up to (n-2)th harmonic signal, and that (n-1)th harmonic signal aliases into the desired signal. It means that the harmonic rejection is not exclusive ability of downconverters with large number of phases, and conventional downconverters with fewer phases have the ability. An example is a differential amplifier type downconverter (n=2), which has the ability of even harmonic signal rejection as common-mode signal. In this paper, the common-mode concept is extended to polyphase circuits. It is named “partial common mode,” because it does not have to be common for all node but is common for a part of nodes. The partial common-mode rejection is effective for harmonic rejection. There is the other type of harmonic rejection techniques for polyphase downconverters, i.e., signal weighting-and-summing type. Comparison between the harmonic rejection with weighting-and-summing circuit and that with the common-mode rejection circuit is discussed, too. Due to its simple structure, a 6-phase downconverter with partial common-mode rejection is attractive for practical wideband receivers. [ABSTRACT FROM PUBLISHER]

This paper explores the modulation bandwidth limits for switching amplifiers, by analyzing the fundamental tracking capabilities of two-level switching signals. With this aim, this work synthesizes two-level switching signals by obtaining the distribution of switching events providing both minimum average switching frequency and inband-error-free encoding, targeting to minimize the amplifier switching losses when tracking a generic bandlimited signal. This analysis also provides a framework reference to characterize the deviation from such limit in modulations used in actual amplifiers. [ABSTRACT FROM PUBLISHER]

N-path commutated capacitive networks provide a practical solution to implement highly sought on-chip high-Q filtering applications in which the use of lumped inductors is undesirable due to their significant footprints and low Q-factors. Recently, it has been also revealed that N-path networks can also exhibit other interesting functionalities, such as nonreciprocal phase-shifting and ultra-wideband true time delay, providing a path to miniaturization of various reciprocal and nonreciprocal devices. The analytical treatment of these networks, however, remains challenging, because their operation involves frequency mixing produced by the time modulation. In this article, we present a highly accurate frequency-domain approach for the analysis of N-path networks based on perturbation theory. Our method compares favorably to the state-of-the-art polyphase analysis by being much simpler mathematically, yet providing results essentially indistinguishable from numerical simulations, while offering physical insights into the N-path filter operation. We particularize the solution for the high-Q operation regime and obtain simple closed-form analytical expressions for harmonic transfer functions, scattering parameters and baseband impedance. [ABSTRACT FROM AUTHOR]

This article presents a small-area Bluetooth Low-Energy (BLE) transceiver (TRX) for short-range Internet-of-Things (IoT) applications in 65-nm CMOS. An integrated Radio-Frequency Input-Output (RFIO) circuitry embedded with transmitter/receiver (TX/RX) switch function and on-chip impedance matching is proposed. A hybrid-loop TRX structure based on a wide-bandwidth fractional-N digital phase-locked loop (DPLL) is implemented to achieve the maximum power reduction. A −94dBm receiver sensitivity is achieved with 2.3mW receiver power consumption, while a RF receiving bypass route integration enhances the input power tolerance. The BLE transceiver delivers −6dBm output power while consuming 2.6mW and delivers 0dBm output power while achieving 18.5% maximum TX efficiency. Thanks to the RFIO with harmonic suppression, −56dBc of 2 $^{\mathrm{ nd}}$ -order harmonic distortion (HD2) and −48dBc of 3 $^{\mathrm{ rd}}$ -order harmonic distortion (HD3) suppression are achieved with 0.85mm2 on-chip area. This transceiver satisfied the BLE radio specification without the need for external filters and with low-power consumption, which enables minimum size and long life-time modules. [ABSTRACT FROM AUTHOR]

A systematic approach is presented to analyze the switching pair linearity of low intermediate frequency (IF) up-conversion mixers. The approach explicitly divides the switching pair operation of the mixer into two steps–conversion of the low IF input to the common-source node voltage, in a common-mode domain, and conversion of the common-source node voltage to the output, in a differential-mode domain. In this way, closed-form formulas of the signal gain and third-order intermodulation distortions (IMD3) are derived, demonstrating that the even harmonics (mainly twice local oscillator frequency harmonics) on the common-source node affects the linearity performance significantly. As a result, the mixer linearity is strongly sensitive to the common-source node parasitic reactance. To suppress the even harmonics, we adopt a harmonic-trapping (HT) capacitor and demonstrate 9.1 dB improvement in OIP3 from the fabricated chip prototypes. The analysis approach and HT technique are further validated by well-matched analytical predictions, simulation and measurement results. [ABSTRACT FROM AUTHOR]

We propose a novel low-harmonics low-noise modulation scheme for switched-mode dc–dc converters. The proposed scheme is a hybrid of a randomized modulation scheme, namely, the randomized wrapped-around pulse position modulation scheme (RWAPPM), and a noise-shaper. The RWAPPM mitigates the switching-frequency harmonics in the input current, whereas the noise-shaper mitigates the low-frequency noise therein. We derive an analytical expression for the input current spectrum of the hybrid scheme. We benchmark the hybrid scheme against the conventional pulse width modulation scheme (PWM) and the RWAPPM without the noise-shaper. At 0.5 duty cycle, 3.3-V input voltage, 100-kHz average switching frequency, and with the second-order noise-shaper, the peak spectral power in the input current spectrum of the hybrid scheme is 18.1 dB lower than the PWM. Other randomized and spread-spectrum modulation schemes, in general, have undesirably higher input noise current than that of the PWM. However, the input noise current of the proposed hybrid scheme, obtained at ~73-mA rms (integrated over a 200-kHz bandwidth without an input filter), is comparable with that of the PWM, and is lower by ~16-mA rms compared with that of the RWAPPM without the noise-shaper. We also benchmark the hybrid scheme against other well known randomized and spread-spectrum modulation schemes. We further propose a novel pulse generator structure that embodies the hybrid scheme. We realize a dc–dc converter employing the pulse generator, and measure the converter to verify the derived expression and the characteristics of the hybrid scheme. We also measure the output voltage spectrum, the transient-response, and the operating range of the converter. [ABSTRACT FROM PUBLISHER]

An analysis of a novel single-ended Class-E mode with shunt capacitance and shunt filter with explicit derivation of the idealized optimum voltage and current waveforms and load-network parameters with their verification by frequency domain simulations with 50% duty ratio is presented. The ideal collector voltage and current waveforms demonstrate a possibility of 100% efficiency. The circuit design with transmission lines at 2.14 GHz is discussed and analyzed. In order to reduce the voltage peak factor, the load network parameters can be rearranged to correspond to Class-E/F 3 mode by providing a short-circuit condition at the third harmonic when the second-harmonic tank is connected in series to the shunt filter. Broadband capability of a Class-E mode with shunt filter using reactance compensation technique has been demonstrated by two examples, one with lumped elements and the other with transmission-line elements. The test board of a transmission-line broadband Class-E GaN HEMT power amplifier with shunt filter was measured and high-performance results with the output power of around 41 dBm, average drain efficiency of 68%, and power gain of about 9 dB were achieved across the frequency band from 1.4 to 2.7 GHz. [ABSTRACT FROM PUBLISHER]

We present a novel randomized wrapped-around pulse position modulation (RWAPPM) scheme for digital modulators of dc–dc converters. Unlike the reported modulation schemes that require a varying switching period (thereby resulting in high attenuation or complete elimination of discrete harmonics), the proposed RWAPPM conversely requires only a constant switching period (thereby advantageous in terms of easy realization in hardware), and yet, its discrete harmonics are negligible. We derive an expression for the spectrum of the RWAPPM scheme to analytically obtain the peak spectral power and ripple noise voltage of RWAPPM. This expression further provides insight to the parameters that influence the RWAPPM spectrum. We benchmark the RWAPPM scheme against the ubiquitous conventional pulsewidth modulation scheme and six reported (randomized and frequency modulation) schemes. The RWAPPM scheme features negligible discrete harmonics [\leq -158 dB relative to full scale (dBFS)], and among the modulation schemes, it features the lowest peak spectral power at -26.6 dBFS (before low-pass filtering) and relatively low ripple noise at 2 mVrms (after low-pass filtering) for a 3.6–2.5-V conversion and an effective switching frequency of 120 kHz. We verify the derived expression and attributes of the RWAPPM spectrum by computer simulations and on the basis of experimental measurements on a dc–dc converter. [ABSTRACT FROM PUBLISHER]