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This paper presents a physics-based mathematical model for anionic memristor devices. The model utilizes Poisson- Boltzmann equation to account for temperature effect on device potential at equilibrium and comprehends material effect on device behaviors. A detailed MATLAB based algorithm is developed to clarify and simplify the simulation environment. Moreover, the provided model is used to simulate and predict the effect of oxide thickness, material type, and operating temperatures on the electrical characteristics of the device. The parameters of the proposed model are tuned and validated using experimental data of a fabricated wire based NbO1–x junction. This device is attractive for neuromorphic and computing applications, where multilevel state is desirable. The value of this contribution is to provide a framework intended to simulate anionic memristor devices using correlated mathematical models. In addition, the model can be used to explore device materials and predict its performance. [ABSTRACT FROM PUBLISHER]

This paper presents comprehensive analyses of power-performance tradeoffs in current-mode logic (CML)-based transmitters via equation-based optimization and provides practical design guidelines that can help achieving optimum power efficiency. An accurate equation-based optimization framework was developed for this purpose, and using this framework, key circuit-level design parameters were found with specific design specifications and process technologies. The proposed optimization framework can determine optimum clock edge-rate (i.e., ratio of rise/fall time to clock period) and inter-stage voltage swings that enable significant power savings without affecting performance. Various transmitter design tradeoffs were analyzed for 45-nm, 65-nm, and 90-nm technologies considering data rate, clock edge-rate, and inter-stage swing optimization. Based on the analysis results, we determined the most energy-efficient data rate that can be achieved with acceptable power overhead for each technology node. Also, we identified the optimal clock edge-rate and inter-stage voltage swings in CML gates that achieved minimum transmitter power dissipation. Our analysis results indicate that, when properly optimized, overall transmitter power consumption can be reduced by up to 43% with inter-stage swing optimization with all other design constraints held constant. [ABSTRACT FROM AUTHOR]

In this paper, we explore and describe the electromechanical coupling which results from eKEH conditioning circuits implementing a rectangular QV cycle, including but not limited to the charge pump and Bennet’s doubler circuits. We present numerical and semi-analytical analyses describing the nonlinear relationship between the oscillating mass and the conditioning circuit. We believe this is a poorly understood facet of the device and, as we will portray, affects the potential harvested energy. An approach to determine the frequency shift due to the electromechanical coupling is presented and compared with novel experimental results. We provide some examples of bifurcation behavior and show that the only source of nonlinearity is in the coupling between the electrical and mechanical domains. This work continues from the electrical analysis presented in Part 1, providing a full insight into the complex behavior of the electromechanical coupling. [ABSTRACT FROM PUBLISHER]

Sub-harmonic pulse injection-locked oscillators are becoming attractive candidates for the design of clock multipliers and as building blocks of phase-locked loops. Unfortunately, due to the large amplitude of the injected signals, these circuits cannot be analyzed with conventional methods and very-time-consuming simulations are needed to determine their phase noise performance. Phase-noise simulations are particularly critical when the ratio N between the output and the injection frequency gets large. To address the above issue, this paper provides an efficient computation flow to derive the phase noise of pulse injection-locked oscillators. The flow simply requires the computation of the phase-domain response and the phase noise of the free-running oscillator. An analytical expression, herewith demonstrated and compared against commercial simulation tools, allows calculating the phase noise of the injection-locked oscillator for any frequency ratio N. [ABSTRACT FROM AUTHOR]

In this work, we propose a physical memristor/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship. The proposed model is capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time. The developed compact model has been validated against two physical devices, fitting unipolar and bipolar switching. With no requirement of Verilog-A code, LTSpice, and Spectre simulations reproduce distinctive phenomena such as the preforming state, voltage/cycle dependent random telegraph noise and device degradation. [ABSTRACT FROM PUBLISHER]