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Radix- $2^{k}$ delay feed-back and radix-K delay commutator are the most well-known pipeline architecture for FFT design. This paper proposes a novel radix-22 multiple delay commutator architecture utilizing the advantages of the radix-22 algorithm, such as simple butterflies and less memory requirement. Therefore, it is more hardware efficient when implementing parallelism for higher throughput using multiple delay commutators or feed-forward data paths. Here, we propose an improved input scheduling algorithm based upon memory to eliminate energy required to shift data along the delay lines. A 1024-point FFT processor with two parallel data paths is implemented in 65-nm CMOS process technology. The FFT processor occupies an area of 3.6 mm2, successfully operates in the supply voltage range from 0.4–1 V and the maximum clock frequency of 600 MHz. For low voltage, high performance applications, the processor is able to operate at 400 MHz and consumes 60.3 mW or 77.2 nJ/FFT generating 800 Msamples/s at 0.6 V supply. [ABSTRACT FROM AUTHOR]

This paper presents a novel control technique for a wide output voltage range digitally controlled SIDO boost converter. It employs minimum phase conditions reported in refid="ref1"/ , refid="ref2"/ and extends the same to SIDO boost converter to eliminate the effect of RHP zero. Further, the proposed work employs input-output linearization technique refid="ref3"/, refid="ref4"/ to linearize the control-to-output transfer function across different operating points to achieve improved stability under unbalanced loads and a wide output voltage range on each output of the proposed SIDO boost power converter. The SIDO boost regulator was verified experimentally for an input voltage of 3.3 V and a maximum simultaneous load current of 350 mA on each output. Measurement results demonstrate that the proposed design achieves a wide output voltage range of 4.8 V–13.75 V, with ability to dynamically transition across these different output voltages in both small and big voltage steps. [ABSTRACT FROM AUTHOR]

In this paper, the classical CMOS Schmitt trigger (ST) operating in the subthreshold regime is analyzed. The complete DC voltage transfer characteristic of the CMOS ST is determined. The metastable segment of the characteristic is explained in terms of the negative resistance of the NMOS and PMOS subcircuits of the ST. Small-signal analysis is carried out to determine the minimum supply voltage at which the hysteresis appears and to obtain a rough estimation of the hysteresis width. It is shown that the theoretical minimum supply voltage required to obtain hysteresis is 2ln( $2+\surd 5$ )kT/q = 75 mV at room temperature. A test chip with CMOS Schmitt triggers was designed and fabricated in a 180 nm technology in order to study their operation at supply voltages between 50 mV and 1000 mV. [ABSTRACT FROM AUTHOR]

This paper presents a physics-based mathematical model for anionic memristor devices. The model utilizes Poisson- Boltzmann equation to account for temperature effect on device potential at equilibrium and comprehends material effect on device behaviors. A detailed MATLAB based algorithm is developed to clarify and simplify the simulation environment. Moreover, the provided model is used to simulate and predict the effect of oxide thickness, material type, and operating temperatures on the electrical characteristics of the device. The parameters of the proposed model are tuned and validated using experimental data of a fabricated wire based NbO1–x junction. This device is attractive for neuromorphic and computing applications, where multilevel state is desirable. The value of this contribution is to provide a framework intended to simulate anionic memristor devices using correlated mathematical models. In addition, the model can be used to explore device materials and predict its performance. [ABSTRACT FROM PUBLISHER]

Two important drawbacks of parallel coupled LC quadrature oscillators (P-QOSC) which have not heretofore been addressed thoroughly in the literature are obviated simultaneously in this paper. The first, has to do with the inevitable off-tune operation of the tank which results in quality factor (Q) degradation, and hence, phase noise deterioration. The other, stems from process, voltage, and temperature (PVT) variations which exacerbate quadrature accuracy. Here, a feedback loop is presented which generates a control signal by mixing the quadrature outputs and tunes the injection strength in the coupled oscillators autonomously. A complex coupling factor is implemented which compensates the phase error to prohibit phase noise degradation. The operation of proposed loop is comprehensively studied mathematically. Measurement results of a 0.18 \mu{\text m} CMOS prototype with an active area of 0.5 {\text{mm}}^{2}$ and an overall power consumption of 5 mW corroborate the functionality of the proposed method. Finally, experimental results prove FoM of 185 dB for the core oscillator and a quadrature phase error of less than 0.8^{\circ}. [ABSTRACT FROM PUBLISHER]

This paper presents comprehensive analyses of power-performance tradeoffs in current-mode logic (CML)-based transmitters via equation-based optimization and provides practical design guidelines that can help achieving optimum power efficiency. An accurate equation-based optimization framework was developed for this purpose, and using this framework, key circuit-level design parameters were found with specific design specifications and process technologies. The proposed optimization framework can determine optimum clock edge-rate (i.e., ratio of rise/fall time to clock period) and inter-stage voltage swings that enable significant power savings without affecting performance. Various transmitter design tradeoffs were analyzed for 45-nm, 65-nm, and 90-nm technologies considering data rate, clock edge-rate, and inter-stage swing optimization. Based on the analysis results, we determined the most energy-efficient data rate that can be achieved with acceptable power overhead for each technology node. Also, we identified the optimal clock edge-rate and inter-stage voltage swings in CML gates that achieved minimum transmitter power dissipation. Our analysis results indicate that, when properly optimized, overall transmitter power consumption can be reduced by up to 43% with inter-stage swing optimization with all other design constraints held constant. [ABSTRACT FROM AUTHOR]

In this paper, we explore and describe the electromechanical coupling which results from eKEH conditioning circuits implementing a rectangular QV cycle, including but not limited to the charge pump and Bennet’s doubler circuits. We present numerical and semi-analytical analyses describing the nonlinear relationship between the oscillating mass and the conditioning circuit. We believe this is a poorly understood facet of the device and, as we will portray, affects the potential harvested energy. An approach to determine the frequency shift due to the electromechanical coupling is presented and compared with novel experimental results. We provide some examples of bifurcation behavior and show that the only source of nonlinearity is in the coupling between the electrical and mechanical domains. This work continues from the electrical analysis presented in Part 1, providing a full insight into the complex behavior of the electromechanical coupling. [ABSTRACT FROM PUBLISHER]

Sub-harmonic pulse injection-locked oscillators are becoming attractive candidates for the design of clock multipliers and as building blocks of phase-locked loops. Unfortunately, due to the large amplitude of the injected signals, these circuits cannot be analyzed with conventional methods and very-time-consuming simulations are needed to determine their phase noise performance. Phase-noise simulations are particularly critical when the ratio N between the output and the injection frequency gets large. To address the above issue, this paper provides an efficient computation flow to derive the phase noise of pulse injection-locked oscillators. The flow simply requires the computation of the phase-domain response and the phase noise of the free-running oscillator. An analytical expression, herewith demonstrated and compared against commercial simulation tools, allows calculating the phase noise of the injection-locked oscillator for any frequency ratio N. [ABSTRACT FROM AUTHOR]

This paper presents new design procedure for a general class-E power amplifier, here referred to as quasi-class-E, with finite dc-feed inductance and switch on-resistance and variable duty cycle under variable voltage switching (VVS), and variable derivative voltage switching (VDS), taking into account the switch breakdown voltage. It is shown that for non-zero switch on-resistance in class-E power amplifier, zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions do not necessarily result in maximum efficiency. Hence, by assuming VVS and VDS, new design equations are derived. The new equations can be solved with a simple and fast numerical method in MATLAB. The theoretical results show efficiency improvement for quasi-class-E power amplifier compared to conventional designs. Circuit simulations confirm the validity of the theoretical results. [ABSTRACT FROM AUTHOR]

This paper presents a design-oriented analytical approach for predicting fast-scale instability in power electronics converters under voltage-mode control strategy. This approach is based on the use of the ripple amplitude of the feedback control voltage as an index for predicting subharmonic oscillations in these systems. First, the work revisits the stability analysis technique based on the nonlinear discrete-time model, demonstrating that the ripple amplitude can be included within the expression of the Jacobian matrix of this model, hence giving a mathematical support to extend the ripple index to more complex topologies. A simple but representative buck converter under voltage-mode control is used to illustrate the approach. Using the ripple-based index, closed-form expressions of stability boundaries are derived. Unlike other available results obtained from existing methods, the stability boundary, in this work is expressed analytically in terms of both power stage and controller design parameters. Moreover, one can determine how these parameters are involved in the closed form expressions and, furthermore, how each parameter affects the stability of the system. The approach is validated by numerical simulations from the state equations and also experimentally within a wide range of the design parameter space. [ABSTRACT FROM PUBLISHER]

With the advances in biochemistry, molecular biology, and neurochemistry there has been impressive progress in understanding the molecular properties of anesthetic agents. However, there has been little focus on how the molecular properties of anesthetic agents lead to the observed macroscopic property that defines the anesthetic state, that is, lack of responsiveness to noxious stimuli. In this paper, we develop a mean field synaptic drive firing rate cortical neuronal model and demonstrate how the induction of general anesthesia can be explained using multistability; the property whereby the solutions of a dynamical system exhibit multiple attracting equilibria under asymptotically slowly changing inputs or system parameters. In particular, we demonstrate multistability in the mean when the system initial conditions or the system coefficients of the neuronal connectivity matrix are random variables. Uncertainty in the system coefficients is captured by representing system uncertain parameters by a multiplicative white noise model wherein stochastic integration is interpreted in the sense of Itô. Modeling a priori system parameter uncertainty using a multiplicative white noise model is motivated by means of the maximum entropy principle of Jaynes and statistical analysis. [ABSTRACT FROM AUTHOR]

In this work, we propose a physical memristor/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship. The proposed model is capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time. The developed compact model has been validated against two physical devices, fitting unipolar and bipolar switching. With no requirement of Verilog-A code, LTSpice, and Spectre simulations reproduce distinctive phenomena such as the preforming state, voltage/cycle dependent random telegraph noise and device degradation. [ABSTRACT FROM PUBLISHER]

Frequency characteristics of the total feedback loop of a current-mode buck DC-DC converter in the discontinuous conduction mode (DCM) are examined by formulating an equivalent small-signal transfer function using a proposed block structure that does not suffer direct influence from the current feedback. Utilizing this transfer function, it is clarified that the type of the compensation slope in a current feedback loop affects the loop frequency characteristics in DCM, and in terms of stability, high voltage gain and large 0-dB frequency bandwidth, the quadratic compensation slope is more effective than the linear compensation slope. The validity of the proposed block structure and formulations and the effectiveness of applying a quadratic compensation slope instead of a linear compensation slope in DCM are verified by comparing calculation results, SPICE simulation results and evaluation results using circuit and measurement data from an MOS current-mode buck DC-DC converter IC that had been previously fabricated. More than 10-dB higher voltage gain, three times larger 0-dB frequency bandwidth, more than 10-degree larger phase margin and faster recovery time in load current change are realizable in DCM compared with the case using a linear compensation slope. [ABSTRACT FROM AUTHOR]

In order to maximize randomness of CMOS Ring Oscillators (RO) used in Random Number Generators (RNG), possibility of weak inversion operation of CMOS transistors is investigated. To predict weak inversion noise performance of RO, phase noise and jitter models of a CMOS RO in weak inversion operating region are obtained. Differential Ring Oscillator (DRO) and Inverter-based Ring Oscillator (IbRO) cases are both investigated. For each case, the model covers the flicker and the white noise component of phase noise and jitter. The derived models are verified by measurement results. 0.25 \mum standard CMOS process has been used with a supply voltage of 0.7 V for DRO and 0.5 V for IbRO. Furthermore, phase noise and jitter behavior of a CMOS RO in strong and weak inversion region are compared through analytical models, simulations, and measurements. Even though white noise component of phase noise uses two different models for weak and strong inversion regions of operation, these two models exhibit continuity. Flicker noise component in weak inversion is much lower than the one in strong inversion, which also reduces the corner frequency. For a fair comparison of randomness performances, a randomness parameter is defined and randomness equations are derived for each case. [ABSTRACT FROM PUBLISHER]

Frequency splitting phenomena are investigated systematically by circuit theory in a series-tuned contactless power transfer (CPT) system. First, in a symmetrical CPT system, the splitting equation is defined and the key frequency splitting characteristics are described by the trough and the ridge equations in a complete fashion. The even and the odd splitting frequencies are exactly two roots of the ridge equation; the splitting coupling is determined theoretically when the even and odd splitting frequencies merge together. Second, in an unsymmetrical CPT system, the idea of the trough and the ridge equation is exploited to find exactly the splitting coupling. Next, the relationship between frequency bifurcation and splitting is elucidated; and a zero-phase control method is suggested to track the splitting frequency when the coupling changes in the splitting region. Finally, the theoretical results are validated by a 10-W prototype with planar spiral coils. [ABSTRACT FROM PUBLISHER]

The use of pathological elements (i.e., nullators, norators, and the voltage mirror-current mirror pair) as universal active elements opens up the possibility to model the behavior of active devices with either differential features or input-output multiples, in order to be used in analysis tasks of linear(ized) analog circuits. This brief tries on the modeling this class of active devices, which is carried out by considering the impedance characteristics along with the behavior equation of each active device, the kind of signal to be processed and by applying the pathological element properties. In order to obtain a more realistic model, not only parasitic elements associated to the input-output terminals of each active device are considered, but the tracking errors of voltage and current differential followers modeled with grounded pathological elements and admittances are also included. Due to that the gain and tracking errors are finites and of limited bandwidth, a two-pole model is used for each of them in order to include their contributions on the symbolic expressions computed. Because the behavior of fully-differential amplifiers is modeled with grounded pathological elements, a standard nodal analysis can be performed. This imply that not only the size of the admittance matrix is smaller than those generated by applying modified nodal analysis (MNA) method, for instance, but also the number of nonzero elements and the generation of cancellation-terms are both reduced. As a result, the computational complexity during the solution of the system of equations is reduced when recursive determinant-expansion techniques are applied. Examples are described and compared with the MNA method, in order to show the usefulness of the proposed models to compute fully-symbolic small-signal characteristics of analog circuits containing fully-differential active devices and/or with input-output multiples. [ABSTRACT FROM AUTHOR]

We suggest an approach to use memristors (resistors with memory) in programmable analog circuits. Our idea consists in a circuit design in which low voltages are applied to memristors during their operation as analog circuit elements and high voltages are used to program the memristor's states. This way, as it was demonstrated in recent experiments, the state of memristors does not essentially change during analog mode operation. As an example of our approach, we have built several programmable analog circuits demonstrating memristor-based programming of threshold, gain and frequency. In these circuits the role of memristor is played by a memristor emulator developed by us. [ABSTRACT FROM PUBLISHER]