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Harmonic content modulation of the oscillator output voltage can contribute to flicker noise up-conversion in LC-tuned oscillators. The paper reports a quantitative analysis of the effect in Van der Pol oscillators using the framework of the impulse sensitivity function (ISF). It is shown that most of the up-conversion efficiency results from the first harmonic of the ISF, which is not perfectly in quadrature to the output voltage waveform, and from the first harmonic of the transistor current, which is slightly lagging the voltage waveform. A closed-form expression of 1/f3 phase noise in voltage-limited LC-tuned oscillator is derived that is in good agreement with circuit simulations. The paper also shows that the values of both phase shifts are determined by the non-linearity of the active element and are linked to the relevant oscillator parameters, i.e., excess gain and tank quality factor. [ABSTRACT FROM PUBLISHER]

In this paper, we consider the problem of out-of-band quantization noise suppression in the general family of direct digital-to-RF (DDRF) conversion circuits, where the RF carrier is amplitude modulated by a quantized representation of the baseband signal. Hence, it is desired to minimize the out-of-band quantization noise in order to meet stringent requirements such as receive-band noise levels in frequency-division duplex transceivers. In this paper, we address the problem of out-of-band quantization noise by introducing a novel signal-processing solution, which we refer to as "segmented filtering (SF)." We assess the capability of the proposed SF solution by means of performance analysis and results that have been obtained via circuit-level computer simulations as well as laboratory measurements. Our proposed approach has demonstrated the ability to preserve the required signal quality and power amplifier (PA) efficiency while providing more than 35-dB attenuation of the quantization noise, thus eliminating the need for substantial post-PA passband RF filtering. [ABSTRACT FROM AUTHOR]

As externally powered microsystems become more common, designers need better tools to understand power delivery systems such as non-resonant capacitive coupling. In this paper we present the first general method which allows a designer to easily model power delivery through capacitive coupling. The method uses a power iteration technique which allows one to analyze systems when the time to charge the coupling capacitor is longer than a charge cycle, enabling us to analyze a greater range of systems than previously possible. In fact, we are able to model the entire system with an equivalent resistance. We show that our model accurately reproduces both static and dynamic characteristics of the exact solution and that this model is general, in that it is valid for capacitor charge times that are longer as well as shorter than a charge cycle. This model also reveals several regions of operation where different parameters (e.g., capacitance, frequency and series resistance) dominate, allowing the designer to quickly and intuitively understand the design space for capacitive power transfer. [ABSTRACT FROM PUBLISHER]

In this paper, a novel class of element-wise inverse Jacket transforms (EIJT) with many parameters are proposed for signal length N = 3 × 2r. The EIJT has 2N-1 independent parameters. It is shown that the inverse transform of the proposed EIJT can be easily obtained by taking each reciprocal entry of the forward matrix of Jacket transform and then transposing the resulting matrix. Their fast transforms are also developed. Due to their simplicity, the proposed EIJT transforms may be used in many transform-based applications, where their independent parameters may provide more degrees of freedom such as affording an additional secret key in watermarking and encryption applications. [ABSTRACT FROM PUBLISHER]

Stability conditions for 2-D shift-varying systems are presented. The shift-varying nature of such systems emerges in applications such as adaptive filtering or adaptive image processing, where the coefficients are neither static nor periodic. The forms considered in this paper are the Givone-Roesser and the Fornasini-Marchesini models, both of which are discrete 2-D state-space filters. The sufficient conditions for BIBO stability that are proven herein are an outgrowth of the 1-D time-varying state-space conditions that have been previously established. The nature of feedback in the 2-D space is explored and found to be much more complex than for the 1-D case. However, it is also shown that when every feedback path is guaranteed to satisfy a variation on exponential stability, then BIBO stability of these two models can be assured. Further conditions are also established which engage the Lyapunov equation and guarantee the exponential stability requirement. [ABSTRACT FROM PUBLISHER]

In this paper and in its companion, a novel cut-based decomposition for transfer functions of linear time-invariant circuits is introduced and an invariance property, with respect to the cut, is proven for the set of quantities introduced by this cut-based decomposition. These results naturally lead to a novel feedback theory of electric circuits which, unlike Bode's feedback theory, is based on the unambiguous decomposition of transfer functions. Such feedback theory provides a natural extension to the elementary model of feedback amplifiers based on block diagrams, from system theory to circuit theory, and a natural extension to Blackman's formula. [ABSTRACT FROM PUBLISHER]

Aiming for the simultaneous realization of constant gain, accurate input impedance match, and minimum noise figure over a wide frequency range, the circuit topologies and detailed design of two broadband dual-loop negative feedback power-to-current low noise amplifiers (LNAs) are presented in this paper: 1) a resistive indirect-feedback power-to-current LNA, which requires an active part with two output terminal pairs, and 2) a transformer feedback power-to-current LNA, which requires a transformer in its current feedback path having a high turn ratio with high magnetic coupling. For both LNAs the feedback networks and active part implementations are discussed in detail. It is shown that for this purpose a novel stacked transformer can be realized using only two metal layers. The two LNAs are designed to be implemented in a 0.2 m GaAs p-HEMT technology process to verify the theory presented. Counter measures are applied to deal with the effects of bond wires and the effects of transformer parasitics on the circuit performance are analyzed. Simulation results show that the resistive indirect-feedback power-to-current LNA exhibits a 0.6-0.8 dB noise figure, an input return loss well below dB, a 200 mS voltage-to-current gain (which corresponds to 23 dB power gain for a 50 load) from 0.3 GHz to 4 GHz, a dBm third-order input intercept point (IIP3) and a 23 dBm second-order input intercept point (IIP2) at 2 GHz. It consumes 73 mA current from a 4 V power supply. The transformer-feedback power-to-current LNA achieves a 0.5-0.8 dB noise figure, an input return loss of less than dB, a 22 dB power gain from 0.8 GHz to 4 GHz, and a 0 dBm IIP3 and 22 dBm IIP2 at 2 GHz while drawing 53 mA current from the 4 V power supply. [ABSTRACT FROM PUBLISHER]

Ternary content-addressable memories (TCAMs) can perform high-speed and deterministic table lookups. However, its main drawback is high power consumption. A significant portion of the TCAM power is consumed by match-line sense amplifiers (MLSAs) for match detection. This paper presents a 20-kilobit TCAM featuring two MLSAs with positive-feedback techniques. The proposed circuits have been fabricated on a test chip in 0.18-μm CMOS technology. Energy measurement results of the two MLSAs show reductions of 56% and 48%, respectively, over the conventional current-race MLSA. [ABSTRACT FROM AUTHOR]

This paper describes a multiband CMOS chip-set for indirect and direct conversion base station receivers. The chip set consists of a low-noise amplifier (LNA), and a down-converter which includes a passive resistive mixer and a local-oscillator balun. The 0.25-µm CMOS receiver chip set, biased at 3 V, meets normal DCS1800, PCS1900, and Universal Mobile Telecommunication System (UMTS) base station specifications in heterodyne and homodyne architectures. In a heterodyne architecture, an third-order input intercept point (IIP3) higher than -5 dBm was achieved with a noise figure (NF) lower than 4.5 dB for the complete receiver chain in the DCS1800, PCS1900, and UMTS bands. In a homodyne architecture, IIP3 and second-order input intercept point (IIP2) values better than 0 and 40 dBm, respectively, were achieved for the complete receiver chain in all three bands, with an NF of less than 6 dB. A dedicated DCS1800 heterodyne receiver based on this chip-set was developed, meeting and exceeding the specifications, with a NF of 5.8 dB and IIP3 of 0.4 dBm. This is believed to be the first CMOS receiver chip set that meets second and third-generation base station specifications in indirect and direct conversion architectures. [ABSTRACT FROM AUTHOR]

This paper examines an embedded low-power technique for the single-shot measurement of GHz digital signals. Two circuits will be demonstrated; the first is a rise time measurement core, while the second represents an embedded technique for the characterization of narrow pulses. Both circuits can be seen as general tools to increase the low-end time dynamic range measurements of digital events in CMOS. The circuits rely on a new fast voltage-crossing detector to convert the input information and condition it into same polarity edges, separated by the timing information to be measured. Those edges are then in turn stretched further using time amplification, making them easily detectable with low-resolution time-to-digital converters. Dynamic current generation techniques are used in the front-end detector to greatly reduce the power consumption. The proposed circuits are compact and introduce only a few tens of femtofarads capacitive loading. The circuits were implemented in a standard 0.18-µm CMOS process. Experimental results show the feasibility of the proposed approach. Rise times of 1 ns and pulses as narrow as 78 ps were successfully captured in a single-shot measurement approach, with total power dissipation not exceeding a few milliwatts, in each of the two cases. [ABSTRACT FROM AUTHOR]

This paper describes a low-power approach to capacitive sensing that achieves a high signal-to-noise ratio (SNR). The circuit is composed of a capacitive feedback charge amplifier and a charge adaptation circuit. Without the adaptation circuit, the charge amplifier only consumes 1 µW to achieve the audio band SNR of 69.34 dB. An adaptation scheme using Fowler-Nordheim tunneling and channel hot-electron injection mechanisms to stabilize the dc output voltage is demonstrated. This scheme provides a very low frequency pole at 0.2 Hz. The measured noise spectrums show that this slow-time scale adaptation does not degrade the circuit performance. The dc path can also be provided by a large feedback resistance without causing extra power consumption. A charge amplifier with a MOS-bipolar pseudo-resistor feedback scheme is interfaced with a capacitive micromachined ultrasonic transducer to demonstrate the feasibility of this approach for ultrasound applications. [ABSTRACT FROM AUTHOR]

In this paper, using a minimum number of passive components, i.e., new grounded and floating inductance simulators, grounded capacitance multipliers, and frequency-dependent negative resistors (FDNRs) based on one/two modified current-feedback operational amplifiers (MCFOAs), are proposed. The type of the simulators depends on the passive element selection used in the structure of the circuit without requiring critical active and passive component-matching conditions and/or cancellation constraints. In order to show the flexibility of the proposed MCFOA, a single-input three-output (SITO) voltage-mode (VM) filter, two three-input single-output (TISO) VM filters, and an SITO current-mode (CM) filter employing a single MCFOA are reported. The layout of the proposed MCFOA is also given. A number of simulations using the SPICE program and some experimental tests are performed to exhibit the performance of the introduced structures. [ABSTRACT FROM AUTHOR]

This paper presents three pulsewidth modulation modulators using CMOS operational transconductance amplifiers. They consist of a ramp integrator and current-tunable Schmitt triggers. Prototype circuits built using discrete components exhibited that their duty cycles are linearly controllable. Because of their simple structure, the proposed modulators can be easily fabricated in a monolithic integrated circuit. [ABSTRACT FROM AUTHOR]

This paper describes high-precision switched-capacitor (SC) track-and-hold amplifier (THA) stages. They use a novel continuous-time correlated double sampling (CDS) scheme to desensitize the operation to amplifier imperfections. Unlike earlier predictive-CDS amplifiers, the circuits do not need a sampled-and-held input signal for their operation. During the tracking period, an auxiliary continuous-time signal path is established, which predicts the output voltage during the holding period. This allows accurate operation even for low amplifier gains and large offsets over a wide input frequency range. Extensive simulations were performed to compare the performance of the proposed THAs with earlier circuits utilizing CDS. The results verify that their operation is far more robust than that of any previously described SC amplifiers. [ABSTRACT FROM AUTHOR]

A framework for symbolic analysis and synthesis of linear active circuits has previously been proposed which is based on the use of admittance matrices and infinity-variables. The notation has the important advantage that it can describe both ideal circuit elements, for which an infinite limit is implied, and nonideal circuit elements for which matrix elements are considered finite. The nullor is a very important circuit element because it can represent the ideal operational amplifier and the ideal transistor. For the nonideal case, the use of finite matrix elements implies that the operational amplifier and transistor are both modelled as a voltage-controlled current source, which is fine if the transistor is a field effect transistor or if the operational amplifier is of the transconductance type, but not otherwise. The purpose of this paper is to apply the w-variable framework in order to derive alternative models for the nullor that can be used to model voltage, current and transresistance operational amplifiers and bipolar junction transistors. We also show that the ∞-variable description of an ideal transistor can include a factor to represent transistor geometry. [ABSTRACT FROM AUTHOR]

In this paper, we use the adjoint network theory to get quick estimates of the noise contributed by various elements in linear lime-invariant opamp based circuits. The noisy operational amplifier is represented using a nullor with an input referred noise voltage and current source. The adjoint model for this representation is derived. This makes the noise analysis of operational amplifier based circuits very simple and the contribution of the operational amplifiers to the output noise can be obtained very often by inspection. The method is applicable to amplifiers, active RC and MOSFET-C filters. Examples of circuits analyzed include the universal active filter and gyrator topologies. [ABSTRACT FROM AUTHOR]

This paper reports synthesis methodologies for linear analog circuits. A generalized multi-input operational transcon-ductance amplifier (OTA) network has been synthesized that can be easily progranuned to realize different analog functions. The design of the multifunction network has been realized without any switches. The inherent characteristic of OTA as a voltage-to-current (V-I) converter with differential input has been exploited in the synthesis procedure. Efficient analog circuits synthesized with progranunable OTA network are reported along with simulation results. The theoretical analysis supported by extensive experimental results confirms low sensitivity, high-frequency response, and efficient programmability of the proposed OTA network to realize different types of filters. [ABSTRACT FROM AUTHOR]

An invasive-attack-resistant physical unclonable function (PUF) with strong reliability is presented. The mismatch of capacitor ratios in real fabrication is sampled by a switched-capacitor (SC) circuit and further amplified by a latch-styled sense amplifier. Transmission lines connected to the sampling capacitors are used to cover and protect the whole chip from outside invasive attacks. The proposed SC PUF is fabricated using HJ standard 0.18 \mum CMOS process. Simulation results show that the invasive-attack-resistant sensitivity is less than 2.56 fF. The failed outside invasive attack efforts verify the anti-invasive-attack property of the PUF unit. Besides, measured results show that the proposed SC PUF circuit with 3 V/1.8 V-VDD achieves an error rate 1x-5.5x lower than other PUF implementations. An error correction block is also presented to achieve a nearly zero error rate. The measured average error rate, bias, average intra-die HD and average inter-die HD of the 3 V/1.8 V-VDD SC PUF with error correction block is 0%, 46.72%, 0%, and 49.84% respectively. [ABSTRACT FROM PUBLISHER]

A low noise transimpedance amplifier (TIA) is used in radiation detectors to transform the current pulse produced by a photo-sensitive device into an output voltage pulse with a specified amplitude and shape. We consider here the specifications of a PET (positron emission tomography) system. We review the traditional approach, feedback TIA, using an operational amplifier with feedback, and we investigate two alternative circuits: the common-gate TIA, and the regulated cascode TIA. We derive the transimpedance function (the poles of which determine the pulse shaping); we identify the transistor in each circuit that has the dominant noise source, and we obtain closed-form equations for the rms output noise voltage. [ABSTRACT FROM PUBLISHER]

Online adaptive equalization is proposed to calibrate channel mismatch errors in time-interleaved (TI) analog-to-digital converter (ADC) arrays with a linear reference path. Code-domain filters are shown to be effective in removing interchannel as well as intrachannel nonlinearity and mismatch errors, including offset, gain, and differential nonlinearity (DNL) and integral nonlinearity (INL) mismatches. An 8-bit, 600-MS/s, 0.13- μm CMOS prototype measured a signal-to-noise plus distortion ratio (SNDR) of 31.0/47.4 dB, a spurious-free dynamic range (SFDR) of 32.8/63.6 dB, a DNL of 1.30/0.30 LSBs, and an INL of 1.70/0.23 LSBs in lab testing without/with equalization, respectively. [ABSTRACT FROM PUBLISHER]

We propose novel direct and indirect learning predistorters (PDs) that employ a new baseband simplicial canonical piecewise linear (SCPWL) function. The performance of the proposed PDs is easily controlled by varying the number of segments of the SCPWL function. When comparing to polynomial-based PDs, our SCPWL-based PDs are more robust for modeling strong nonlinearities and are less sensitive to input noise. In particular, we show that noise appearing in the feedback path of an indirect learning SCPWL-PD has negligible effect on the performance while the polynomial counterpart suffers from a noise-induced coefficient bias. We consider adaptive implementations of both Hammerstein-based and memory-based SCPWL PDs; the former featuring less parameters to be identified while the latter renders more straightforward parameter identification. When deriving the PD algorithms, we avoid a separate PA identification step which allows for a true real-time, or sample-by-sample, implementation without an alternating PA and PD identification procedure. However, to arrive at efficient sample-by-sample algorithms for Hammerstein PDs we need to bypass the problem of the associated nonconvex cost function. This is done by employing a modified, linear-in-the-parameter, Wiener model whose parameters can be explicitly or implicitly used for both indirect and direct learning. Extensive simulations confirm that the proposed SCPWL PDs outperform their polynomial counterparts, especially when noise is present in the feedback path of the indirect learning structure. The same is also verified by circuit level simulations on the Freescale MRF6S23100H class-AB PA in an 802.16d WiMAX system. [ABSTRACT FROM PUBLISHER]

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, slew rate, and input/output range are carried out. Based on these analyses, a manual design methodology and a genetic algorithm based optimization are presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13 \mu \m 1.2 V standard CMOS technology are shown. [ABSTRACT FROM PUBLISHER]

None of the previously reported third-order and fourth-order operational transconductance amplifier and capacitor (OTA-C) elliptic filter structures use the minimum number of active and passive components. After an innovative algebraic decomposition for a complicated transfer function, i.e., a new analytical synthesis method, a current-mode odd-nth-order and a current-mode even-nth-order OTA-C elliptic filter structure having the following advantages are presented: 1) all the OTAs have single-ended inputs; 2) all the capacitors are grounded; 3) the minimum active and passive components are used. An equal-capacitance-type structure is designed taking into account the difficulty of precisely fabricating capacitances in integrated circuits. Although the above three advantages lead to the lowest total parasitics and to the most precise output response, the small deviations (such as the 3.5159% error in fp) of the four parameters of the new third-order OTA-C elliptic filter can be drastically reduced (for example, to 0.1553% error in fp) by only slightly tuning the four transconductances, but fixing the ratio of the given three capacitances, and without adding any other active and passive components. H-spice high-pass and low-pass simulations with 0.35-μm process are provided to demonstrate the theoretical results. [ABSTRACT FROM AUTHOR]

A new family of single-stage super Class-AB operational transconductance amplifiers (OTAs) suitable for low-voltage operation and low power consumption is presented. Three novel topologies are proposed featuring simplicity and compactness. They are based on the combination of adaptive biasing techniques for the differential input stage and nonlinear current mirrors for the active load that provide additional dynamic current boosting. The OTAs have been fabricated in a standard 0.5-mum CMOS process. Experimental results show a greatly improved slew rate by factors 30-60 and gain-bandwidth product by factors 11.5-17 when compared to a classical Class-A OTA. The circuits are operated at plusmn1-V supply voltage with only 10 muA of bias current [ABSTRACT FROM PUBLISHER]

Design equations for satisfying the off-nominal operating condition [i.e., only the zero-voltage switching (ZVS) condition] of the Class-E amplifier with a linear shunt capacitance at a duty ratio D = 0.5 are derived. A new parameter s (V/s), called the slope of switch voltage when the switch turns on is introduced to obtain an image of the distance from the nominal conditions. By examining off-nominal Class-E operation degree of the design freedom of the Class-E amplifier increases by one. In addition various amplifier parameters such as operating frequency, output power, and load resistance range can be set as design specifications. For example, the peak switch voltage and switch current can be taken into account in the design procedure. Examples of a design procedure of the Class-E amplifier for off-nominal operation are given. The theoretical results were verified with PSpice simulation and experiments. [ABSTRACT FROM AUTHOR]

An integrated receiver channel for a pulsed time-of-flight laser range finder is presented. The receiver operates in a wide dynamic range without gain control. This is achieved by converting the received unipolar pulse to a bipolar waveform already after the optical detector before the signal is fed to amplifier blocks. Thus the nonlinearities of the amplifiers have the minimum effect on the timing point, which is located in the zero crossing of the bipolar pulse. A parallel resonant circuit is used to shape the pulse in the input of the channel, which consists of a cascade of limiting voltage amplifiers followed by a comparator. The measurements show that the receiver has a walk error of 74 ps in the dynamic range of 1:1280. This corresponds to 11 mm in distance. The minimum usable input signal is limited by the noise of the receiver and equals 1.9 μA. [ABSTRACT FROM AUTHOR]

A methodology for the optimal parasitic-aware design of RF power amplifiers toward maximum power efficiency is presented. It is based on a template-driven simulation-based optimization approach, including the effect of all device parasitics (transistors, passives) during the sizing. The combination of expert knowledge (in the template) with a state-of-the-art evolutionary algorithm results in a highly flexible and optimal sizing methodology tailored to RF circuits. Parasitic information is obtained through interaction with device profilers. The methodology is implemented in a fully featured software tool called M-DESIGN and is applied to the optimal sizing of a two-stage Class E power amplifier for maximum efficiency. The complete sizing was obtained in less than one hour of CPU time. Moreover, the constraint templates that were used are presented and discussed. An amplifier manufactured in a commercial 0.35-μm SM2P CMOS process and sized using the proposed methodology shows a maximum value of 67% for the drain efficiency (DE) versus 66% simulated. Measurement results show that it works at 850 MHz and has a maximum output power of 30 dBm at 23 V. The power-added efficiency (PAE) is always greater than 60% for an output power above 160 mW and a maximum PAE of 66% is achieved. [ABSTRACT FROM AUTHOR]

A general procedure is presented for noise analysis and optimization in continuous-time operational transconductance amplifier (OTA)-C filters of arbitrary order and topology. Based on a matrix description of a general OTA-C filter structure, universal expressions are derived that permit computing the filter noise and optimizing the noise performance in any OTA-C filter. The results are not only useful for classical (discrete or integrated) OTA-C designs at medium to high frequencies but also in modern radio-frequency integrated circuits (RFICs) by carefully replacing transistors or electronic subcircuits by OTA (macro) models The formulas are easy to implement and are readily included in computer-aided analysis and optimization algorithms. The accuracy of the proposed algebraic method is confirmed by a coma parison with SPICE-simulation results. Two application examples are given: Finding the minimum-noise a multiple-loop-feedback filter configuration to implement fifth-order Butterworth and Bessel transfer functions, and determining the optimal biquad sequencing and gain distribution in a cascade realization of an eighth-order Butterworth filter. [ABSTRACT FROM AUTHOR]

A gain stabilization technique for tuned integrated low-noise amplifiers (LNAs) is presented. The proposed method regulates the LC-tuned load impedance of the amplifier at the operation frequency against variations of passive devices in integrated circuit (IC) process. The impedance stabilization technique is based on the excellent relative accuracy of integrated resistors. Although the absolute deviation of the integrated resistors can be as large as ±20%, the relative deviation can be made smaller than ± 1% provided that resistors are placed close to each other. By applying the proposed method, the voltage-gain variation of the inductively degenerated common-source LNA, which is the most popular LNA architecture, can be reduced several decibels. As a consequence, the entire radio receiver can more easily meet its specifications in the presence of IC process variations and the product yield is improved. Finally, besides the LNAs, the presented stabilization technique can also be utilized in other tuned amplifiers, filters or oscillators employing damped LC-tuned loads. [ABSTRACT FROM AUTHOR]