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This paper deals with nonlinear control of a single-phase half-bridge interleaved buck shunt active power filter (HBIB-SAPF) with a nonlinear load. The control objective for the system is twofold: performing power factor correction by compensating for harmonics and reactive current consumed by the nonlinear load from one hand and tightly regulating the HBIB converter DC capacitor voltage. Both objectives are accomplished using a two-loop nonlinear controller. The inner loop acts on the switching devices so that the active filter current tracks its reference with the aim of ensuring a unity power factor. This loop is tackled using backstepping technique and Lyapunov approach. The outer loop is responsible for regulating the DC capacitor voltage to its desired value, using a PI controller with a pre-filter. The stability analysis of the closed-loop system is formally performed by using the averaging theory. The validity of the designed nonlinear controller is checked by simulations in Matlab/SimpowerSystem showing its robustness and accuracy under various operating conditions. [ABSTRACT FROM AUTHOR]

This paper introduces a fully integrated switched-capacitor (SC) DC-DC boost converter suitable for energy harvesting in miniature sensor systems with varying harvesting source and battery voltages. Unlike the conventional SC DC-DC boost converters, where efficiency is optimized only for a few topology-dependent voltage conversion ratios (VCRs), the proposed soft-charging-based SC converter achieved VCR-insensitive evenly high efficiency for a wide range of input and output voltages. A test chip was fabricated in 180nm process, and the measured peak efficiency and average efficiency are 85.3% and 83.6%, respectively, for 1.8V regulated output voltage and a wide range of input voltages (0.95–1.8 V). Also, a peak efficiency of 88.9% and average efficiency of 87.6% are achieved for a wide range of battery output voltages (3.0–4.2 V) and a 1.2V harvesting source input voltage. [ABSTRACT FROM AUTHOR]

This paper presents a thermal/RF hybrid energy harvester. The energy harvesting system can scavenge energy from a thermoelectric generator (TEG) and a radio-frequency (RF) energy source simultaneously, and deliver the combined power to a single load. Two techniques are employed in the system to increase the end-to-end efficiency; the rectifying-combination technique is proposed to eliminate the power loss associated with a dedicated AC-DC converter before the combiner and an improved fractional open-circuit voltage (FOCV) maximum power tracking (MPPT) is considered for a high average efficiency. A dynamic power path control extracts the maximum RF power from a cross-coupled differential rectifier, and also behaves as an AC/DC energy combiner. The thermal/RF harvester system achieves a measured peak end-to-end power conversion efficiency (PCE) of 63.4%. The shorter sampling time of 26ms every 16s for the proposed FOCV MPPT method reduces the long charging tail required to refresh the sampling capacitor, resulting in a an improved average efficiency of 82.2% for the thermal harvester. Fabricated in 0.18 $\mu \text{m}$ CMOS technology, the prototype operates at a thermal input voltage ranging from 40 mV to 400 mV and an RF power from −18 dBm to −3 dBm and delivers an output voltage of 1.8 V. The total area of the fabricated circuit prototype is 1.22 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a study of compact multiple-output switched-capacitor voltage regulators (MOSCVRs). Two methods to produce multiple outputs with an SCVR and their effects on performance – power efficiency and cross-regulation, are examined with output impedance analysis. Moreover, to help a circuit designer to implement a compact MOSCVR, a design method to determine the number of outputs and their conversion ratios is also proposed in this work. To verify this method, we demonstrate the design of an example compact MOSCVR. The MOSCVR is capable of simultaneously producing four different output voltages from a single input power supply with only two flying capacitors and twelve switches. The study presented in this work provides not only comprehensive insight but also guidance to find the suitable topology of a compact MOSCVR. [ABSTRACT FROM AUTHOR]

This paper proposes a LLC type resonant forward converter using adjustable turning-off time control for low power and voltage applications. The new circuit is derived from the conventional LLC converter, and it has simple structure while maintaining decent soft-switching characteristics. The switching losses are reduced by ZVS (zero voltage switching) and ZCS (zero current switching). Also, regulation of the output voltage does not require a small ratio between magnetizing inductor and resonant inductor, so the leakage inductor of transformer can be utilized instead of an external inductor to realize resonance, which makes it possible to use only one magnetic component in the resonant topology. Besides, the adjustable turning-off time control strategy is adopted in the scheme, which optimizes the switching condition while ensuring the wide range operation. In comparison to the traditional PWM (pulse width modulation) control, the proposed control strategy can further reduce the switching loss and improve power efficiency. This is also suitable for the utilization of GaN (gallium nitride) devices due to the requirement of higher switching frequencies at wide input applications. In addition to the detailed theoretical analysis, the validity of the proposed concept is confirmed by the experimental results of a prototype. [ABSTRACT FROM AUTHOR]

Low-power circuits often employ dynamic voltage scaling and energy harvesting. Such circuits need a power management unit that can convert the voltage source to a wide range of target voltages with high efficiency. Targeting such a power management unit, this paper presents a reconfigurable architecture of switched capacitor (SC) voltage converter. It introduces a design optimization methodology that can determine trade-off among design parameters to meet the goal. The proposed converter employs a reconfigurable topology with four capacitors. It provides 11 conversion ratios: 6 step-down and 5 step-up ratios supporting wide input/output voltage range. An analytical model for the output impedance of the proposed reconfigurable SC topology is presented. Using the model, the proposed optimization methodology can minimize the total power dissipation. To validate the proposed architecture and optimization methodology, the converter has been implemented in a 130-nm CMOS process using integrated capacitors of total size 2.2 nF. Simulation results show that the optimized converter circuit achieves an efficiency range from 83.41% to 74.69% for a load current of $100~\mu \text{A}$. [ABSTRACT FROM AUTHOR]

In this paper, a generic, low-noise, negative-voltage generator with wide tuning range and moderate driving capacity is presented. The highly integrated solution, incorporating a fully-integrated charge-pump and a regulator block, requires only one off-chip capacitor that can be shared with the supply decoupling capacitors. The fully integrated charge-pump operation is analyzed quantitatively, and a closed-form expression of its output impedance is derived. Powered from a single 3.3-V dc input, the output has a tuning range from −4.4 to +2.1 V for biasing applications, while the design supports a maximum load current of 250, 550, and $800~\mu \text{A}$ for the regulated output voltage at −3.0, −1.5, and 1.5 V, respectively. The measured steady-state ripple is under 3 mVPP, while the noise voltage at the charge-pump operating frequency harmonics is below 130 $\mu \text {V}_{\mathrm{ rms}}$ and the noise floor is under $5~\mu \text {V}_{\mathrm{ rms}}$. The design is also the application verified with a gallium nitride power amplifier, thus further confirming its low-noise performance. Implemented in CMOS 180-nm process, the prototype chip occupies an area of 0.55 mm2. [ABSTRACT FROM AUTHOR]

This paper presents an area- and power-efficient dual-output switched capacitor (DOSC) dc–dc buck converter for wearable biomedical devices. The DOSC converter has an input voltage range between 1.05 and 1.4 V and generates two simultaneous regulated output voltages of 1 and 0.55 V. The DOSC consists of two main blocks: a switched capacitor regulator and an adaptive time multiplexing (ATM) controller. The switched capacitor regulator generates a single regulated voltage using pulse frequency modulation based on a predetermined reference voltage. In addition, the ATM controller generates two simultaneous output voltages and eliminates the reverse current using pulse width modulation during the switching between the output voltages. Addressing the reverse current problem is important to reduce the output voltage droop and improve the performance. The proposed converter supports load currents of 10– $350~\mu \text{A}$ and 1– $10~\mu \text{A}$ at load voltages of 1 and 0.55 V, respectively. The DOSC circuit is fabricated in 65-nm CMOS, and it occupies an active area of 0.27 mm2. Measured results show that a peak efficiency of 78% is achieved at a load power of $300~\mu \text{W}$. [ABSTRACT FROM AUTHOR]

It is essential to retain improved efficiency in a dc–dc converter over a wide load current range to extend the battery-life in portable devices. This requires a multi-mode controller, consisting of pulse-width-modulation (PWM) and pulse-frequency-modulation (PFM) schemes. However, existing approaches attempt to integrate structurally different controllers; thus it is difficult to achieve a seamless controller transition. While a digital platform offers controller configurations, it remains difficult to identify a suitable digital PWM/PFM technique and decide on its sampling mechanism to achieve stable behavior. This paper proposes a unified digital PWM/PFM scheme which shares a common digital PWM (DPWM) block and has the provisions for online controller configuration and automatic (switching) frequency adaptation. The proposed scheme retains improved efficiency over a wide operating range and inherently achieves seamless controller transitions. Further, a unified discrete-time framework is proposed for the analysis and design of the proposed multi-mode controller. Buck and boost converter prototypes are tested and the proposed controller is implemented using a field-programmable-gate-array device. [ABSTRACT FROM AUTHOR]

The series-capacitor boost converter (SCBC) requires a duty cycle ($D) \ge0.5$ control, otherwise has issues of power switch overstress and inductor currents imbalance. Then, we cannot use the SCBC in wide conversion ratio (CR) applications that require CR < 4. Meanwhile, the $D \ge0.5$ control does not allow $D$ to increase smoothly from 0 during start-up, causing severe inrush inductor currents. As a solution, we propose two control schemes on the capacitor-cross-connected (CCC) boost converter, which is the symmetric version of the SCBC. With the proposed hard-charging control, the CCC converter allows $D < 0.5$ without overstress or imbalance issues, thus extending the CR range and facilitating a soft start-up. In addition, we propose a soft-charging control that enhances the efficiency for 3< CR < 4. We study the output impedance and CR expressions under these two types of controls. Finally, we propose a compact centrosymmetric floorplan that reduces the switching nodes’ ringing, verifying the proposed schemes with a 2.8-to-8.4-V input / 24-V output prototype converter. It exhibits a soft start-up with the proposed control. Under an 8-V input voltage and 1.5-A output current, the peak efficiency of the proposed hard-charging and soft-charging control is 94.7% and 96.3%, respectively. [ABSTRACT FROM AUTHOR]

High step-up conversion is an indispensable feature for the power processing of low voltage renewable sources in grid-connected systems. Motivated by this necessity, this paper presents a study on non-isolated dc-dc converters based on the conventional Boost converter that can provide such feature with high efficiency. By the topological variation and gain cell concepts, it is demonstrated that these converters can be treated as a unique generalized converter, called Boost Converter with Gain Cell (BCGC). The operating principle, the key waveforms and the components stresses of the BGCG are analyzed for the continuous-conduction mode, independently of the employed gain cell. A methodology to create the gain cells is developed from the combination of coupled inductors and voltage multiplier techniques. In order to verify the realized analysis, a 150 W prototype concerning to the proposed generalized converter and able to operate with several different gain cells is developed for the comparison between theoretical and experimental static gain results. [ABSTRACT FROM PUBLISHER]

This paper proposes a fast transient quasi-V^2 fixed-frequency hysteretic buck converter designed and fabricated using TSMC 2P4M 0.35-\mum CMOS process. The proposed converter can achieve fixed frequency switching through a novel phase-locked-loop-based two-stage adaptive window control. Under ultralight load conditions, the proposed converter operates in a pulse frequency modulation mode to reduce the switching loss and improve light load efficiency. A quasi-V^2 technique is applied for obtaining inductor current information without relying on an output capacitor with a high equivalent series resistance; therefore, the output voltage ripple can be reduced. The experimental results show that the proposed converter can operate at a load current ranging from 18 to 700 mA, a supply voltage ranging from 2.7 to 4.2 V, and an output voltage of 1.2 V. The off-chip inductor and output capacitor are 2.2 \muH and 10 \muF, respectively. Through the PLL control, the switching frequency is maintained at 1 MHz. The transient response time is approximately 5 \mus, and the highest efficiency registered is 95.6%. [ABSTRACT FROM AUTHOR]

A systematic design approach using signal flow graph (SFG) is presented in this paper, tailored for integrated reconfigurable switched-capacitor (SC) power converters. To achieve an optimal power stage, an unified signal flow graph (USFG) model is developed. System transfer function and I/O impedance can be evaluated based on it. To verify the design approach, the paper demonstrates a step-up/down reconfigurable SC power converter with five optional gain ratios. A dual-loop control scheme is employed to reconfigure the converter according to the instantaneous line/load conditions. A low-power, digital controller is designed in the subthreshold region for the feedback control loop. The converter was fabricated with a 130-nm CMOS process. Experimental results show that its output can be continuously regulated from 0.4 to 2.2 V, while allowing the input voltage to randomly vary between 0.9 and 1.5 V. The line regulation is maintained below 1.4%, with a lowest value of 0.07%. The maximum efficiency of 90.22% is measured at 0.55-V output voltage and 20-mW load. [ABSTRACT FROM PUBLISHER]

Energy harvesting is an emerging technology for powering wireless sensor nodes, enabling battery-free operation of these devices. In an energy harvesting sensor, a power management circuit is required to regulate the variable harvested voltage to provide a constant supply rail for the sensor circuits. The power management circuit needs to be compact, efficient, and robust to the variations of the input voltage and load current. A closed-form power expression and custom control algorithm for regulation of a switched-capacitor DC-DC converter with optimal conversion efficiency are proposed in this paper. The proposed regulation algorithm automatically adjusts both the voltage gain and switching frequency of a switched-capacitor DC-DC converter based on its input voltage and load current, increasing the power efficiency across a wide input voltage range. The design and simulation of a fully integrated circuit based on the proposed power managing approach is presented. This power management circuit has been simulated in a 0.25 \mum standard CMOS process and simulation results confirm that with an input voltage ranging from 0.5 V to 2.5 V, the converter can generate a regulated 1.2 V output rail and deliver a maximum load current of 100 \muA. The power conversion efficiency is higher than 74% across a wide range of the input voltage with a maximum efficiency of 83%. [ABSTRACT FROM AUTHOR]

Multiple-supply are required to minimize the power consumptions in bio-implant systems. A single-inductor multiple-output (SIMO) switching converter is one of the solutions. But it has inherent problems which block the applications in the embedded biomedical systems. In this paper, a circuit arrangement for providing multiple outputs based on low-dropout (LDO) regulator is proposed. The regulating transistor of LDO is time-shared by N output legs. Two error amplifiers (EAs) are utilized in the topology, irrespective of number of the output legs. The corresponding switching strategy alleviates the difficulties associated with controlling multiple switching functions for conventional time-sharing methods, and thus, permits multiple outputs to be generated easily. A prototype multiple-output LDO (MOLDO) regulator with four output legs was fabricated with a standard 0.35 \mu\ m CMOS process. The measurement results verify the good performance of this design such as no cross regulation (CR), small ripples, and less power consumption. Moreover, it does not require inductor and presents low total harmonic distortion, which is very suitable for bio-implant fields. [ABSTRACT FROM PUBLISHER]

This paper explores the subharmonic oscillation mechanism for constant on-time control, which has been widely used for power supply controllers in industry. As well as analyzing the stability criterion, this research reveals that the circuit propagation delay (\Delta t) can significantly increase the demand of ESR\cdot Co value for stable operation in practical applications. A thorough study is provided based on the inductor current information and the charge variations of the output capacitor. Thus, critical condition for subharmonic oscillation is derived, and the effect of circuit propagation delay is also quantified. Based on detailed analysis, a prototype with constant on-time control and added inductor current ramp is built. Experimental results verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents an analysis on the effect of having different number of capacitors n in the first-stage switched-capacitor circuit of an improved hybrid switched-capacitor buck converter for high-voltage-gain conversion. Various aspects of the topology, operation, and efficiency are investigated. It is shown both analytically and experimentally that a higher n in the step-down capacitor stage does not necessarily lead to an overall improved power efficiency. A design and optimization method is thus proposed for the improved SC-buck converter. [ABSTRACT FROM PUBLISHER]

This paper proposes a highly integrated dual-side dual-output (DSDO) switched-capacitor (SC) converter with only two flying capacitors. Generally, a dual-phase voltage doubler and an inverter are used to supply positive and negative voltages for thin film transistor-liquid crystal display (TFT-LCD) gate drivers, respectively. Four flying capacitors, eight pin-outs for the four flying capacitors, and 16 power switches are necessary for their operations in the driver integrated chip (IC). The proposed DSDO SC converter combines both dual-phase voltage doubler and inverter converter in one channel through the use of time multiplexing technique with minimal performance degradation. As a result, the proposed converter not only reduces the number of flying capacitors from four to two, but also removes four IC pin-outs for lower cost and more compact size. Moreover, the 16 required power switches are reduced to 12, resulting in an approximated 27% decrease of the silicon area. [ABSTRACT FROM AUTHOR]

A two-stage hybrid power management unit (PMU) is presented with a highly-efficient novel ON-OFF LDO as the second stage and uses a switched-capacitor dc-dc divider as the first stage. The design targets IoT applications that operate across a wide range of load from sub-microwatt to 100’s of microwatts. The first stage provides a step-down using selectable sizing of its switches to improve efficiency to >95% across the target range of load current. The output voltage that is divided from the first stage is then regulated using the proposed ON-OFF LDO with a dropout voltage of < 30mV. The hybrid architecture regulates a 1.3V input to 0.4V and achieves a power efficiency of >80% for load ranges 1μ - 240μA. The design is fabricated in 28-nm CMOS technology. [ABSTRACT FROM AUTHOR]

The general structure of a multilevel multistate dc–dc converter is introduced, which is a hybrid between inductor-based (buck) converters and capacitor-based (switched capacitor) converters. The control of the new converter is hybrid between switched capacitor converters and buck converters, where the coarse tuning of the output voltage is achieved through the selection of an appropriate operating region similar to an SC converter, while fine tuning is achieved through the adjustment of a duty cycle value similar to a buck converter. A silicon implementation of a four-level four-state hybrid converter is presented as a specific example of the general hybrid converter structure. A new state interleaving technique was employed resulting in an increased effective switching frequency of the converter. Silicon measurements of the integrated four-level four-state converter on a 65-nm GF technology show that the converter can cover a wide range of output voltage values achieving a peak efficiency of 93% with a power density of 47 mW/mm2. The implemented converter attains a response time in the sub- ${\mu }\text{s}$ range with output voltage ripples below 50 mV. [ABSTRACT FROM AUTHOR]

A low energy-noise switched-capacitor (SC) sensor interface for resistive bridge sensor is presented. The SC amplifier achieves low-power metric with two operating modes using operation-phase-dependent biasing and compensation scheme in the op-amp design. This novel op-amp works in high-bandwidth high-power mode to sample the bridge signal for 13\mu \text s twice and in low-bandwidth low-power mode for 474\mu \text s over 500\mu \text s measurement interval. To further reduce the power of the SC amplifier in system level, a SC level-shift design is adopted. Regarding offset calibration, a capacitor divider based trimming scheme is implemented to generate the mid-point DC output voltage under the constraint of the feedback capacitor size. Implemented in 65 nm CMOS, the SC interface together with the regulator, voltage reference and trimming circuit occupies an area of 0.358 mm2. For the first test setup utilizing Half Wheatstone Bridge, the proposed SC amplifier consumes 12.3\mu \text W at 1 V regulated supply with a 2 kHz system clock. The measured Signal-to-Noise Ratio (SNR) of SC circuit is 55.6 dB. In the second test setup using a commercial sensor with 0.092 mV/kPa sensitivity, the interface has demonstrated the sensing function with sensitivity of 3.52 mV/kPa. Finally, compared to the representative prior-arts, this work has achieved the best energy-noise figure-of-merit at identical fractional resistance change. [ABSTRACT FROM AUTHOR]

A current-based resonant power delivery (CRPD) technique with multi-cycle switching has been presented that enables efficient inductive power transmission at large distances. Unlike the conventional inductive link, in which the receiver (Rx) LC-tank is utilized as a voltage source, the proposed CRPD switches the Rx LC-tank for several cycles in a novel fashion to utilize it as a current source. Therefore, the voltage across the load (RL) can be significantly higher than the Rx LC-tank voltage. This eliminates the need for DC-DC charge pumps or AC-DC voltage multipliers, which require several capacitors and diodes. In CRPD, the energy is first stored in the Rx coil by shorting the Rx LC-tank for several power carrier cycles. At the peak of Rx coil current, the coil energy is then transferred to RL for a quarter of the power carrier cycle. The circuit theory behind CRPD has been developed and verified with simulation results. A proof-of-concept CRPD was also characterized in measurements to demonstrate its feasibility. In measurements, CRPD was capable of achieving the DC voltage of 3.1 V across an RL of 100 \textk\Omega, by switching the Rx LC-tank at 50 kHz with an AC voltage amplitude of 1 V across the Rx coil at the operation frequency of 1 MHz. Moreover, compared to a conventional inductive link followed by a passive rectifier, to achieve a minimum DC voltage of 2.8 V across an RL of 100 \textk\Omega the proposed CRPD extended the range from 7 cm to 13 cm for the same voltage across the transmitter coil. [ABSTRACT FROM AUTHOR]

A high efficiency, maximum power point tracking (MPPT) power management unit (PMU), with 3.6 \mmb\mu\bf W quiescent power, aimed at a thermoelectric generator (TEG) array is presented. The proposed energy harvesting PMU is made up of a boost converter with a cascaded capacitor-less low drop-out (CL-LDO) voltage regulator. The segmented approach allows the PMU to match the TEG array's changing dynamic series resistance via the boost converter and simultaneously provide voltage regulation with adaptive, high switching noise rejection via the CL-LDO. The boost converter's switching frequency (f{sw}) is tracked via a Sense-and-Control loop which modifies the CL-LDO's power supply rejection (PSR) characteristics to place a notch in the PSR transfer function around the average f{sw}. Experimental results show an overall system efficiency better than 57% @ 1.6 V output voltage, PSR of 40 dB at f{sw}, and a notch-tuning range of 15–65 kHz. The total active area is 0.93 mm^2 in 0.5 \mum CMOS. [ABSTRACT FROM PUBLISHER]

A high efficiency 3.3 V-to-1 V switched-capacitor (SC) step-down DC-DC converter with load-dependent frequency control (LFC) and deep-green mode (DGM) operation is proposed for system-on-a-chip (SoC) application. According to output loading current, the LFC technique can immediately and dynamically adjust the switching frequency through the use of pseudo-clock generator (PCG) and lead-lag detector (LLD) circuit to obtain high power conversion efficiency and small output voltage ripple over a wide loading current range. Therefore, adequate loading current supplying function and output voltage regulation can be guaranteed. Moreover, the DGM operation, similar to pulse skipping mode, can mask the switching clock to reduce power loss at ultra-light loads for further improving power efficiency. The test chip fabricated in 55 nm CMOS process demonstrates that the proposed fast transient converter can deliver wide load range from 10 mA to 250 mA with two small flying capacitors (CF1, CF2 =0.1\ \muF) and one output capacitor (COUT =1\ \muF). The peak conversion efficiency is 89% compared to the ideal value of 91% (3* VOUT/VIN). In other words, the peak normalized efficiency is equal to 98%. The overall normalized efficiency is always kept higher than 90% while the output voltage ripple is guaranteed smaller than 30 mV. [ABSTRACT FROM PUBLISHER]