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This paper presents a comprehensive design space exploration for boosting energy efficiency of a fast Fourier transform (FFT) VLSI accelerator, exploiting several approximate multipliers (AxM) combined with approximate adder (AxA) circuits. The FFT hardware herein presented consists of a fixed-point sequential architecture using a radix-2 butterfly with decimation in time. We explore a set of AxMs – namely Dynamic Range Unbiased (DRUM), Rounding-based Approximate (RoBA), leading one Bit-based Approximate (LoBA), and Truncated approach – jointly with the LOA, ETA-I, CopyA, CopyB, Trunc0, Trunc1 approximate adders. The approximate arithmetic operators are used in the butterfly kernel with exploration of the approximation levels (for the ${L}$ and ${K}$ least-significant bits, respectively, for the AxM and AxA), aiming at discovering the most energy-efficient configuration under a design-time QoR constraint. The mean square error and peak signal-to-noise ratio metrics define which approximate levels combining ${L}$ and ${K}$ variations will enable the FFT to process signals to generate spectrograms without significant losses. Our results show that the LoBA multiplier with $L$ =8 together with the LOA, Trunc1 and Trunc0, at different approximation levels, provide most energy savings with controllable quality degradation, presenting a minimum decrease of 20.2% in power dissipation without degrading the spectrogram generation quality. [ABSTRACT FROM AUTHOR]

This paper proposes a fingerprint scanning analog front-end (AFE) for a $41\times32$ under-glass mutual-capacitive fingerprint sensor. As the mutual-capacitive fingerprint sensor is a smaller version of a projected-capacitive touch screen, this transparent fingerprint sensor can be mounted underneath screen cover glass. However, such glass significantly diminishes the signal-to-noise ratio (SNR) of fingerprint scanning AFE in proportion with increasing glass thickness. Moreover, external noise interferences from the display and charger are severe in displays with thin form factor. The proposed fingerprint scanning AFE can achieve a 17 atto-farad capacitance resolution using high-voltage (20 V) transmitters and multi-channel receivers comprising a pipelined readout amplifier, mixer, and second-order low-pass filter (128 kHz). A differential sensing structure and band-pass filtering are employed in the receiver front-end to enhance the noise immunity. A differential phase-encoded sequential driving transmitter with a proposed on-chip replica channel mitigate random offsets in the readout amplifier with high matching accuracy. Measurement results show that the fingerprint scanning integrated circuit (IC) fabricated by a $0.18 ~\mu \text{m}$ BCD (Bipolar-CMOS-DMOS) process achieved a 13.4 dB SNR at a frame rate of 120 Hz under a 0.2 mm-thick cover glass. The prototype IC provides 20 VPP noise immunity from 0 to 500 kHz and consumes 23.2 mW from a 3.3 V supply. [ABSTRACT FROM AUTHOR]

This paper presents direct sequence spread spectrum (DS/SS) datalinks operating at 92-100 GHz with spreading factors up to 100K. Unlike traditional DS/SS datalinks which rely on preamble and cyclic dispreading for synchronization, the reported datalink uses a self-synchronous demodulation scheme, avoiding the large hardware complexity associated with exceptionally large spreading factors, and avoiding the difficulties of synchronizing the long de-spreading codes that are applicable to mm-wave systems. A demonstration link chipset is presented operating at 92-100 GHz with a spreading factor of 104K and a spread bandwidth of 6.0 GHz (baseband bandwidth of 56Kb/s) while consuming a total of 425mW. [ABSTRACT FROM AUTHOR]

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, −3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with V DD of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area. [ABSTRACT FROM AUTHOR]

Time-interleaved analog-to-digital converters can significantly increase system sampling rate, but channel mismatches, such as gain mismatch, offset mismatch and phase mismatch, can cause great error in the system. The problem of broadband mismatches calibration for multichannel time-interleaved analog-to-digital converters system will be discussed in this paper by using the foreground calibration technique. Essentially, the calibration can be divided into two steps: First, all the mismatches between analog input and digital output will be measured by taking a linear frequency modulated signal as the reference signal; Next, a set of finite-impulse response filters will be calculated based on those mismatches to generate frequency dependent mismatches compensation, so that the signal to noise and distortion ratio, and spurious-free dynamic range will not be limited by the channel mismatches. There are two advantages of the proposed method when compared with previous methods. The complexity of error estimation can be reduced dramatically and high precision error estimation can also be achieved. In order to evaluate the performance, a series of experiments were conducted in a two-channel time-interleaved analog-to-digital converter system. The results show that the spurious-free dynamic range is improved by more than 10dB. [ABSTRACT FROM AUTHOR]

Approximate computing is an efficient approach for reducing computational costs. This method involves a trade-off between computational accuracy and the circuit’s power consumption, delay, and area. However, the accuracy requirements may differ for different applications. In some situations, precise results are required. Therefore, this paper proposes an accuracy-configurable radix-4 adder (ACRA), which uses the power gating technique to turn on or turn off the partial logic gates of an adder element dynamically to compute accurate or approximate results. When the ACRA operates in the approximate mode, the partial sum of one adder element is modified to reduce the error distance between the approximate and accurate results. A comparison of the ACRA with two state-of-the-art accuracy-configurable adders indicated that the ACRA achieved the best trade-off between the power–delay product and computational accuracy. In addition, in the image processing experiment conducted in this study, under half-approximate computation, the peak signal-to-noise ratio of the ACRA was less than 1 dB and its structural similarity index measure was maintained above 0.99. These results are superior to those obtained for other accuracy-configurable adders. [ABSTRACT FROM AUTHOR]

A novel galvanic isolated amplifier based on CMOS integrated Hall sensors is presented in this paper. Two serially connected Hall-effect sensors are integrated along with their instrumentation amplifiers using the TSMC 65nm process. A printed-circuit board is employed to validate the proposed isolation amplifier by assembling the chip with chopper modulator, coil driver, miniature coil, variable gain amplifier, and anti-aliasing filter. Because of the miniaturized size of isolation components, this approach can be packaged in chip for industrial applications. This solution replaces the need of bulky/frequency dependent current transformers, complex isolation amplifiers with embedded analog to digital converters, and allows proposed sensors to be used in voltage and current sensing applications. The introduced prototype achieves an input referred offset of 1 mV, 50 dB full-scale signal-to-noise ratio in a 10 kHz bandwidth, and spurious-free dynamic range of 53 dB, while satisfying continuous isolation working voltage of 550 V. [ABSTRACT FROM AUTHOR]

This paper presents a single-coarse dual-fine architecture that improves energy-efficiency of pipelined-SAR analog-to-digital converters (ADCs). A coarse and fast sub-ADC is used to quantize the most significant bits (MSBs), which are encoded with a proposed residue transformation method to control the residue generation of the first stages in two fine channels. The residue voltages generate on the capacitive digital-to-analog converters (C-DACs) of split fine channels directly without successive approximation processes. Therefore, the conversion rate is increased and the power is reduced. A shuffle mechanism is introduced into split-ADC based digital background calibration to avoid the divergence of the conventional algorithm in the proposed architecture. A high-energy-efficiency dynamic amplifier is also introduced as the residue amplifier. A 14-bit 60-MS/s ADC is prototyped in a 28-nm CMOS process. The digital calibration engine operates under 0.9-V supply, other parts of the ADC core operate under 1.05-V supply. The ADC core consumes 4.26 mW. Measurement results show that the calibration improved the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) dramatically, the calibrated ADC achieves SNDR and SFDR of 66.9 dB and of 91.0 dB respectively, translating to a Schreier FoM of 165.4 dB and a Walden FoM of 39.3 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper presents the design and experimental characterization of a Proton Sound Detector (ProSD), a device that physically captures and senses the weak acoustic signal emitted by the fast energy deposition at the end of the same proton beam range. The measured acoustic signal Time-of-Flight provides a very accurate ($13~\mu \text{m}$ accuracy) measure of the proton beam penetration depth in water, improving the proton range verification accuracy w.r.t. previous works in pre-clinical scenarios. This suggests interesting possibilities for high-accuracy and real-time beam monitoring and calibration in hadron-therapy for cancer treatment. The detector has been fully characterized and tested with a physical 20 MeV proton beam in a water energy absorber. The ProSD and the water tank have been mounted in front of the exit layer of a 20 MeV 120 ns pulse time-width proton beam. A clear sinusoidal-like acoustic signal of 5 Pa and 2.3 MHz frequency has been detected at 12 dB SNR with 0.8 Gy single shot dose. After averaging 10 beam shots the achieved Signal-to-Noise-Ratio is 22 dB allowing a $\pm 7.5~\mu \text{m}$ precision vs. previously reported $\pm 45~\mu \text{m}$ ionoacoustic precision. [ABSTRACT FROM AUTHOR]

In all-digital transmitters (ADTs), delta-sigma modulation (DSM) is the most popular encoding method. However, implementing DSM-ADT on a field-programmable gate array (FPGA) produces problems with high complexity and low carrier frequency (CF) agility. To solve these problems, an agile ADT based on a look-up table (LUT) is proposed in this paper. The encoding and upconversion are implemented using the LUT, which defines the mapping between the intermediate frequency (IF) complex signal and the radio frequency (RF) binary signal. In addition, different CFs correspond to different LUT values. In this way, the CF can be adjusted flexibly by updating the LUT values, which makes the architecture of the ADT simple and easy to implement. To enhance the signal-to-noise ratio (SNR) and coding efficiency(CE), the noise of the encoder is analyzed and key-parameter selection methods are presented. Simulation results show that the proposed architecture achieves better performance in terms of the SNR and CE than current state-of-the-art approaches. The proposed agile ADT is also implemented on an FPGA. For 16-QAM modulated signals with 5 MBd and 20 MBd symbol rates (SRs), most measured SNRs are better than 45 dB and 40 dB, respectively, with CF varies from 0.65 GHz to 6.85 GHz. [ABSTRACT FROM AUTHOR]

This paper proposes a high power-performance-area efficient background noise aware keyword-spotting (KWS) processor based on an optimized binarized weight network (BWN). To reduce the power consumption while maintaining the system recognition accuracy for different background noise, the KWS processor with a SNR prediction module can be adaptively configured to use dual computing modes (standard computing mode and approximate computing mode) for both high recognition accuracy under high background noise and ultra-low power consumption under low background noise. The mel-scale frequency cepstral coefficients (MFCC) module is optimized with approximate computing technologies, which can reduce the power consumption by up to $3.1\times $ and $5.7\times $ for high/low background noise, respectively. Based on the evaluation of the architecture design space exploration, an ultra-low power BWN accelerator with low voltage, area and leakage power and using precision self-adaptive approximate computing units was proposed. Evaluated under 22nm process technology, this work can support up to 10 keywords real time recognition with power consumption of $15.1~\mu \text{W}$ for high background noise and $10.8~\mu \text{W}$ for low background noise. Compared to the state-of-the-art KWS architectures, our work can achieve ultra-low power consumption (about $1.7\times $ reduced), while maintaining high system capability and adaptability. [ABSTRACT FROM AUTHOR]

Slewing in switched capacitor (SC) circuits reduces the available time for linear settling, and hence increases the nonlinear settling error. This transient demand in current can be supplied by making the bias currents larger in the operational transconductance amplifier (OTA). However, this increases the static power consumption significantly. In this paper a slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to the SC circuit so that OTA does not need to provide high peak current. This may eliminate slewing altogether, and allows using OTAs with less static current for the same settling accuracy. The operation of the proposed technique is illustrated by incorporating it in a second-order delta-sigma modulator (DSM). The modulator was designed and simulated in a 65nm CMOS process. Post-layout extracted simulations with optimized design show more than 12 dB improvement in signal to noise and distortion ratio (SNDR) for the same static power. Alternatively, compared to a DSM without such technique, the same performance can be achieved with 30% less power. [ABSTRACT FROM AUTHOR]

The benefits of the ordering technique to improve the static linearity performances of digital-to-analog converters are discussed. Different techniques of grouping or sequencing elements are studied for segmented, binary or unary DAC architectures. The statistic of ordered elements and their properties are reviewed and studied. Then, the optimal selection of elements for a binary or unary use is discussed. The paper also estimates the limit caused by gradient, a systematic offset, and a non detected interval in the comparator used for the sorting. Results show that the use of segmented architecture with 8~16 groups of elements sorted and optimally selected grants 2~3 bits more in the performance. The benefit can become 5 bits for 128 groups at the cost of more significant efforts for the ordering. [ABSTRACT FROM AUTHOR]

This paper describes the design of a touch screen panel (TSP) readout IC having an in-band noise immunity. The proposed IC employs a cascaded spread spectrum TSP driving scheme combining chirp spread spectrum (CSS) and pseudo-random (PR) orthogonal sequences. The CSS shows the 12-dB spread gain prior to an application of PR sequences, resulting in total -24-dB in-band noise immunity. The proposed IC adopts trans-impedance amplifier (TIA) with differential current scaler (DCS), providing dynamic range of an analog front-end (AFE) only for a capacitive change from touches. The IC was fabricated in a 0.13- $\mu \text{m}$ standard CMOS. The measurement result shows that the proposed AFE achieves 54.2-dB SNR and 240-Hz scan rate with 11.5-mW power consumption. The readout IC was demonstrated with 5.3-inch $31\times16$ TSP. [ABSTRACT FROM AUTHOR]

This paper presents a linear-mode light detection and ranging (LiDAR) analog front-end architecture with multiplex analog-to-digital converter/time-to-digital converter (ADC/TDC). An added voltage-to-time converter (VTC) and a reused TDC are simultaneously used to implement the ADC and TDC function, thus replacing discrete ADC and TDC, saving hardware cost and reducing power consumption. A three-stage inverter-based transimpedance amplifier (TIA) with ultra-low-power, low-noise and high/low gain mode (long/short range mode) is proposed to reduce its influence to optical signal-to-noise ratios (OSNR). The prototype TIA and ADC/TDC is fabricated in the 65-nm CMOS technology and integrated into the single-line APD-based LiDAR system. The receiver front-end of TIA and ADC/TDC only consumes 12.44-mW. The minimum detection current of the receiver front-end is less than 238 nA with bandwidth of 150MHz for long-range and weak-light detection. LiDAR achieves a measurement range of 60 m with a 70-klx direct sunlight and only 6.16 mW average laser power. Experimental results show that this architecture is suitable for low-cost multi-line integrated LiDAR applications compared to conventional architecture using ADC, TDC, ADC+TDC architecture. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) that uses a digital-to-analog converter (DAC) configurable window switching technique. By reusing the capacitors in the DAC, the proposed window switching scheme yields window boundaries to determine whether the input is located within the window, and thus avoid unnecessary capacitor switching. The proposed window SAR ADC improves the conversion efficiency and ADC linearity. A qualitative analysis of prior window switching schemes is presented to elaborate for various applications. A low-input capacitance of 1 pF was adopted to relax the input and reference buffers. A prototype ADC was implemented in 180-nm CMOS occupying an active area of 0.1 mm2. At 20 MS/s, it consumes a total power of 1.22 mW from a 1.5-V supply. The measured peak signal-to-noise and distortion ratio and spurious-free dynamic range were 61.7 and 79 dB, respectively. At the Nyquist rate, the measured effective number of bits (ENOB) was 9.53, equivalent to a figure-of-merit (FOM) of 83 fJ/conversion-step. In low-power mode (100 kS/s), it consumed a total power of $1.5~\mu \text{W}$ from a 0.7-V supply. At the Nyquist rate, the measured ENOB was 9.82, equivalent to a FOM of 16.6 fJ/conversion step. [ABSTRACT FROM AUTHOR]

This paper presents a fingerprint mutual capacitive touchscreen panel (TSP) readout IC, which uses a differential coded multiple signaling (DCMS) method. A readout IC with high SNR and fast frame rate is required for fingerprint recognition. However, achieving high SNR is challenging owing to the limited capacitance difference originating from the small depth variations between the ridges and valleys of the fingerprint. In addition, scanning the entire fingerprint TSP with multiple electrodes is time-consuming. A fully differential receiver with DCMS is proposed to detect the low capacitance difference in a fingerprint TSP. The internal noise is minimized by the low-noise amplifier, and external noise is eliminated by a lock-in sensing architecture. In addition, DCMS reduces the offset and enhances the SNR while achieving faster frame rate in multiple channels. The proposed architecture can detect capacitance of 50 aF, which is the capacitance difference resulting from the ridges and valleys of a finger under a 0.3-mm-thick (T) cover glass. The readout IC achieves 15.1-dB peak-to-peak SNR and 23-Hz frame rate with a transparent mutual capacitive fingerprint TSP under 0.3T glass. The power consumption is below 21 mW at 3.3-V supply voltage. The IC was fabricated using a 0.18- $ {\mu }\text{m}$ standard CMOS process. [ABSTRACT FROM AUTHOR]

The error floor phenomenon, associated with iterative decoders, is one of the most significant limitations to the applications of low-density parity-check (LDPC) codes. A variety of techniques from code design to decoder implementation have been proposed to address the error floor problem, among which post-processors have shown to be both effective and implementation-friendly. In this paper, we take the inspiration from simulated annealing to generalize the post-processor design using three methods: quenching, extended heating, and focused heating, each of which targets a different error structure. The resulting post-processor is demonstrated to lower the error floors by two orders of magnitude for two structured code examples, a (2209, 1978) array LDPC code and a (1944, 1620) LDPC code used by the IEEE 802.11n standard. The post-processor can be integrated with a belief-propagation decoder with minimal overhead. The post-processor design is equally applicable to other structured LDPC codes. [ABSTRACT FROM AUTHOR]

Generalized integrated interleaved (GII) codes have attracted much attention in distributed storage systems since they can reduce the overall redundancy by creating redundancy shared by the interleaves. The Berlekamp-Massey (BM) algorithm makes the GII decoding efficient by reusing the preceding results at each decoding stage. However, it also forms the speed bottleneck of GII decoders. The reformulated inversionless Berlekamp-Massey (riBM) algorithm is well known for its short critical path, but it is not generally suitable for GII decoding since its polynomials are difficult to be reused directly. In this paper, we address this issue by reinitializing the polynomials and propose a riBM-based GII decoding algorithm. In our simulations, slight performance degradation induced by the first-layer miscorrection is observed in the high signal-to-noise ratio (SNR) region. Hence, a subtle method is introduced to handle the miscorrected interleaves. Furthermore, the hardware architecture of the proposed decoding algorithm is developed and a high throughput decoder for the given example GII code is implemented. The synthesis results under TSMC 28-nm technology show that the decoder can achieve a throughput of up to 124 Gb/s. Moreover, the decoder has been implemented into a field-programmable gate array (FPGA) to validate its error-correction performance. [ABSTRACT FROM AUTHOR]

In this paper, we present a simple and robust voice activity detection algorithm using a generalized exponential kernel (GEVAD). Taking advantage of a non-linear metrics, kernel functions are used to classify acoustic signatures as speech and non-speech. The analysis are performed for different signal features in the frequency domain, based on elements of the short-time discrete Fourier transform as well as in time domain, namely the short time energy. The performance of all the features was compared to each other and the best was assessed by the GEVAD algorithm. Also, insights of how to choose the best kernel function are given based in frame error rate analysis. To test the efficiency of our approaches, comparisons with other existing algorithms are presented, with GEVAD showing better performance in adverse environments as stationary (and non-stationary) low signal-to-noise ratio. [ABSTRACT FROM AUTHOR]

Pulse compression (PuC) is exploited in several applications, where the impulse response of a linear system must be estimated in a noisy environment. In nondestructive testing (NDT), PuC based on frequency-modulated signals is applied with sensors of different types. The presence of sidelobes in the impulse response retrieved after the PuC is a major drawback of the method as it degrades the quality of the estimation. To limit this effect, the matched filter is usually shaped by means of windows. Here, a windowing function based on reactance transformation is proposed that outperforms the most used ones in terms of near-sidelobes level reduction and sidelobes oscillations suppression. Numerical and experimental data were used to validate the technique. It is shown that the proposed approach is particularly suitable for those NDT techniques, such as eddy current and thermography that use very broadband excitations. The proposed window function is first introduced and applied to linear frequency-modulated signals and then extended to nonlinear frequency-modulated signals, which are needed in some applications. The quite general framework introduced in this paper for designing frequency-modulated signals and optimizing sidelobes is of general validity and can be successfully exploited in any application relying on chirp PuC. [ABSTRACT FROM AUTHOR]

This paper presents a 2.3 GS/s 12-way time-interleaved pipelined-SAR ADC achieving 1.1 GHz input bandwidth with 47.4 dB signal-to-noise distortion ratio (SNDR). Here, we propose a hierarchical interleaving with passively shared sub-sampling front-end to eliminate the timing skews, thus avoiding the timing calibration for design simplicity as well as better area and power efficiency. To provide a fast signal transfer with good power efficiency to the sub-ADCs, the power and bandwidth trades off by using the passive sharing or active buffers are analyzed according to our developed mathematic model. The analysis is based on two scenarios: noise and matching limited sampling. Moreover, we propose a boosting-capacitor-sharing technique to enhance the compactness of the time-interleaved bootstrapped sampling front-end, which is particularly critical when omitted the time calibration in this design. Measurement results on a 65 nm CMOS prototype operated at 2.3 GS/s and 1.2 V supply show 31 mW total power consumption with a SNDR of 47.4 dB @Nyquist leading to a FOM of 69 fJ/conv.step. [ABSTRACT FROM AUTHOR]

In this paper, signal-to-noise ratio (SNR) degradation from random clock jitter in a current-steering digital-to-analog converter (CS-DAC) is analyzed based on a timing-to-amplitude error conversion method. A closed-form equation is derived to predict SNR for white noise clock jitter (WN-J) and low-pass filtered clock jitter (LPF-J) in non-return-to-zero (NRZ) and return-to-zero (RZ) DAC. Especially for the clock source with LPF-J, our equation predicts that the return-to-zero (RZ) DAC SNR is better than what the conventional analysis foresees due to the high-pass filter function derived in our analysis. Our analysis completely captures both WN-J and LPF-J in NRZ and RZ DAC, and is verified in both MATLAB simulation and measurement with the difference of less than 2 dB. [ABSTRACT FROM AUTHOR]

This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively. [ABSTRACT FROM AUTHOR]

The use of a single-bit quantizer in a wideband CT \Delta \Sigma \textM is attractive, as the quantizer can be implemented in a power and area-efficient manner. Unfortunately, 1-bit CT $\Delta \Sigma $ Ms are plagued by a host of difficulties. Clock jitter and quantizer metastability are particularly problematic, and the higher loop filter linearity needed to process the full-scale feedback waveform results in increased power dissipation. The use of a finite impulse response (FIR) feedback DAC is a power efficient way of addressing the challenges above. However, even this technique runs into difficulties at multi-GHz clock rates. This paper introduces the idea of time-interleaved (TI) FIR feedback to enhance the performance of a conventional FIR DAC. A single-bit CT \Delta \Sigma \textM that uses a $2\times $ TI-FIR DAC achieves 67.6/68.8/76 dB SNDR/SNR/DR in a 60 MHz bandwidth. Designed in a low leakage 65 nm CMOS process, the modulator operates at 6 GHz and occupies only 0.07 mm2. Its Walden Figure of Merit is 56.5 fJ/lvl. [ABSTRACT FROM PUBLISHER]

In conventional charge redistribution successive approximation register (SAR) ADCs that use a single comparator, the comparator offset causes no distortion but a dc shift in the transfer curve. In loop-unrolled (LU) SAR ADCs, on the other hand, mismatched comparator offset voltages introduce input-level-dependent errors to the conversion result, which deteriorates the linearity and limits the resolution. Still, the literature lacks a quantitative analysis on this phenomenon, and the resolution of most reported SAR ADCs of this kind, until recently, has been limited to 6 bit. In this paper, we analyze the effects of comparator offset voltage mismatch in LU-SAR ADCs, and establish the quantitative relation between individual offsets and the signal-to-noise-and-distortion ratio (SNDR) and the effective-number-of-bits. A statistical linearity model is proposed for yield estimation. Finally, an on-line deterministic calibration technique for auto-zeroing dynamic comparator offset is presented to treat the offsets mismatch and improve linearity. A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7 to 42.9 dB. The ADC consumes 640~\mu \textW from a 1.2-V supply with a figure-of-merit of 37.5 fJ/conv-step. [ABSTRACT FROM PUBLISHER]

This paper presents a discrete time 2-1 MASH Delta-Sigma ( $\Delta \Sigma )$ modulator with multirate opamp sharing for analog-to-digital converters, targeting the optimization of power efficiency in active blocks, such as opamps and quantizers. Through the allocation of different settling times to the opamps and by adopting the multirate technique, the power of the shared opamps is utilized more efficiently, and the 4-b successive approximation register quantizer and the data weighted averaging block in the first stage enjoy additional operation time. Moreover, a detailed analysis and related simulations are presented to validate the enhanced opamp power efficiency in the proposed sharing scheme. The 65-nm CMOS experimental chip running at multirate 120/240 MHz achieves a mean signal-to-noise and distortion ratio (SNDR) of 77.1 dB for a 5-MHz bandwidth, consuming 4.2 mW from a 1.2 V supply and occupying 0.066-mm2 core area. It exhibits a Walden figure of merit (FoM) of 69.7 fJ/conv-step and a Schreier FoM of 167.9 dB based on SNDR. [ABSTRACT FROM PUBLISHER]

This paper analyzes the effect of the offset mismatch in time-interleaved analog-to-digital converter (TI-ADC) circuits on bit error rate (BER) performance of a receiver for pulse amplitude-modulated or quadrature amplitude-modulated signals in orthogonal frequency division multiplexed systems. Exact BER expressions, as well as simplified BER expressions that hold for high signal-to-noise ratios (SNRs) and large offset mismatch values only, are derived. From the obtained exact BER expressions, a condition is established on the offset mismatch level, under which the BER performance shows an error floor at high SNRs. Numerical results further show that if we keep the offset mismatch level below 25% of the threshold above, which the offset mismatch causes an error floor, there is essentially no BER performance degradation compared with the offset-mismatch free case. Our analysis further evinces that the tolerable level of the offset mismatch is proportional to the square-root of the number of sub-ADCs, indicating that as opposed to what might be expected, the offset mismatch level that can be tolerated actually increases with the number of sub-ADCs. [ABSTRACT FROM PUBLISHER]

This paper proposes a 5-b 5-GS/s time-based flash ADC in 65-nm digital CMOS technology, which utilizes both rising and falling edges of the clock for sampling and quantization. A dual-edge-triggered scheme reduces the dynamic power consumption of a voltage-to-time converter and the clock buffers by half. We doubled both the reset and the available regeneration times by interleaving the time comparators. The ADC has a low input capacitance and the calibration circuit is included on-chip for suppressing various mismatches. The prototype running at 5 GS/s consumes 7.8 mW from a 1-V supply and achieves a signal-to-noise and distortion ratio of 26.19 dB at Nyquist. The resulting figure of merit is 94.6 fJ/conversion-step and the core area is only 0.004 mm2. [ABSTRACT FROM PUBLISHER]

Harmonic-reject mixers (HRM) are commonly used in wideband receivers to suppress the effects of spurious harmonic interferers. Both analog and digital HRMs have been proposed in the literature. In existing works, the local oscillator (LO) phases are assumed to be equally spaced. When viewed as a multiuser access system, the drawback of equally-spaced LO phases is that the signature vectors of the desired signal and some harmonic interferers become aligned, limiting the number of interferers that can be attenuated. In this paper, a digital HRM with non-uniform phase spacing that can suppress additional harmonics while being robust to gain and phase mismatches is described. This paper also presents a low-complexity, adaptive and robust digital HRM receiver that enables the fewest LOs and analog-to-digital converters necessary depending on the interference environment for low power. The performance of the adaptive non-uniformly spaced HRM is shown to be significantly superior to existing HRMs with equal LO phase spacing. [ABSTRACT FROM AUTHOR]

Spiking neural networks (SNNs) receive trains of spiking events as inputs. In order to design efficient SNN systems, real-valued signals must be optimally encoded into spike trains so that the task-relevant information is retained. This paper provides a systematic quantitative and qualitative analysis and guidelines for optimal temporal encoding. It proposes a methodology of a three-step encoding workflow: method selection by signal characteristics, parameter optimization by error metrics between original and reconstructed signals, and validation by comparison of the original signal and the encoded spike train. Four encoding methods are analyzed: one stimulus estimation [Ben’s Spiker algorithm (BSA)] and three temporal contrast [threshold-based, step-forward (SW), and moving-window (MW)] encodings. A short theoretical analysis is provided, and the extended quantitative analysis is carried out applying four types of test signals: step-wise signal, smooth (sinusoid) signal with added noise, trended smooth signal, and event-like smooth signal. Various time-domain and frequency spectrum properties are explored, and a comparison is provided. BSA, the only method providing unipolar spikes, was shown to be ineffective for step-wise signals, but it can follow smoothly changing signals if filter coefficients are scaled appropriately. Producing bipolar (positive and negative) spike trains, SW encoding was most effective for all types of signals as it proved to be robust and easy to optimize. Signal-to-noise ratio (SNR) can be recommended as the error metric for parameter optimization. Currently, only a visual check is available for final validation. [ABSTRACT FROM AUTHOR]

This paper considers the set membership fusion estimation problem for the general multisensor dynamic systems with unknown but bounded noises. In order to achieve the ellipsoidal fusion formulae, we divide the set membership filter problem into two steps: the prediction step and the fusion update step. The proposed method has the following nice properties. First, each step can be converted into a semidefinite programming problem, which can be efficiently computed. Second, part-analytical formulae of the shape matrix and the center of the bounding ellipsoid can be derived by using a decoupled technique, which can significantly reduce the computational complexity. Moreover, the relationship between the fusion center and local sensors can be clearly revealed based on the ellipsoidal fusion formula. Finally, it is interesting that the ellipsoidal fusion formula is similar in form to the classic mean-squared error filter fusion, although they are of the different optimization frameworks. However, the fusion weights of the information matrix provided by the different sensors are different and the optimal fusion weights can be calculated by solving a convex optimization problem. A typical numerical example in target tracking demonstrates the effectiveness of the proposed centralized and distributed fusion formula. [ABSTRACT FROM AUTHOR]

This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable reference ripple tolerance, thus significantly relaxing the reference settling requirement. To verify the proposed technique, a prototype 10-bit 100-MS/s SAR ADC is fabricated in a 40-nm CMOS process. Equipped with the proposed technique, it only requires a 0.5-pF decoupling capacitor and an on-chip low-power reference buffer consuming 0.26-mW static power. The proposed technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL) and differential non-linearity (DNL) by 15 times. Overall, the prototype ADC achieves an SNDR of 56.3 dB at Nyquist rate while consuming 1.4 mW, including on-chip reference buffers. [ABSTRACT FROM AUTHOR]

This paper presents a digital blind background calibration technique of imperfections in time-interleaved analog-to-digital converters (TI-ADCs). The proposed technique directly operates on the statistics of the input signal to continuously estimate and eliminate the conversion errors resulted from offset, gain, and timing mismatch. Behavioral simulations are presented for a 4-channel 10-bit TI-ADC in order to verify the effectiveness of the proposed method. The signal-to-noise-and-distortion ratio (SNDR) is enhanced from 33.7 dB to more than 61 dB using the introduced calibration technique. This calibration method converges after roughly 4 \times 10^6 conversions. [ABSTRACT FROM AUTHOR]

In energy-constrained applications like Body Area Networks (BAN) receiver performance is traded for lower power consumption. The limited receiver performance will deteriorate the output signal-to-noise-ratio (SNR) and bit-error-rate (BER) of the receiver. In this paper we present closed-form output SNR and BER models of a non-ideal receiver front-end with limiter-discriminator demodulator for binary FSK. The presented model is very useful in defining the minimally required receiver specifications. Moreover, the models are useful for gaining insight into the influences of the receiver impairments on its performance. In the models, the gain and phase imbalances between the in-phase and quadrature-phase paths as well as the receiver generated noise and the phase noise produced by the local frequency reference are taken into account. This paper shows that the gain and phase imbalances shift the FM threshold to higher carrier-to-noise-ratios (CNR) and only have small influence on the SNR above threshold. On the other hand, receiver generated noise reduces the output SNR both below and above the FM threshold, and phase noise limits the maximum output SNR. Additionally, a trade-off between the FSK frequency deviation and phase noise robustness is derived. [ABSTRACT FROM PUBLISHER]

This article revisits the concept of “noise measure” and its importance in designing high-frequency low-noise amplifiers. A new derivation is offered which is simpler than the original derivation of Haus and Adler. Several examples are used to calculate the minimum noise measure of a CMOS amplifier. It is also shown that “noise cancellation” techniques cannot improve the minimum noise measure. [ABSTRACT FROM AUTHOR]

A multi-access multiple-input multiple-output (MIMO) relay differential chaos shift keying cooperative diversity (DCSK-CD) system is proposed in this paper as a comprehensive cooperation scheme, in which the relay and destination both employ multiple antennas to strengthen the robustness against signal fading in a wireless network. It is shown that, with spatial diversity gains, the bit error rate (BER) performance of the proposed system is remarkably better than the conventional DCSK non-cooperation (DCSK-NC) and DCSK cooperative communication (DCSK-CC) systems. Moreover, the exact BER and close-form expressions of the proposed system are derived over Nakagami fading channels through the moment generating function (MGF), which is shown to be highly consistent with the simulation results. Meanwhile, this paper illustrates a trade-off between the performance and the complexity, and provides a threshold for the number of relay antennas keeping the user consumed energy constant. Due to the above-mentioned advantages, the proposed system stands out as a good candidate or alternative for energy-constrained wireless communications based on chaotic modulation, especially for low-power and low-cost wireless personal area networks (WPANs). [ABSTRACT FROM AUTHOR]

This paper studies optimal tracking performance issues for multi-input-multi-output linear time-invariant systems under networked control with limited bandwidth and additive colored white Gaussian noise channel. The tracking performance is measured by control input energy and the energy of the error signal between the output of the system and the reference signal with respect to a Brownian motion random process. This paper focuses on two kinds of network parameters, the basic network parameter-bandwidth and the additive colored white Gaussian noise, and studies the tracking performance limitation problem. The best attainable tracking performance is obtained, and the impact of limited bandwidth and additive colored white Gaussian noise of the communication channel on the attainable tracking performance is revealed. It is shown that the optimal tracking performance depends on nonminimum phase zeros, gain at all frequencies and their directions unitary vector of the given plant, as well as the limited bandwidth and additive colored white Gaussian noise of the communication channel. The simulation results are finally given to illustrate the theoretical results. [ABSTRACT FROM PUBLISHER]

This paper presents a mutual capacitive touch screen panel (TSP) readout IC (ROIC) with a differential continuous-mode parallel operation architecture (DCPA). The proposed architecture achieves a high product of signal-to-noise ratio (SNR) and frame rate, which is a requirement of ROIC for large-sized TSP. DCPA is accomplished by using the proposed differential sensing method with a parallel architecture in a continuous-mode. This architecture is implemented using a continuous-type transmitter for parallel signaling and a differential-architecture receiver. A continuous-type differential charge amplifier removes the common-mode noise component, and reduces the self-noise by the band-pass filtering effect of the continuous-mode charge amplifier. In addition, the differential parallel architecture cancels the timing skew problem caused by the continuous-mode parallel operation and effectively enhances the power spectrum density of the signal. The proposed ROIC was fabricated using a 0.18-$\mu$m CMOS process and occupied an active area of 1.25 \text{mm}^{2}. The proposed system achieved a 72 dB SNR and 240 Hz frame rate with a 32 channel TX by 10 channel RX mutual capacitive TSP. Moreover, the proposed differential-parallel architecture demonstrated higher immunity to lamp noise and display noise. The proposed system consumed 42.5 mW with a 3.3-V supply. [ABSTRACT FROM PUBLISHER]

Noise shaping digital quantizers, most commonly digital delta-sigma $(\Delta\Sigma)$ modulators, are used in fractional- $N$ phase-locked loops (PLLs) to enable fractional frequency tuning. Unfortunately, their quantization noise is subjected to nonlinear distortion because of the PLL's inevitable non-ideal analog circuit behavior, which induces spurious tones in the PLL's phase error. Successive requantizers have been proposed as $\Delta\Sigma$ modulator replacements with the advantage that they reduce the power of these spurious tones. However, the quantization noise from previously published successive requantizers is only first-order highpass shaped, so it usually causes more PLL phase noise than that from the second-order and third-order $\Delta\Sigma$ modulators commonly used in PLLs. This paper presents second-order and third-order successive requantizers to address this limitation. Additionally, successive requantizer design options are presented that result in either lower-power spurious tones or lower phase noise compared to $\Delta\Sigma$ modulators when used in PLLs. [ABSTRACT FROM PUBLISHER]

Analog-to-digital converter (ADC)-based multi-Gb/s serial link receivers have gained increasing attention in the backplane community due to the desire for higher I/O throughput, ease of design portability, and flexibility. However, the power dissipation in such receivers is dominated by the ADC. ADCs in serial links employ signal-to-noise-and-distortion ratio (SNDR) and effective-number-of-bit (ENOB) as performance metrics as these are the standard for generic ADC design. This paper studies the use of information-based metrics such as bit-error-rate (BER) to design a BER-optimal ADC (BOA) for serial links. Channel parameters such as the m-clustering value and the threshold non-uniformity metric h_{t} are introduced and employed to quantify the BER improvement achieved by a BOA over a conventional uniform ADC (CUA) in a receiver. Analytical expressions for BER improvement are derived and validated through simulations. A prototype BOA is designed, fabricated and tested in a 1.2 V, 90 nm LP CMOS process to verify the results of this study. BOA's variable-threshold and variable-resolution configurations are implemented via an 8-bit single-core, multiple-output passive digital-to-analog converter (DAC), which incurs an additional power overhead of < 0.1% (approximately 50 \mu\textW). Measurement results show examples in which the BER achieved by the 3-bit BOA receiver is lower by a factor of 10^9 and 10^10, as compared to the 4-bit and 3-bit CUA receivers, respectively, at a data rate of 4-Gb/s and a transmitted signal amplitude of 180 mVppd. [ABSTRACT FROM AUTHOR]

This paper introduces and analyzes an ultra-low power and low-complexity analog IR-UWB radio system for unlicensed audio streaming which achieves continuous wave FM performance but exploiting aggressively duty-cycled signaling. At the TX, signal is modulated using a VCO which generates pulses with variable rate (PRF modulation), for an average of \sim600 kHz. At the RX an asynchronous and interference-robust detector regenerates the modulated signal at half frequency without requiring phase-locking, which is successively processed by a passive FM detector. The obtained demodulated signal is filtered using a fourth order Sallen-Key cell. The TX and RX modules based on commercial components draw 1.89 and 10 mA from 100 mAh Lithium-ion rechargeable batteries (1 \times TX and 2 \times RX) and include an integrated TX/RX chipset in a 130 nm RFCMOS technology which operates at 3.5 GHz center frequency and 1.2 V supply. The radio system transmits audio with THD <1%, provides an SNR of 64 dB (aligned with FM radio and compact cassettes) and has a frequency response 110 Hz–17 kHz, for a continuous play time of 50 h (TX) and 12 h (RX), and 2.5 m radio range. [ABSTRACT FROM PUBLISHER]

This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) for implantable medical devices. To achieve the nanowatt range power consumption, a novel switching scheme is proposed, which can accomplish the first three comparisons without consuming any energy and thus improve the energy efficiency significantly. In addition, to boost the offset performance of the comparator working under low supply voltage, a detailed theoretical analysis of comparator offset voltages is made. Based on the analysis, the comparator is optimized by only adjusting transistor sizes without any particular offset cancellation. As a result, when the common-mode input voltage varies from 300 mV to 450 mV at a 0.6 V supply, the 3\times\sigma offset voltage is optimized to be about 6 mV with a fluctuation of only 0.15 mV, as revealed by Monte Carlo simulations. A prototype of the proposed ADC was fabricated in 0.18 \mum 1P6M CMOS technology, which occupies an active area of only 380\times 430\ \mum^2. At a 0.6-V supply and 20 kS/s sampling rate, the ADC achieves an SNDR of 58.3 dB and a power consumption of 38 nW, resulting in a figure of merit (FOM) of 2.8 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

In this work we model from a system design perspective the realization of a novel mixed-signal approach to pulse width modulation (PWM). The working principle for the approach, along with an implementation scheme comprised of a digital zero-positioning (ZP) followed by a proper digital-to-analog converter (DAC) and comparator, has been introduced in a companion paper. We here focus on analyzing the global system in order to get a model of its performances in terms of dynamic range and non-linearity. Since non-linearities and quantization noise occur between the ZP and the comparator, firstly, upstream models for them are provided; then their effect on the PWM signal is calculated by means of a downstream model of perturbations at the input of an ideal natural sampling PWM. Finally, an exhaustive formula for the resulting dynamic range is given and some configurations of practical interest are proposed. [ABSTRACT FROM AUTHOR]

This paper analyzes the thermal and reference noises of two types of successive-approximation-register (SAR) analog-to-digital converters (ADCs): the time-interleaving (TI) and the partial-interleaving (PI) Pipelined. The thermal noise is investigated with accurate estimation by deriving closed-form expressions according to the noise equivalent models on different phases. Additionally, the design trade-off between power and noise for two ADC architectures is discussed in detail. On the other hand, the reference noise due to the large switching transient, which significantly degrades the conversion accuracy, is analyzed and verified through behavioral and circuit level simulations of two ADC architectures operating at 500 MS/s for 10-bit resolution. The simulated results show the supremacy of the PI Pipelined-SAR (PS) architecture over the TI-SAR because it exhibits less reference noise sensitivity. [ABSTRACT FROM AUTHOR]

This paper proposes a multi-bit incremental analog-to-digital converter (ADC) based on successive approximation (SA) for column-parallel readout circuits. The proposed ADC suppresses the random noise and enhances the resolution by embedding the conventional SA ADC with an integrator and decimation filter. In addition, the operating speed is increased through the two-step operations of coarse conversion with the proposed ADC and fine conversion with the embedded SA ADC. A residue fitting method is adopted to adjust the residue voltage to the fine conversion range after the coarse conversion. The proposed ADC with 12-bit resolution was fabricated using a 0.13 \mum CMOS image sensor process with a pixel array that has an image format of 648 \times 488 and a pixel size of 5.6\ \mum\times 5.6\ \mum. The measured results show a random noise of 108 \muV, a dynamic range of 60.9 dB, a differential nonlinearity of +1.02/-0.34 least significant bit (LSB), and an integral nonlinearity of +0.64/-0.54 LSB. [ABSTRACT FROM AUTHOR]

This paper presents an analog baseband beamforming topology, which combines phase shifting, signal combination, and biquadratic lowpass filtering in one block. This reduces the number of stages cascaded in a receiver chain, leading to a shorter signal path, thus improving the dynamic range. Flexibility of the proposed solution is illustrated with different possible implementations depending on the top-level chip floorplan. It is shown that the proposed structure does not introduce extra power consumption compared to the conventional approach, while obtaining a higher SNR. A four-antenna-path version of the proposed topology is implemented in 40 nm low-power CMOS as a prototype together with a variable gain block forming a complete analog baseband section for a phased-array receiver. The functionality includes beamforming with a resolution better than 6.8 degrees, fourth-order lowpass filtering with a 1 GHz cutoff frequency, variable gain between 10.6 and 30 dB and automatic DC offset compensation. Output IP3 above 10 dBm and output noise below 4.2 mVrms over the whole gain range yield an SFDR larger than 31.2 dB, which is sufficient for 16-QAM modulation according to IEEE 802.11ad. The circuit consumes between 30 and 42 mW. [ABSTRACT FROM AUTHOR]

This paper introduces a method for bandpass cancellation of the quantization noise occurring in high efficiency, envelope pulsed transmitter architectures-or carrier bursting. An equivalent complex baseband model of the proposed system, including the -modulator and cancellation signal generation, is developed. Analysis of the baseband model is performed, leading to analytical expressions of the power amplifier drain efficiency, assuming the use of an ideal class B power amplifier. These expressions are further used to study the impact of key system parameters, i.e. the compensation signal variance and clipping probability, on the class B power amplifier drain efficiency and signal-to-noise ratio. The paper concludes with simulations followed by practical measurements in order to validate the functionality of the method and to evaluate the performance-trend predictions made by the theoretical framework in terms of efficiency and spectral purity. [ABSTRACT FROM PUBLISHER]

Clock jitter is one of the most fundamental obstacles in realizing future generations of wideband receivers. Stringent jitter specifications in the sampling clocks of high-performance single-channel and multichannel time-interleaved analog-to-digital converters severely limit the evolution of baseband receivers. This paper presents an analytical framework for the design of clock-jitter-tolerant low-order multichannel filter-bank receivers, with techniques to dramatically lower the sampling-clock-jitter specifications. Although it is well understood that high-order frequency-channelized receivers provide higher tolerance to sampling jitter, this paper shows that low-order bandwidth-optimized multichannel receivers can achieve similar sampling-jitter tolerance. Additionally, this paper presents design tradeoffs and specifications of an example multichannel receiver that can process a 5-GHz baseband signal with 40 dB of signal-to-noise-ratio using sampling clocks that can tolerate up to 5\ \psrms clock jitter. In comparison, existing architectures based on time-interleaving require 0.5\ \psrms clock jitter for the given specifications. This extreme jitter tolerance allows for relaxed design of clocking systems, which averts a major roadblock in future wideband-communication-receiver development and provides the potential to enable several high-data-rate communication applications. [ABSTRACT FROM PUBLISHER]

This paper presents an optimization approach to single-bit quantization. The paper starts by redefining single-bit quantization as a maximum-likelihood sequence detection problem and by showing that the Viterbi algorithm is its optimal solution. It also shows that the conventional ΣΔ converter implements a greedy solution to the same optimization problem. There is, moreover, a continuum of solutions with different degrees of complexity between the ΣΔs and the Viterbi solution. The paper details one such intermediate-complexity solution (based on the M-Algorithm) and demonstrates that with an appropriate noise shaping filter it achieves a performance very close to the optimal Viterbi solution. The paper concludes by presenting two procedures for designing effective noise shaping filters. [ABSTRACT FROM AUTHOR]