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This paper presents fully integrated switched-capacitor boost-buck power converters with conversion ratios 5, 7, and 1/5. Such converters operate over a voltage range extended beyond the device ratings due to a low-voltage-stress configuration, accumulation-mode NMOS capacitors, and a circuit technique for switch bootstrapping. After modeling the simple and the symmetrical ladder converters, we determined methods for assessing the device working voltages and for optimizing the sizes of capacitors and switches. The key performance parameters were compared and the losses due to non-linear parasitic capacitances were calculated. The characterization of the prototypes in a 1.8–3.3-V, 0.18- $\mu \text{m}$ CMOS process demonstrated a 15 V range, a 5.4 mW/mm2 output power density, and good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]

In this paper, a generic, low-noise, negative-voltage generator with wide tuning range and moderate driving capacity is presented. The highly integrated solution, incorporating a fully-integrated charge-pump and a regulator block, requires only one off-chip capacitor that can be shared with the supply decoupling capacitors. The fully integrated charge-pump operation is analyzed quantitatively, and a closed-form expression of its output impedance is derived. Powered from a single 3.3-V dc input, the output has a tuning range from −4.4 to +2.1 V for biasing applications, while the design supports a maximum load current of 250, 550, and $800~\mu \text{A}$ for the regulated output voltage at −3.0, −1.5, and 1.5 V, respectively. The measured steady-state ripple is under 3 mVPP, while the noise voltage at the charge-pump operating frequency harmonics is below 130 $\mu \text {V}_{\mathrm{ rms}}$ and the noise floor is under $5~\mu \text {V}_{\mathrm{ rms}}$. The design is also the application verified with a gallium nitride power amplifier, thus further confirming its low-noise performance. Implemented in CMOS 180-nm process, the prototype chip occupies an area of 0.55 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of eight MOS transistors to control one unit capacitor, the 3-bit LSB MDAC is realized by a MOS string with four native MOS transistors to control two unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared to a Vcm-based 10-bit pure CDAC with the same unit capacitance. Under the sampling rate of 200 kS/s, the prototype 10-bit SAR ADC implemented in a 0.18- ${\mu }\text{m}$ CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes $1.76~{\mu }\text{W}$ at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/−0.21 LSB and +0.43/−0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm2. [ABSTRACT FROM AUTHOR]

This paper proposed a high efficiency boost converter targeting thermoelectric generator energy harvesting. The proposed converter adopts the critical conduction mode rather than the discontinuous mode to reduce the conduction loss, which can improve the peak efficiency at high input power. To reduce the minimum input voltage, an adaptive on-resistance switch, which can automatically change the high side and low side on-resistance according to the input voltage, is used. To maximize the output power, a maximum power point tracking circuit is designed to track the internal source resistance. Radio frequency (RF) kick-up and low voltage startup are used to improve the cold start voltage. The proposed converter is implemented in a 0.18- $\mu \text{m}$ standard CMOS process, which occupies a chip area of about 0.48 mm2. Measurement results show that the peak efficiency of the converter can be up to 90.8% and 60% at 180 and 20 mV of the open-circuit voltage, respectively. Owing to the cold startup circuit, the proposed converter can start successfully with 260-mV open-circuit voltage or −16-dBm RF input. Moreover, the open-circuit voltage can be further lowered to 12 mV with 1.5- $\mu \text{W}$ output power after startup. [ABSTRACT FROM AUTHOR]

This paper presents a novel control technique for a wide output voltage range digitally controlled SIDO boost converter. It employs minimum phase conditions reported in refid="ref1"/ , refid="ref2"/ and extends the same to SIDO boost converter to eliminate the effect of RHP zero. Further, the proposed work employs input-output linearization technique refid="ref3"/, refid="ref4"/ to linearize the control-to-output transfer function across different operating points to achieve improved stability under unbalanced loads and a wide output voltage range on each output of the proposed SIDO boost power converter. The SIDO boost regulator was verified experimentally for an input voltage of 3.3 V and a maximum simultaneous load current of 350 mA on each output. Measurement results demonstrate that the proposed design achieves a wide output voltage range of 4.8 V–13.75 V, with ability to dynamically transition across these different output voltages in both small and big voltage steps. [ABSTRACT FROM AUTHOR]

This paper presents a physics-based mathematical model for anionic memristor devices. The model utilizes Poisson- Boltzmann equation to account for temperature effect on device potential at equilibrium and comprehends material effect on device behaviors. A detailed MATLAB based algorithm is developed to clarify and simplify the simulation environment. Moreover, the provided model is used to simulate and predict the effect of oxide thickness, material type, and operating temperatures on the electrical characteristics of the device. The parameters of the proposed model are tuned and validated using experimental data of a fabricated wire based NbO1–x junction. This device is attractive for neuromorphic and computing applications, where multilevel state is desirable. The value of this contribution is to provide a framework intended to simulate anionic memristor devices using correlated mathematical models. In addition, the model can be used to explore device materials and predict its performance. [ABSTRACT FROM PUBLISHER]

In this paper the stability and sensitivity function of three basic dc-dc converter with the consideration of circuit parasitics has been analyzed for analog and digital controller implementation. The steady state and small-signal analysis has been used to derive the mathematical expressions for uniformly sampled voltage-mode controlled converters. The effect of digital controller using the ratio of sampling to carrier frequency has been analyzed. The sampling frequency limits the voltage gain in the stepped manner and also affects the stability of the digitally controlled converter. The sensitivity function has been defined for voltage gain with respect to various system parameters. The maximum affected regions on duty ratio scale with corresponding parasitic variable have been discussed. The detailed stability analysis has been carried out for digitally implemented three basic dc-dc converters, i.e., buck, boost, and buck-boost circuits. The analytical results are verified with the simulations performed in PSCAD/EMTDC. An FPGA controller is considered as digital controller for the dc-dc converter and verification of the results through experiment. [ABSTRACT FROM PUBLISHER]

This paper introduces a push-pull class-EM power amplifier for achieving low harmonic contents and high output power. By applying the push-pull configuration of the class-EM power amplifier, the proposed amplifier achieves an extremely lower total harmonic distortion (THD) and about four times higher output power than the conventional single class-EM power amplifier. Design curves of the proposed amplifiers for satisfying the class-EM ZVS/ZDVS/ZCS/ZDCS conditions are given. A design example is shown along with the PSpice-simulation and experimental waveforms for 1-MHz amplifier, considering the MOSFET drain-to-source nonlinear parasitic capacitances, MOSFET switch-on resistances, and equivalent series resistance of the inductors. The waveforms from the PSpice simulation and circuit experiment satisfied all the switching conditions, which has shown the accuracy of the design curves given in this paper and validated the effectiveness of the push-pull class-EM power amplifier. [ABSTRACT FROM PUBLISHER]

Field Programmable Gate Arrays (FPGAs) can benefit non-volatility and high-performance by exploiting Resistive Random Access Memories (RRAMs). In RRAM-based FPGAs, the memories do not only replace the SRAMs and store configurations, but they can also replace the transmission gates and propagate datapath signals. The high-performance achievable by RRAM-based FPGAs comes from the fact that the on-resistance of the memory devices R_\mathrmLRS is smaller than the equivalent resistance of a transmission gate. Efficient programming structures for RRAMs should provide high current density with a small area footprint, to obtain a low R_\mathrmLRS. In this paper, we first examine the efficiency of the widely-used 2Transistor/1RRAM (2T1R) programming structure and identify four major limitations of the 2T1R structure. To overcome these limitations, we propose a 2Transmission-Gates/1RRAM (2TG1R) and a 4Transistor/1RRAM (4T1R) programming structures. We perform both theoretical analysis and electrical simulations on the evaluated programming structures. 4T1R programming structure is the best in terms of current density with 1.4 \times and 1.1 \times as compared to 2T1R and 2TG1R counterparts, respectively. We also investigate the effect of boosting the programming voltage V_\mathrmprog of the programming structures. Experimental results show that boosting V_\mathrmprog for all the programming structures improves driving current of the evaluated programming structures by 3 $\times$ and area efficiency by 1.7 $\times$ on average. [ABSTRACT FROM AUTHOR]

A maximum-power-point-tracking DC-DC boost converter to harvest energy from sub-\muW power sources is presented. For available input-power levels below 1 \muW, voltage boosting is achieved by operating all circuits in the sub-threshold region, and by switching the DC-DC converter at tens of Hz, thereby reducing switching losses. The paper further explores the possibility of energizing the DC-DC inductor for an optimum duration, such that switching and resistive losses are minimized. The sub-\muW energy harvesting circuit uses an area of 0.2 mm^2 on a standard 180 nm CMOS process, and utilizes an auxiliary voltage source for start-up. The designed and fabricated system is more than 50% efficient when the available power is greater than 2 \muW. The circuit can harvest energy whenever the available power is more than 0.3 \muW. Efficiency at 0.3 \muW is 25%, at 0.5 \muW is 37% and at 1 \muW is 48%. The complete IC consumes 50 nA for internal operations and the input voltage can be as low as 70 mV. [ABSTRACT FROM PUBLISHER]

This paper proposes a high-efficiency zero-voltage- switching (ZVS) AC-DC light-emitting-diode (LED) driver. The structure of the proposed converter is based on a buck-boost power-factor-correction (PFC) converter. Through replacement of an output diode with a self-driven synchronous rectifier (SR), the conduction loss decreases significantly, and there is no switching loss because of the ZVS operation of the switching devices. In addition, no additional control circuit is required and cost reduction is achieved because the SR is self-driven. The efficiency of the proposed converter is higher than that of the conventional critical-conduction-mode (CRM) buck-boost PFC converter, owing to the reduced conduction loss of the high-side output rectifier and no switching loss of either of the switches. For verifying the ZVS operation and efficiency improvement of the proposed AC-DC LED driver, theoretical analysis and experimental results of a 48-[V] and 1.4-[A] prototype for LED driver are discussed. [ABSTRACT FROM AUTHOR]

A soft-switching bidirectional dc-dc converter using a lossless active snubber is proposed in this paper. In the proposed converter, zero-voltage-switching (ZVS) of main switches is achieved by utilizing an active snubber which consists of auxiliary switches, diodes, an inductor, and a capacitor. Although conduction losses associated with additional components increase, switching losses are significantly reduced due to the ZVS operation of main switches. Therefore, total efficiency is improved. Moreover, there is no reverse-recovery problem of the intrinsic body diodes of the switches. To verify the ZVS of the main switches and efficiency improvement of the proposed bidirectional dc-dc converter, theoretical analysis and experimental results from a 200 W prototype are discussed. [ABSTRACT FROM AUTHOR]

This paper presents new design procedure for a general class-E power amplifier, here referred to as quasi-class-E, with finite dc-feed inductance and switch on-resistance and variable duty cycle under variable voltage switching (VVS), and variable derivative voltage switching (VDS), taking into account the switch breakdown voltage. It is shown that for non-zero switch on-resistance in class-E power amplifier, zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions do not necessarily result in maximum efficiency. Hence, by assuming VVS and VDS, new design equations are derived. The new equations can be solved with a simple and fast numerical method in MATLAB. The theoretical results show efficiency improvement for quasi-class-E power amplifier compared to conventional designs. Circuit simulations confirm the validity of the theoretical results. [ABSTRACT FROM AUTHOR]

This paper proposes a systematic sizing methodology for switched-capacitor DC/DC converters aimed at maximizing the converter efficiency under the die area constraint. To do so, we propose first an analytical solution of the optimum switching frequency to maximize the converter efficiency. When the parasitic capacitances are low, this solution leads to an identical contribution of the switches and transfer capacitors to the converter output impedance. As the parasitic capacitances increase, the optimum switching frequency decreases. Secondly, optimum capacitor and switch sizes for maximum efficiency are provided. We show that the overdrive voltage strongly impacts the optimum switch width through the modification of their conductance. To support the sizing methodology, a model of the efficiency of switched-capacitor DC/DC converters is developed. It is validated against simulation and measurement results in 65 nm and 0.13 \mu\ m CMOS, respectively. The proposed sizing methodology shows how the converter efficiency can be traded-off for die area reduction and what is the impact of parasitic capacitances on the converter sizing. [ABSTRACT FROM AUTHOR]

Active pulse-width-modulated (PWM) voltage rectifiers are commonly used to convert ac power from a three-phase grid to a regulated dc voltage with unity input power factor. The output voltage regulation is normally achieved by an outer voltage feedback loop and a sinusoidal pulse-width-modulated (SPWM) inner current loop. Due to output voltage disturbances, such as those produced by a capacitive load, the inner current loop can be easily driven into over-modulation and possible six-step operating regions. Current research efforts have focused on extending the linearity of the modulated voltage in the over-modulation range to reduce the input current harmonics and on studying the closed-loop stability via conventional small-signal linearization around a fixed operating point. Such linear techniques obviously fall short of predicting large-signal transient stability. In this paper, catastrophic bifurcation of the three-phase voltage-source converter is reported. The physical origin of the phenomenon is identified. Boundaries of catastrophic bifurcation in the parameter space are derived. The phenomenon has been verified experimentally. [ABSTRACT FROM PUBLISHER]

This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a differential segmented capacitive digital-to-analog converter (DAC). The flash ADC controls the thermometer coarse capacitors of the DAC and the SAR ADC controls the binary fine ones. Both theoretical analysis and behavioral simulations show that the differential non-linearity (DNL) of a SAR ADC with a segmented DAC is better than that of a binary ADC. The merged switching of the coarse capacitors significantly enhances overall operation speed. At 150 MS/s, the ADC consumes 1.53 mW from a 1.2-V supply. The effective number of bits (ENOB) is 8.69 bits and the effective resolution bandwidth (ERBW) is 100 MHz. With a 1.3-V supply voltage, the sampling rate is 200 MS/s with 2.2-mW power consumption. The ENOB is 8.66 bits and the ERBW is 100 MHz. The FOMs at 1.3 V and 200 MS/s, 1.2 V and 150 MS/s and 1 V and 100 MS/s are 27.2, 24.7, and 17.7 fJ/conversion-step, respectively. [ABSTRACT FROM AUTHOR]

Total ampere-turns of the primary and secondary windings of a transformer are taken as one of variables to analyze the bifurcation behaviors and the border collision phenomenon on voltage-mode-controlled flyback converter. Six operation modes which are separated by the two borderlines of capacitor voltage and the three borderlines of total ampere-turns are obtained. A class of explicit piecewise smooth discrete-time maps with six operation modes is derived to describe the dynamics of the system. The numerical calculations are carried out, the bifurcation diagrams and the maximal Lyapunov exponent spectrums with the control period as a parameter are obtained. Then, the paper particularly analyzes the stability and existence conditions of main periodic orbits. The structure of bifurcation diagrams and the characteristics of operation modes at the border collision points are studied too. Finally, PSIM simulation and experimental results testify the validity of theoretical analysis. [ABSTRACT FROM PUBLISHER]

A two-stage hybrid power management unit (PMU) is presented with a highly-efficient novel ON-OFF LDO as the second stage and uses a switched-capacitor dc-dc divider as the first stage. The design targets IoT applications that operate across a wide range of load from sub-microwatt to 100’s of microwatts. The first stage provides a step-down using selectable sizing of its switches to improve efficiency to >95% across the target range of load current. The output voltage that is divided from the first stage is then regulated using the proposed ON-OFF LDO with a dropout voltage of < 30mV. The hybrid architecture regulates a 1.3V input to 0.4V and achieves a power efficiency of >80% for load ranges 1μ - 240μA. The design is fabricated in 28-nm CMOS technology. [ABSTRACT FROM AUTHOR]

The proposed SFE IC adopts an eight-channel H-bridge structure with an integrated voltage compliance monitoring circuit. It has stimulation current ranged from 0.78mA to 6.2mA selected by 3b control and the stimulation current level can be controlled with 7b resolution within a selected current range. The current range can be expanded by using a high current option ranged from 2.71mA to 21.7mA under 3b control. The worst DNL and INL of the stimulation current source are 0.32 LSB and 0.3 LSB, respectively, from all the current ranges. The average mismatch between the cathodic and anodic current pulses in a biphasic stimulus is measured as 0.034% without using charge balancing techniques. The voltage compliance monitoring circuit is based on triode detection of a sensing MOSFET and it shows the detection accuracy of 45mV from its measurement results. The maximum steady-state voltage across the electrodes/ solution interface (resting potential) is also rigorously analyzed and verified through bench-top and saline experiments by utilizing the proposed stimulator. The SFE IC was fabricated in $0.18~\mu \text{m}$ 24 V CMOS process. [ABSTRACT FROM AUTHOR]

The general structure of a multilevel multistate dc–dc converter is introduced, which is a hybrid between inductor-based (buck) converters and capacitor-based (switched capacitor) converters. The control of the new converter is hybrid between switched capacitor converters and buck converters, where the coarse tuning of the output voltage is achieved through the selection of an appropriate operating region similar to an SC converter, while fine tuning is achieved through the adjustment of a duty cycle value similar to a buck converter. A silicon implementation of a four-level four-state hybrid converter is presented as a specific example of the general hybrid converter structure. A new state interleaving technique was employed resulting in an increased effective switching frequency of the converter. Silicon measurements of the integrated four-level four-state converter on a 65-nm GF technology show that the converter can cover a wide range of output voltage values achieving a peak efficiency of 93% with a power density of 47 mW/mm2. The implemented converter attains a response time in the sub- ${\mu }\text{s}$ range with output voltage ripples below 50 mV. [ABSTRACT FROM AUTHOR]

In this work, we propose a physical memristor/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship. The proposed model is capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time. The developed compact model has been validated against two physical devices, fitting unipolar and bipolar switching. With no requirement of Verilog-A code, LTSpice, and Spectre simulations reproduce distinctive phenomena such as the preforming state, voltage/cycle dependent random telegraph noise and device degradation. [ABSTRACT FROM PUBLISHER]

The simultaneous switching activity in digital circuits challenges the design of mixed-signal SoCs. Rather than focusing on time-domain noise voltage minimization, this work optimizes switching noise in the frequency domain. A two-tier solution based on the on-chip clock scheduling is proposed. First, to cope with the switching noise at the fundamental clock frequency, which usually dominates in terms of noise power, a two-phase clocking scheme is employed for system timing. Second, on-chip clock latencies are manipulated to target harmonic peaks in specific frequency bands for the spectral noise optimization. An automated design flow, which allows for noise optimization in user-defined application-specific frequency bands, is developed. The effectiveness of our design solution is validated by measurements of substrate noise and conductive EMI (electromagnetic interference) noise on a test chip, which consists of four wireless sensor node baseband processors each addressing a distinct clock-tree-synthesis strategy. Compared to the reference synchronous design, the proposed clock scheduling solution substantially reduces noise in the target GSM-850 band, i.e., by 11.1 dB on the substrate noise and 12.9 dB on the EMI noise, along with dramatic noise peak drops measured at the 50-MHz clock frequency. [ABSTRACT FROM PUBLISHER]

A floating buck controlled multi-mode dimmable light-emitting diode (LED) driver that uses a stacked NMOS switch is presented, which reduces static operational current and eliminates auxiliary winding to simplify design and cost. The accuracy of the output current benefits from the use of a line-voltage compensation technique which can mitigate the effect of line-voltage fluctuation on current consistency. The proposed LED driver is implemented in 0.5 \mum 5V/40 V backend 2P2M CMOS process and occupies a die size (with pads) of 1.17\times 0.84\ mm^2. The experimental results show that the proposed LED driver achieves peak power efficiency of 95.4% across a wide range of input voltage from 85 to 264 Vac and a wide range of series-connected load LEDs from 11 to 27. The worst-case line regulation and load regulation of the output current are 0.28% and 0.25%, respectively. Measurements further show that the startup time is only 34.8 ms at 220 Vac with 50 Hz-input and multi-mode dimming can be easily implemented. [ABSTRACT FROM AUTHOR]

A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design DAC together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a built-in output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string DAC which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and resampling of the output voltages. [ABSTRACT FROM AUTHOR]

In today's process technologies, power supply noise may cause serious clock jitter and circuit malfunction. Noise occurs by the fast and simultaneous voltage switching. A primary contributor to the noise is the clock-tree and the underlying sequential circuits that switch simultaneously, thus causing high current peaks. This work proposes to spread the switching of the clock-tree drivers, while maintaining low skew at the sinks of the tree, where the clocked circuits are connected. Driver switching characterization has been used for fast computation of peak currents, delays and slopes, integrated in a two-phase algorithm. It first constructs the clock-tree in a top-down traversal, employing a mix of high threshold voltage (HVT) and weak low threshold voltage (LVT) clock-drivers. A bottom-up delay correction phase then takes place, aiming at clock skew minimization. The algorithm was implemented in 40 nanometers TSMC process technology, achieving 35% to 70% clock-tree peak current reduction, translated to similar reduction in power supply noise. The proposed method can easily be combined with other existing methods to further reduce the noise. [ABSTRACT FROM AUTHOR]

A modular compact model for memristors which describes a wide range of memristive devices is presented. Its modular structure enables the modeling of various device behaviors by adopting different functions inside the comprising blocks. Rooted from the theoretical analysis on ideal memristors, the window function of the model is uniquely based on the constitutive relationship between charge and flux. This not only solves the stability issue from previously reported models, but also reveals that an equivalent charge-flux constitutive relationship can always be obtained from a variety of memristive devices. Simulations on three types of memristive devices demonstrate that the model is able to reflect common memristive device properties such as limited memristance switching range, linear/nonlinear memristance switching rate, threshold voltages for SET/RESET, nonlinear I-V characteristics, and device parameters with variations. [ABSTRACT FROM AUTHOR]

A triple-mode step-up/step-down switched-capacitor DC-DC converter is proposed, and it can work with a wide input voltage range. There are three operational modes in the proposed converter: triple-step-up, double-step-up, and step-down modes. A built-in clock generator was designed to generate a constant switching frequency, independent of the input voltage. The proposed circuit was implemented by a 0.35-\mum CMOS mixed-signal 2P4M 3.3/5 V polycide process with a die area of 1.56\times 1.47\ mm^2. The output voltage is fixed at 3.3 V, while the input voltage range is 1.8–5 V. The maximal load current for a 1.8-V input voltage is 10 mA, while it increases to 30 mA when the input voltage is larger than 3 V. [ABSTRACT FROM PUBLISHER]

An improved zero-voltage-switching (ZVS) dc-dc converter with a high voltage gain and a ripple-free input current is proposed. It consists of two converter cells - a boost cell and an asymmetrical pulse-width-modulation (APWM) full-bridge cell. The boost cell in the proposed converter has the capabilities of providing a ripple-free input current. The APWM full-bridge cell provides a high voltage gain. The output diodes are under zero-current-switching (ZCS) during turn-off. The proposed converter has high efficiency due to soft-switching operation in full-bridge switches. Steady-state analysis of the converter is presented to determine the circuit parameters. A laboratory prototype of the proposed converter is developed, and its experimental results are presented for validation. [ABSTRACT FROM AUTHOR]

Charge balance analysis and state transition analysis are presented in analyzing hysteretic voltage mode switching converters working in the steady state. It is shown that the ideal buck converter with a current-sink load can only work in discontinuous conduction mode (DCM) but not in continuous conduction mode (CCM), and the same converter with a resistive load can work in CCM, but the output voltage ripple is very large compared to the hysteresis window. Previously published CCM designs are functional because their operations actually rely on the small but nonzero equivalent series resistance (ESR) of the filtering capacitor. For the CCM buck converter with nonzero ESR, our proposed state transition analysis gives a much more accurate switching frequency than previous approaches. The hysteretic voltage mode boost and buck-boost converters are then analyzed, and shown to have no feasible operating region. Crucial simulation results are presented to confirm the analyses. [ABSTRACT FROM PUBLISHER]