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The six-phase asymmetrical induction motors (SPIMs) are employed for high power medium voltage drive due to its attractive features of reduced stator copper loss, lower torque pulsation, higher torque per ampere, and higher reliability. In this paper, analysis of carrier-comparison-based pulse width modulation (PWM) techniques namely sinusoidal PWM and double zero-sequence injection PWM are carried out from a space vector perspective. Furthermore, new space vector pulsewidth modulation (SVPWM) techniques are developed by modifying the switching sequences of carrier-based PWM techniques. A comprehensive analysis of these PWM techniques is carried out in terms of harmonic flux trajectories, squared harmonic flux, and harmonic distortion factor (HDF). As a result, modified SVPWM technique namely 6ΦSVM3 is found superior to aforesaid PWM techniques, which significantly reduces HDF and provides lower current total harmonic distortion (THD). The experimental results of aforementioned PWM techniques are obtained and verified from six phase asymmetrical induction motor fed by dual two-level 3ΦVSIs. This paper is also accompanied by a video file of experimental test setup recorded while 6ΦSVM2 is running on SPIM. [ABSTRACT FROM AUTHOR]

This paper targets the reduction of common-mode voltage in an indirect matrix converter (IMC) through an intelligent space-vector-based modulation technique. This mode of control results in lower dV/dt at the motor terminals, thereby, reducing voltage stress to windings; and reduced output voltage distortion resulting in lower machine losses. The conventional indirect space vector pulse-width modulation method of controlling matrix converters involves independent control of either the rectifying stage or the inverting stage of the converter. However, in this paper, by suitable selection of space vectors, the rectifying stage of the matrix converter generates different levels of virtual dc-link voltage. Therefore, the responsibility of formulating output voltages with a particular magnitude and frequency, which can be translated to different machine speeds, has been transferred solely to the rectifying stage of the IMC. Estimation of the degree of distortion in the three-phase output voltage is another facet discussed in this paper, which aids the sizing and designing of output passive filters. The analysis of output voltage distortion and the proposed modulation strategies have been substantiated by simulations in MATLAB/Simulink and experimentally verified on a scaled down laboratory prototype. [ABSTRACT FROM AUTHOR]

This paper introduces a novel five-level nested neutral point piloted (NNPP) converter and analyzes the operating principle of five-level NNPP converter. This paper presents a novel space vector pulse width modulation (SVPWM) algorithm based on gh coordinate for five-level NNPP converter. First, the common-mode voltage is reduced by choosing the appropriate redundant switching states. After that, the floating-capacitor voltage balance control strategy is presented. The appropriate switch combinations of each phase are determined by the control requirements of floating-capacitor voltages respectively and the hardware mapping method of the switching states is presented. Furthermore, the neutral-point voltage balance control strategy is presented. In order to balance the dc-link capacitor voltages, the seven-segment switching sequence is selected according to the control requirements of dc-link capacitor voltages and the neutral-point voltage regulatory factor is introduced to regulate the durations of the redundant switching states in a switching cycle. Finally, the validity of the novel SVPWM algorithm with decoupling control strategies of floating-capacitor voltages and dc-link capacitor voltages is verified by the experimental results of five-level NNPP converter under steady-state and dynamic conditions. [ABSTRACT FROM AUTHOR]

This paper proposes the use of advanced bus clamping switching sequences to reduce the impedance network inductor current ripple of the three-phase Z-source inverter (ZSI). Proposed technique is named as ABC4_MCB. MCB denotes that the maximum constant boost control method is used for the voltage boosting. One of the conventional space vector pulsewidth modulation of ZSI, “ZSVM6,” is termed as ZSVM6_MCB under the maximum constant boost control method. The switching sequences of ABC4_MCB technique are designed in such a way that it offers around 34% reduction in the maximum instantaneous inductor current ripple as compared to the ZSVM6_MCB for the equal average switching frequency. The factor of percentage reduction in the inductor current ripple using the proposed technique is constant over the entire range of shoot through duty ratio (0–0.48). Theoretical findings have been verified using simulation and experimental results. [ABSTRACT FROM AUTHOR]

Parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) are widely used due to their distinct advantages of high power delivery, modularity, low current rating devices, etc. Along with these advantages, the parallel interleaved 2L VSIs could also be analyzed as a single three-level (3L) VSI. Conventionally parallel interleaved 2L VSIs are modulated using the 2L pulsewidth modulation (PWM) techniques. However, implementation of parallel interleaved 2L VSIs using the 2L PWM techniques may generate a higher ac side current ripple as compared to implementing the parallel interleaved 2L VSIs using 3L PWM techniques. This paper proposes a carrier-based method for implementing different 3L discontinuous PWM (DPWM) techniques for parallel interleaved 2L three-phase VSIs. Comparison of different 2L switching sequences for implementing a 3L DPWM switching sequence based on circulating current, line current ripple, and switching loss is also carried out. Simulation and experimental results are also displayed to validate the proposal. [ABSTRACT FROM AUTHOR]

According to different clamping methods, nine modes (C_MODE1-9) of the traditional discontinuous pulsewidth modulation (DPWM) for neutral-point-clamped three-level converter have been revealed. Since traditional DPWM cannot balance neutral point (NP) voltage under the full range of modulation index (MI) and power factor (PF), two extended modes (E _MODEs) are proposed in this paper, which can balance NP voltage. The proposed extended discontinuous pulsewidth modulation (EDPWM) is characterized by using C_MODEs and E_MODEs alternately.Therefore, EDPWM can balance NP voltage under the full range of MI and PF. Since the switching numbers under C_MODE and E_MODE in one switching cycle are two and three, respectively, the switching loss under EDPWM is lower than that under other pulsewidth modulation (PWM) strategies. The performance of EDPWM is analyzed and compared with traditional DPWM, space vector PWM (SVPWM) and virtual SVPWM (VSVPWM) in terms of switching loss, waveform quality, and the ability of NP voltage control. Finally, the feasibility and superiority of the proposed method are verified by experiments. [ABSTRACT FROM AUTHOR]

In this paper, a novel discontinuous pulsewidth modulation (DPWM) modulation strategy for a neutral-point-clamped (NPC) three-level converter (TLC) is proposed to reduce the switching loss, reduce common-mode voltage (CMV), and remove dc offset from the neutral-point (NP) voltage simultaneously, which is named as RCMV_DPWM. Based on the space vector diagram with reduced CMV, all clamping modes under RCMV_DPWM are revealed. Then, the NP voltage is controlled by selecting proper clamping mode. The realization of RCMV_DPWM is also discussed. Moreover, the performances of RCMV_DPWM are analyzed and compared with other PWM strategies in term of the NP voltage ripple, switching loss, and waveform quality. Finally, the feasibility and superiority of RCMV_DPWM are verified by experiments. [ABSTRACT FROM AUTHOR]

In several electrical dc–ac power conversions, the ac output voltage is higher than the input voltage. If a voltage-source inverter (VSI) is used, then an additional dc–dc boosting stage is required to overcome the step-down VSI limitations. Recently, several impedance source converters are gaining higher attentions [1], [2], as they are able to provide buck-boost capability in a single conversion stage. This paper proposes the merging of the boost stage and the VSI stage in a single stage dc–ac power conversion, denoted as split-source inverter (SSI). The proposed topology requires the same number of active switches of the VSI, three additional diodes, and the same eight states of a conventional space-vector modulation. It also shows some merits compared to Z-source inverters, especially in terms of reduced switch voltage stress for voltage gains higher than 1.15. This paper presents the analysis of the SSI and compares different modulation schemes. Moreover, it presents a modified modulation scheme to eliminate the low frequency ripple in the input current and the voltage across the inverter bridge. The proposed analysis has been verified by simulation and experimental results on a 2.0-kW prototype. [ABSTRACT FROM PUBLISHER]

The increasing interest in multiphase drive systems has led to the extension of inverter topologies and pulse width modulation (PWM) methods from three-phase to multiphase occasions. Carrier-based PWM (CPWM) dominates space vector PWM when the phase number increases, because of its simple computation and modular implementation. Although intensive work has been done on modifying PWM methods to reduce the common-mode voltage (CMV), not enough work has been done on CPWM methods with CMV reduction for multiphase drives. This paper extends the phase-shifted sinusoidal PWM (PS-SPWM) method for five-phase and six-phase two-level voltage-source inverters (VSI) and employs the intersection-plotting method and Fourier analysis to reveal the nature of the CMV. Both experiment and simulation results comply with theoretical analysis that compared with the conventional SPWM, the PS-SPWM can effectively reduce the CMV in peak-to-peak value and RMS value, though it leads to a higher phase current distortion. In addition, the hardware realization of PS-SPWM for multiphase inverters by a distributed control system is presented in this paper. [ABSTRACT FROM AUTHOR]

Two parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) can be analyzed as a single three-level (3L) VSI. A generalized carrier-based method is proposed in this paper for implementing different 3L pulsewidth modulation (PWM) techniques using two parallel interleaved 2L VSIs. The proposed method modifies the given three-phase reference signals of 3L VSI for implementation of the PWM technique using two parallel interleaved 2L VSIs. The influence of nonidealities on the equivalent 3L PWM switching sequences is also discussed. To overcome the effect of nonidealities, a new modified discontinuous PWM technique (MDPWM1) is proposed. The analysis of different performance indices is carried out for different 3L PWM techniques, and the key advantages of different PWM techniques are identified. Simulation and experimental results are also presented. [ABSTRACT FROM AUTHOR]

This paper proposed a novel hybrid random pulsewidth modulation (HRPWM) technique based on the modified space vector PWM for three-phase voltage source inverters to eliminate the PWM acoustic noise. Due to PWM technique and switching losses considerations, ear-piercing high-frequency noise from motor is common. The proposed HRPWM technique is able to remove the high-frequency unpleasant acoustic noise more effectively than the conventional RPWM with lower switching losses and shorter random frequency range. In addition, the PWM harmonics in phase voltage and phase current are reduced significantly. The HRPWM method is simple to implement and does not employ additional circuits in drive system. Finally, the effectiveness of the proposed approach has been confirmed by detailed experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a five-phase dual random space vector pulsewidth modulation (FPDR-SVPWM) strategy with an optimized probability density function (PDF) for a five-phase voltage-source inverter, and its performance and evaluation are also analyzed. Based on the nearest four vectors modulation method, the FPDR-SVPWM strategy, combined with random switching frequency and random zero vector, is investigated to significantly reduce the amplitude of high-order harmonics near the switching frequency and its integer multiples. For the nonsinusoidal power supply, third harmonic injection is introduced in this modulation strategy as well. Considering the effect of random numbers on the performance, an optimized Beta distribution is studied in detail. In order to analyze harmonic dispersion degree qualitatively and quantitatively, the power spectral density and the harmonic spread factor are both employed to assess the performance of the FPDR-SVPWM strategy. A series of results of simulation in MATLAB and experiments based on field programmable gate array demonstrate that the proposed modulation strategy is correct and valid, and it distributes high-order harmonics into a wide range without affecting the fundamental wave and third harmonic. [ABSTRACT FROM AUTHOR]

This paper presents new space vector pulsewidth modulation (PWM) strategies for a single-phase three-level buck-boost neutral point clamped inverter coupled with impedance-source (IS) network. These strategies can be implemented for systems with any IS network with neutral point. The case study system is based on the quasi-Z-source inverter with continuous input current. To demonstrate an improved performance, the strategies are compared with a traditional PWM strategy. The advantages lie in reduced switching number, without output voltage quality distortion. The simulation and experimental results confirm the theoretical predictions. [ABSTRACT FROM AUTHOR]

In this paper, in response to the open-circuit fault scenario in the grid-side converter (GSC) of doubly fed induction generator-based wind turbines (DFIG-WTs), a fault-tolerant four-switch three-phase (FSTP) topology-based GSC is studied. Compared with other switch-level fault-tolerant converter topologies, fewer switches, less switching and conduction losses, and simpler converter structure are derived. A simplified space vector pulse width modulation (SVPWM) technique is proposed to improve the output current quality and reduce the computational complexity in the control process. Unified expressions of duty ratios for the two remaining healthy bridge arms are obtained. In addition, the three-phase unbalance phenomenon caused by the capacitive impedance in the faulty phase is analyzed from the ac point of view, and a current distortion compensation scheme is illustrated. Furthermore, a dc-bus voltage deviation suppression strategy is proposed to maximize the dc-bus voltage utilization rate and mitigate the damage to the dc-link capacitors. Simulations are carried out in MATLAB/Simulink2017a to demonstrate the validity of the proposed SVPWM technique and compensation schemes in FSTP GSC for a 1.5-MW grid-connected DFIG-WT when different working conditions are considered. [ABSTRACT FROM AUTHOR]

In this paper, a novel space-vector pulsewidth modulation technique for a five-level active neutral-point clamped (5L-ANPC) inverter is proposed to eliminate the common-mode voltage (CMV). For the 5L-ANPC inverter, which produces a good output voltage performance and lowdv/dt, the total 125 voltage vectors can be generated, among which the proposed scheme employs only 19 voltage vectors producing a zero CMV. Due to the limitation of voltage vectors selected, the dc-link capacitor voltages of the 5L-ANPC inverter cannot be balanced by themselves. Therefore, the capacitor voltages of the inverter should be controlled by choosing the redundant switching states appropriately. The validity of the proposed modulation scheme has been verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes the new clamping angle control (CAC) pulse width modulation (PWM) method to restore its maximum linear modulation range of voltage source inverters (VSIs) reduced by the duty ratio limitation in hardware implementation, which makes the VSIs to operate nonlinearly in the high modulation range. The deadtime and the bootstrap gate driver circuit mainly cause this duty ratio limitation in practice. In particular, the bootstrap gate driver circuit is used in many industrial applications by avoiding the additional power supply to apply the gate-source voltage of power switches, and therefore making the VSIs to be small size with the low cost. First, the proposed CACPWM method is theoretically analyzed. Then, it is applied in the high modulation range to overcome the limitation of the duty ratio due to the use of the bootstrap gate driver circuit. Thereafter, its practical effectiveness is verified by both simulation and experimental tests. Also, the resulting harmonic distortions are compared with those by the conventional PWM methods. [ABSTRACT FROM AUTHOR]

This paper has focused on the novel space vector pulse-width modulation (SVPWM) strategy for the two-level three-phase inverter, which could eliminate the harmonics nearby pulse width modulation (PWM) frequency. Ear-piercing high-frequency electromagnetic noise from motor is common due to PWM technique. The proposed SVPWM is able to remove the high-frequency harmonics located nearby the PWM frequency and other odd multiples by changing the original switching states. The unpleasant acoustic noise could be removed with the novel strategy whose PWM frequency is selected near 10 kHz. By comparison, it is near 20 kHz for conventional SVPWM to achieve the similar performance. Therefore, the switching losses are significantly reduced using the novel method. Furthermore, the proposed technique neither changes the characteristics of the fundamental wave nor employs the additional circuits in the drive. At last, the effectiveness of proposed strategy is verified by simulation and experiment. [ABSTRACT FROM AUTHOR]

In this paper, various types of discontinuous space vector pulse-width modulation techniques for a three-leg voltage source inverter supplying balanced two-phase loads are proposed. The main objectives of the paper are to analyze switching loss characteristics associated with semiconductor devices and to reduce output current ripple by dealing with various types of zero space vector time in each switching sequence. Capabilities of reductions in switching losses and current ripple for both balanced and unbalanced output phase voltages at high modulation index and load power factor angle of 30° lagging are focused. The validity of the proposed techniques is verified by simulation and experimental results in terms of voltage spectrum, current waveforms, reductions in switching losses, and output current ripple at high modulation index when compared to a continuous space vector pulse-width modulation technique. [ABSTRACT FROM AUTHOR]

This paper presents a fast and generalized space vector pulse width modulation (SVPWM) scheme for any multilevel inverter. The SVPWM scheme generates all the available switching states and switching sequences based on two simple and general mappings, and calculates the duty cycles simply as if for a two-level SVPWM, thus independent of the level number of the inverter. Because the switching states, duty cycles, and switching sequences are all obtained by simple calculation in the proposed SVPWM scheme, no lookup table is needed and the scheme is computationally fast. The generalized method of generating the switching states (first mapping), calculating the duty cycles, and determining the switching sequence (second mapping) is described in this paper. The scheme is suitable for any reference vector with any modulation index, and can be conveniently extended to meet specific requirements, such as symmetric switching sequences. Compared with prior methods, the SVPWM scheme proposed in this paper provides two more degrees of freedom, i.e., the adjustable switching sequences and duty cycles, thus offering significant flexibility for optimizing the performance of multilevel inverters. The influence of redundant switching sequences in the output phase voltage of inverters is demonstrated for a nine-level inverter. This paper also thoroughly compares the proposed SVPWM scheme with prior methods. Both simulation and experimental results are given. [ABSTRACT FROM AUTHOR]

This paper presents the direct compensation of the switching interval error of the effective voltage vectors by the dead time of a pulsewidth modulation voltage source inverter (PWM-VSI). The output voltages of a three-phase PWM-VSI are distorted and have voltage errors from the dead time to avoid the shoot-through of inverter arms and the time delay of the gate drive. Voltage distortion increases the harmonics of the output voltages and decreases control performance. This paper presents a simple and direct compensation technique to solve this problem in a three-phase VSI. The practical switching output voltages are determined by the dc-link voltage, the switching signals of each phase, the dead time, the time delay, and the current polarities of each phase. For these reasons, output voltage errors are not constant. In order to analyze the dead-time effect in the actual switching voltages of each phase, the practical switching voltages in a sampling period of a space vector PWM (SVPWM) method are calculated according to the current polarity. In the calculation, the dead time, the time delay of devices, and the voltage drops on power devices are included to consider nonlinear voltage distortion. From these practical switching voltages during the switching intervals in a sampling period, the average output voltages of each phase can be derived, and the output voltage errors between the voltage commands and the average output voltages of each phase are obtained. The SVPWM switching intervals of each phase can be derived by the average output voltages that are calculated according to the current polarity and nonlinear voltage distortion to compensate for the output voltage errors. With the simple detection of the current polarity, the practical errors of the switching intervals of each phase can be compensated by the addition of the compensated switching time. Simulation and experimental results validating the proposed compensation method are presented in this paper. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) have replaced conventional two-level inverters for medium-voltage high-power industrial applications. One of the best modulation techniques for MLIs is the space vector modulation (SVM). Although SVM has its own advantages, it has been overlooked for much simpler carrier-based modulation schemes in the industry. Nearest level modulation (NLM) is a simple alternative, which is functionally similar to SVM. In this paper, a new generalized SVM algorithm is presented, in which the SVM is achieved using the concept of NLM. A generalized switch matrix is introduced to derive gate pulses for the inverter, which further simplifies the algorithm. The algorithm is tested and verified for a three-phase, three-level, and five-level neutral-point-clamped inverters in both simulation and hardware. [ABSTRACT FROM PUBLISHER]

Neutral-point (NP) voltage imbalance is an inherent problem of three-level neutral-point clamped (NPC) converter. To solve this problem, an improved virtual space vector pulse width modulation (VSVPWM) is proposed in this paper. A new repartitioning of the space vector sectors is proposed for three-level NPC converter by considering the amplitude variations of small vectors under NP voltage imbalance. The factor k of the NP voltage imbalance is introduced. The small vector favorable to the NP voltage balance is selected based on the factor k and phase current direction to achieve precise control and balancing of NP voltage. The proposed method can effectively maintain NP voltage balance and eliminate the low frequency oscillation of the NP voltage over the whole modulation index range. The improved VSVPWM also has advantages of good dynamic performance. The method has been tested and verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

Presently, the neutral-point potential offset is an inherent problem for three-level converters on three-phase four-wire active power filters. The conventional three-dimensional space vector pulse width modulation (3-D-SVPWM) strategy is adopted as a normal solution to the problem, but the selection of space vector sectors for four-wire converter is both abstract and complicated in practice. This paper proposes a new PWM strategy accordingly to simplify the selection process and the calculation of duration. Compared to the conventional 3D-SVPWM, the proposed method locates the sector of optimal vector directly with the polarity of three-phase reference voltage. Then, by applying voltage–second balance rule, it can perform a fast calculation of the duration and generate PWM signals to control the switching devices’ on/off. As an approach to correct the imbalance dc-link capacitor voltage, this strategy reconstructs the switching sequence. A portion of state O duration is disassembled into states P and N to suppress the neutral-point potential offset. The proposed strategy is validated with a range of experiments. The results indicate that this simplified PWM strategy can effectively reduce the computational burden, and also the dc-link capacitor voltage is well controlled. [ABSTRACT FROM PUBLISHER]

Loss reduction in converters is one of main targets in power electronics to obtain higher efficiency and lower thermal stress, which can enhance the lifetime of devices. This paper presents a variable switching frequency technique for switching loss reduction in a three-phase voltage source inverter, obtaining similar output current quality as that of a space vector pulse width modulation (SVPWM) algorithm. This type of optimization has not been applied for a three-phase system before. Simulation and experimental results are also shown. The output current ripple rms value of three-phase SVPWM is used as the optimization constraint. Results of the optimization of the switching losses with quality constraints in the switching frequency as the variable are presented for different load angles and compared with classical SVPWM. Experimental results show that this technique can save up to nearly $19\%$ in switching losses with similar total harmonic distortion of the output current, concluding that converter losses are reduced without reducing output current quality. [ABSTRACT FROM AUTHOR]

Space vector modulation (SVM) control of multilevel inverters (MLIs) is very popular. However, it gets extremely challenging with the increase in the number of output voltage levels due to the emergence of subtriangles in the various sectors of the hexagon, which results in increased computational complexity and storage requirements of switching states and corresponding pulse durations. Currently, this is handled through laborios offline computations in conjunction with the visual inspection of the space vector hexagon and its various sectors. This paper aims to simplify the implementation of the SVM scheme for an n-level MLI by proposing generalized equations that not only facilitate direct online computation of control pulses and obviate the requirement of lookup tables but also result in optimized switching. Yet, the on-time computations of the various MLI switches are still based on simple two-dimensional Cartesian co-ordinate system combined with the basic two-level inverter implementation. The proposed scheme makes use of a unique l-factor approach, which directly identifies the location of the various subtriangles in the space vector hexagon and leads to direct online computations of the control pulses. The proposed scheme is validated by simulations and experimental results for three- and five-level diode clamped MLI. [ABSTRACT FROM AUTHOR]

In high-power traction drive systems, the switching frequency of the inverter is strictly limited owing to the restrictions on switching losses and cooling conditions. In this case, the multimode modulation strategy is usually adopted. Based on the analysis of a modified 24-sector space vector pulse width modulation (SVPWM) technique, several synchronous modulation strategies with different pulse numbers are proposed in this paper, which can be applied to the two-level six-phase voltage-inverter-fed asymmetrical dual-stator induction machines. By comparing the harmonic performance of the synchronized modulations, the authors present a set of multimode SVPWM strategy, which is suitable for the high-power traction drive systems under low switching frequency. At the same time, the switching strategy for transitions between different modulation modes is proposed as well. Simulation and experimental results verify the validity and effectiveness of the proposed synchronized modulation strategies and the switching strategy between different modulation modes. [ABSTRACT FROM AUTHOR]

Several pulsewidth modulation (PWM) strategies have been proposed for three-phase multilevel converters. Typically, these PWM methods can be either space-vector or carrier-based implemented, where the carrier-based implementation usually presents a lower computation complexity. In this paper, a novel approach for the carrier-based implementation of different existing PWM methods is proposed for three- (3L) and four-level (4L) dc–ac converters, which can be easily extended to any number of levels. The main features of the proposed approach are its reduced computation complexity and computation time. On the other hand, the proposed approach suggests the derivation of novel PWM strategies which can potentially present improved performance features. As an example, two new discontinuous PWM (DPWM) strategies are proposed for the 4L converter. One of these DPWM strategies presents lower weighted total harmonic distortion than other previously proposed strategies. Simulation and experimental results verify the effectiveness of the proposed approach and novel DPWM strategies. [ABSTRACT FROM AUTHOR]

This paper presents a generalized algorithm to eliminate spikes of common-mode voltages (CMV) caused by dead-time effect for common-mode voltage reduction pulse width modulation (CMVRPWM). The characteristics of the CMV spikes for the popular CMVRPWM strategies (AZSPWM1, NSPWM, CRLO-CMVRPWM, and SLO-CMVRPWM) are studied and compared by analyzing the extreme switch pulse patterns. The proposed CMV spikes elimination method directly adjusts the injected zero-sequence voltages instead of the durations of the adopted voltage space vectors to avoid the overlaps of the adjacent dead time periods. The CMV spikes can be eliminated regardless of the output voltages in the dead time periods; thus, the signs of phase currents are not needed to detect and overcome the problem caused by the resolution of the current sensors when the phase currents approach to zero. In addition, an effective method by online selecting low or high active pulses for the three legs is proposed to ensure that at most one leg switches between adjacent carrier periods. The proposed method is generalized and effective for all the CMVRPWM with symmetrical switch pulse patterns and no simultaneous switching problem. The simulation and experimental results validate the effectiveness. [ABSTRACT FROM AUTHOR]

Five-phase fault-tolerant permanent-magnet motors incorporate the merits of high-efficiency and high fault-tolerant capability. By adopting the fault-tolerant control technique, these motors can continue operating even fault occurs. This paper proposes two space vector pulse-width modulation (SVPWM) control strategies, namely the symmetric one and the asymmetric one. The novelty of the proposed SVPWM control strategies includes two parts. One is that voltage vector locations in both SVPWM strategies are reconfigured based on a new vector space diagram. Another is that the process of switching vector calculation under fault is similar to that under healthy condition. A five-phase fault-tolerant permanent-magnet motor drive is developed and the proposed fault-tolerant control strategies are evaluated in terms of the torque, voltage, current waveforms, and total harmonic distortion. Simulated and experimental results are provided to verify the effectiveness of the theoretical analysis. [ABSTRACT FROM AUTHOR]

A four-level open-end winding induction motor (OEWIM) drive is known to suffer from two perennial problems. One is the problem of zero-sequence currentin the motor phases, which is caused by the existence of zero-sequence voltage in them. The other is the overcharging of the dc-link capacitor of theinverter operated with lower dc-link voltage by its counterpart operated with a higher dc-link voltage. This paper investigates the applicability of aspecial variant of space vector pulse width modulation (SVPWM) scheme for a recently proposed power circuit configuration, in which arectifier–inverter combination is nested within the conventional two-level inverter configuration to achieve four-level inversion. This PWM schemeis named as the sample-averaged zero-sequence elimination (SAZE) SVPWM scheme, wherein the zero sequence voltage is suppressed in each sampling timeperiod in the average sense. Both of the aforementioned problems encountered in this drive are successfully overcome for this power circuit configurationby resorting to the proposed SVPWM strategy. [ABSTRACT FROM PUBLISHER]

This paper presents a new space vector pulsewidth modulation scheme to reconstruct phase currents using neutral-point current sensing in three-level T-type converters (TLTTCs). For this purpose, zero vector and offset vectors are replaced with complementary active vectors. These active vectors do not affect the resultant output voltage and the voltage balance at the neutral point of TLTTCs. Hence, the pulsewidths of corresponding active vectors can be adjusted even at low speeds without much additional switching losses and low-frequency noise in the inverter. The modified switching patterns can easily be generated without significant computational complexity. The proposed method is experimentally verified using Texas Instruments TMS320F28335 and Spartan 6 controllers, on a custom designed T-type converter based on Fuji IGBT modules. [ABSTRACT FROM PUBLISHER]

The most recent literature on multiphase machine drives is based on voltage-source converter (VSC) systems utilizing different modulation techniques. Very little attention is given to the multiphase current-source converters (CSCs). Applying CSCs in high-power multiphase drive systems is promising and can effectively solve many technical problems associated with conventional VSC-based systems. This paper proposes a space vector pulsewidth-modulation (SVPWM) scheme suitable for a five-phase CSC. Generally, in SVPWM-CSCs, a current path should be provided for the dc-link current by ensuring that one pair of upper and lower switches is always on. Applying this constraint yields 25 different space vectors, which are mapped into two concentric decagons with ten equal sectors in the $\alpha\beta$ and $xy$ sequence planes. Each sector has two active-large vectors, two active-small vectors, and a null vector. Moreover, the active-large vectors in the $\alpha\beta$ plane are active-small vectors in the $xy$ plane, and vice versa. In the proposed scheme, the ampere-second concept is utilized to determine the ratio between the dwelling times of the large and small vectors such that the $xy$ current components are nullified, the utilization of the input dc-current is maximized, and the switching transitions are minimized, which, in turn, minimizes the CSC switching losses. The proposed scheme can effectively provide sinusoidal converter currents, which is suitable for motor drives and energy conversion applications. The proposed scheme is verified using a 1-kW prototype five-phase induction motor fed by a five-phase CSC. [ABSTRACT FROM PUBLISHER]

In this paper, three overmodulation techniques for the three-to-five-phase indirect matrix converter (IMC) are proposed. The first technique utilizes only the adjacent large vectors in the sector in which the reference output voltage vector lies. The second technique improves on that by continuously adapting vector elimination in the d_2-q_2 vector space based on the output voltage requirements. The third technique utilizes the ripple in the dc link to further reduce the modulation index of the inverter stage during overmodulation. All three techniques increase the voltage transfer ratio of the three-to-five-phase IMC from 0.788 to 0.923, but with the addition of harmonics generated by a vector in the d_2-q_2 vector space of the inverter stage. Simulation and experimental results from a prototype three-to-five-phase IMC validate the three proposed overmodulation techniques. [ABSTRACT FROM AUTHOR]

This paper proposes a three-phase isolated bidirectional ac/dc converter. The converter achieves buck–boost ac/dc bidirectional conversion, sinusoidal ac current, and high-frequency electrical isolation with single-stage structure. The traditional SVPWM algorithm should be modified to keep the voltage–second balance of the transformer. The circuit derivation, operation principles, and SVPWM algorithm are presented specifically. The solution for shoot-through problem is proposed, which does not need extra dead time. To verify the theoretical analysis, the proposed converter was simulated by MATLAB/SIMULINK and a 3 kW prototype was built in the lab. The simulation and experimental results show the high power factor and the low harmonic distortion characteristics of the circuit. [ABSTRACT FROM AUTHOR]

Multilevel converters have been well studied for high-voltage high-power renewable energy applications. Owing to the multibranch structure, these converters can be operated under fault conditions in case of a loss of a branch or voltage cell. In this regard, this paper proposes a new active fault-tolerant space vector pulsewidth modulation strategy for single-phase faults in three-phase multilevel converters. The proposed modulation strategy treats the multilevel converter as a two-level converter by introducing an offset vector. A generalized approach is proposed to search for the offset vector and to adjust the modulation of the converter online under different fault operation conditions. Several short- and open-circuit faults have been demonstrated on a seven-level hybrid input-switched converter to prove the effectiveness of the proposed fault-tolerant scheme. [ABSTRACT FROM PUBLISHER]

This paper presents a six-phase current reconstruction scheme for dual traction inverters in hybrid electric vehicles (HEVs) with a single dc-link current sensor. During the phase current reconstruction, one of the inverters is proposed to operate using active vectors, whereas the other inverter operates using nonactive vectors. An advanced phase-shift scheme for all pulsewidth-modulated (PWM) signals based on the sequence of duty cycles is implemented. PWM signals are considered in three types: large, medium, and small duty cycles. Then, the minimum phase-shift scheme is applied to each type of PWM signal to ensure the minimum duration of the active vector for stable current reconstruction. With this proposed phase-shift scheme, the maximum allowable modulation index and dc-link voltage utilization are improved. In addition, the relationship between the minimum required time for stable phase current reconstruction and the maximum allowable modulation index is derived theoretically. The effectiveness of the proposed method is verified by both simulation and experimental results. With this scheme, cost and volume of dual inverters in HEVs are reduced, considering the lower number of current sensors. [ABSTRACT FROM PUBLISHER]