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A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]

In this paper, performances on two kinds of aggregated flyback microinverters are compared in aspect of harmonic resonances, which are controlled by current feedback control and peak current control. Based on the Norton models of flyback microinverters obtained by a small-signal modeling approach, potential harmonic resonances with the grid are analyzed. Following that, an impedance-based stability criterion is proposed, where the resonance frequency can be calculated and predicted based on the derived Norton models and the system admittance matrix of aggregated microinverters. After comprehensive analysis and comparisons, it is found that the peak-current-control-based flyback microinverters has better performance on damping the harmonic resonances than the current feedback controlled one. Simulations and experiments are carried out for verifying the effectiveness of the presented models and the correctness of the analysis results. [ABSTRACT FROM AUTHOR]

In this paper, a novel space-vector pulsewidth modulation technique for a five-level active neutral-point clamped (5L-ANPC) inverter is proposed to eliminate the common-mode voltage (CMV). For the 5L-ANPC inverter, which produces a good output voltage performance and lowdv/dt, the total 125 voltage vectors can be generated, among which the proposed scheme employs only 19 voltage vectors producing a zero CMV. Due to the limitation of voltage vectors selected, the dc-link capacitor voltages of the 5L-ANPC inverter cannot be balanced by themselves. Therefore, the capacitor voltages of the inverter should be controlled by choosing the redundant switching states appropriately. The validity of the proposed modulation scheme has been verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) is known as a major cause of premature motor failures. The form and amplitude of the CMV generated by any converter depends on both the circuit topology and modulation technique. Among single stage ac–ac converters employed in drive applications, the Z-source ultra sparse matrix converter (ZSUSMC) is a desirable choice due to reduced number of switches in its structure and voltage boosting capability. Based on these considerations, this paper aims to: 1) theoretically determine and compare the CMV of the ZSUSMC with four well-known impedance networks, namely, cascaded, switched-inductor, quasi, and series, in its structure and 2) propose modulation techniques for CMV reduction in the ZSUSMCs. To this end, first, it is shown that the ZSUSMC, depending on the impedance network used in its structure, provides more freedom to choose from redundant switching states compared to the ultra sparse matrix converter. Then, by taking advantage of this feature, novel modulation strategies that attenuate the CMV without affecting the boosting capability are developed. The proposed modulation schemes are based on avoiding the switching states most contributing to the CMV during a switching period. Through hardware-in-the-loop studies, the effectiveness of the proposed modulation strategies in reducing the CMV of the ZSUSMCs is verified. [ABSTRACT FROM AUTHOR]

In voltage-source inverters (VSIs), dead time is used to prevent shoot-through over switching devices. However, the existence of the dead time will distort the output phase current, which degrades the performance of the inverter as well as influences the common-mode voltage (CMV), particularly in CMV elimination relevant modulation schemes, such as zero-common-mode (CM) pulsewidth modulation (PWM)-based paralleled inverters. In the light of the situation that the normal sampling-based dead-time compensation (DTC) methods are often disturbed by the current ripple, this paper introduces a novel DTC method for the VSI, which can mitigate the impact of the current ripple and improve the accuracy of DTC. The proposed method deduces the real-time current ripple, which can reconstruct the actual trajectory of phase-leg currents, and the peak values corresponding to rising and falling edges for PWM signals can be predicted. In this way, DTC can be implemented based on the direction of relevant instantaneous switching currents and finally improves the accuracy. Especially, the current-ripple-prediction-based DTC can help to improve the CMV distortion caused by the dead time for paralleled inverters with zero-CM PWM. Simulation and experimental results are provided to validate that the proposed method can be applied to different topologies and modulation schemes with good performance. [ABSTRACT FROM AUTHOR]

The three-phase four-wire inverter with split dc-link capacitors can supply unbalanced loads. For the purpose of reducing the filter inductors, a neutral inductor could be introduced into the neutral line. This paper analyzes the operation principle of the three-phase four-wire inverter with split dc-link capacitors when a neutral inductor is introduced. It is illustrated that the neutral inductor can reduce the zero-sequence switching harmonics in the voltages between the phase-leg midpoints and the output neutral point, thus the filter inductors can be reduced. The optimized design of the neutral inductor and filter inductors is proposed with the considerations of the inductor current ripple, the ability of supplying unbalanced loads, and the total energy stored in the inductors. The equivalent circuits of the three-phase four-wire inverter with split dc-link capacitors and neutral inductor is derived in the α–β–0 frame, and the zero-axis voltage regulator is modified to suppress the third-order harmonic in the zero-sequence current caused by the deadtime of the drive signals for the power switches. Finally, the experimental results from a 9-kW prototype are provided to prove the effectiveness of the proposed optimized design of the neutral inductor and filter inductors and the control strategy of the inverter. [ABSTRACT FROM AUTHOR]

In this paper, a modified selective harmonic mitigation pulse amplitude modulation (SHM-PAM) is presented to be capable of canceling all triplen harmonic orders and suitable for single-phase application of five-level type of voltage source inverters. To this end, a new constraint is established for the two switching angles (α1, α2) to derive the new formula for the harmonics’ amplitude, which results in self-elimination of all triplen harmonics (e.g., 3rd, 9th, 15th, …). The fifth and seventh harmonic orders are mitigated through normal operation of the proposed SHM-PAM technique. It is also shown that the proposed technique is extendable to other multilevel voltage waveforms and a flowchart of self-elimination of all triplen harmonics has been presented. Mathematical analysis supported by experimental investigations show the desired performance of the proposed SHM-PAM algorithm on a two-cell single-phase cascaded H-bridge inverter as a typical five-level configuration in dealing with linear and nonlinear loads. Then, it is demonstrated that the maximum number of harmonic orders would be controlled with the minimum number of available angles in a low switching frequency voltage waveform. [ABSTRACT FROM AUTHOR]

This paper proposes a transformerless line-interactive uninterruptible power supply (UPS) with low ground leakage current. A high-efficiency bidirectional inverter is suggested, which performs the line-interactive UPS functions with low ground leakage current. It has a full-bridge inverter and a bidirectional switch, which operate with the unipolar pulsewidth modulation. Because the bidirectional switch operates at the line-frequency, switching losses can be lower than the previous transformerless inverters. As the inverter operates, the parasitic capacitance between the inverter and the ac voltage ground is clamped to zero voltage for a positive line cycle and to the ac voltage for a negative line cycle, respectively. Thus, the parasitic capacitance can be prevented from being charged or discharged, which ensures the absence of the ground leakage current. The operation modes of the proposed system are described. The control schemes are presented to design the proposed inverter for the line-interactive UPS. Experimental results for a 2.0 kW prototype are discussed to verify the performance of the proposed system. [ABSTRACT FROM AUTHOR]

This paper proposes a new diode-clamped multilevel inverter that can effectively balance the voltages of dc capacitors. For the proposed inverter, the inductors are inserted between the diodes and the main switches. Also, the voltage balance of the dc capacitors can be guaranteed by controlling the opening time of the corresponding main switches in particular modes. Thus, the parallel circuits on the dc side in the conventional inverters are canceled. Consequently, the proposed topology requires fewer switches, diodes, and capacitors, although it adds the compensation currents to the corresponding main switches. Both the simulation and experimental results demonstrate the suitability and applicability of the proposed topology. [ABSTRACT FROM AUTHOR]

In this paper, a novel space vector modulation (SVM) strategy is proposed and designed for dual three-phase three-level motor drives based on vector space decomposition (VSD), which could be applied for high-power and high-reliability applications. The key of the proposed method is to design two decoupled groups of voltage vector candidates for synthesis on α − β subspace and x − y subspace, respectively. The two decoupled groups of voltage vectors will synthesize respective voltage references on α − β subspace and x − y subspace, while having no impact on each other. The redundant small voltage vectors and zero-sequence voltage vectors are utilized to mitigate voltage oscillation in midpoint of dc link and suppress zero-sequence current component for dual three-phase windings with a common neutral. For comparison, another VSD-SVM strategy is designed based on traditional solution, which cannot offer closed-loop control on x − y subspace. Both simulation and experiments have been given to verify that the proposed decoupled VSD-SVM can suppress harmonic components on x − y subspace besides tracking torque components on α − β subspace. Furthermore, the harmonic performance of the proposed decoupled VSD-SVM has been compared with the traditional VSD-SVM strategy and the carrier disposition based pulsewidth modulation. [ABSTRACT FROM AUTHOR]

Although high-frequency circulating current exists in parallel-operated inverters, it has not attracted as much attention as low-frequency circulating current, and thus has not been analyzed in detail previously. In this paper, a mathematical model and analysis are presented, which reveal the spectrum components and their changing trends of the circulating currents caused by carrier phase differences. The impact of carrier phase difference on high-frequency circulating current is also analyzed and verified. A closed-loop control scheme is proposed to suppress the switching frequency circulating current caused by carrier phase difference. In addition, the deadbeat and closed-loop control are combined to suppress the low- and high-frequency circulating currents simultaneously, to improve the overall performance of circulating current suppression. The effectiveness of the proposed scheme is verified by the simulation and experimental results acquired from a laboratory platform. [ABSTRACT FROM AUTHOR]

This paper proposes a control method for a five-level hybrid flying-capacitor (5L-HFC) inverter, of which structure stems from the conventional five-level active neutral-point-clamped (5L-ANPC) topology by dividing the dc-link stage into three series-connected capacitors. In this inverter, the voltage stress on the power switches connected to the dc link is reduced by a half compared with that of the 5L-ANPC topology, thus the lower number of equally voltage-rated power devices can be employed. Also, the power losses in the 5L-HFC inverter are more evenly distributed than in the 5L-ANPC. In order to balance the dc-link capacitor voltages, a third-order harmonic offset injection is applied. When a diode rectifier is used to supply the dc bus voltage, the balancing method is not effective if the modulation index is higher than 0.64. Thus, an auxiliary circuit is needed to support the balancing of the dc-link capacitor voltages. However, the unbalancing problem can be overcome in a full-range operation without the auxiliary circuit if the back-to-back configuration is utilized. Finally, simulation and experiment results have verified the performance of the 5L-HFC inverter with the proposed control method. [ABSTRACT FROM AUTHOR]

This paper proposes the new clamping angle control (CAC) pulse width modulation (PWM) method to restore its maximum linear modulation range of voltage source inverters (VSIs) reduced by the duty ratio limitation in hardware implementation, which makes the VSIs to operate nonlinearly in the high modulation range. The deadtime and the bootstrap gate driver circuit mainly cause this duty ratio limitation in practice. In particular, the bootstrap gate driver circuit is used in many industrial applications by avoiding the additional power supply to apply the gate-source voltage of power switches, and therefore making the VSIs to be small size with the low cost. First, the proposed CACPWM method is theoretically analyzed. Then, it is applied in the high modulation range to overcome the limitation of the duty ratio due to the use of the bootstrap gate driver circuit. Thereafter, its practical effectiveness is verified by both simulation and experimental tests. Also, the resulting harmonic distortions are compared with those by the conventional PWM methods. [ABSTRACT FROM AUTHOR]

Parallel inverters are commonly adopted in high-power applications, for instance wind energy systems, smart transformers, and power conditioners. Meanwhile, interleaved pulse width modulation is usually considered as an optimal approach to reduce the current ripple and harmonics of the parallel inverters. However, in the case of a common dc link, the problem of circulating current emerges and leads to performance degradation. This paper aims at investigating the influence of different modulation techniques on the circulating current of two neutral-point-clamped (NPC) inverters under interleaved operation. Two modulation techniques, phase disposition (PD) and alternative phase opposite disposition (APOD), have been studied and compared in terms of current ripple, spectrum quality, and circulating current. Though the PD modulation was regarded as the optimum solution in most of the single-NPC cases, it offers worse performance in the two parallel NPC applications due to higher circulating current. Simulation and experimental validations are provided and show that the APOD leads to much lower circulating current and similar current ripple as well as spectrum quality compared to the PD. [ABSTRACT FROM AUTHOR]

This paper presents a new least-mean-square (LMS) algorithm based deadtime compensation method to suppress the current distortion in permanent-magnet synchronous motor (PMSM) field-oriented control (FOC) drives. Compared to conventional average value compensations, the proposed method is robust to switching device parameter variations thanks to the online adaptation capability of the LMS algorithm. Similarly, the disturbance observer compensators are also immune to switching device parameter variations; however, varying motor parameters degrade their compensation performance. Without prior knowledge of switching device or motor parameters, the proposed method can directly reduce the deadtime current harmonics by generating compensation voltage references. In addition, the proposed method is easy to implement since it does not require voltage errors estimation or current harmonics extraction, which are necessary for disturbance observer and adaptive filter based methods. The proposed method is tested on a 2.5-kW voltage-source inverter PMSM drive controlled by an FOC algorithm. Its effectiveness is validated by both experimental results and spectrum analysis. [ABSTRACT FROM AUTHOR]

An adaptive control of DPWM implementable in clamped-three-level inverters with two strings of photovoltaic (PV) panels in cascaded connection is proposed in this paper. The proposed modulation is developed based on the so-called circuit-level decoupling concept. It is able to provide balance line voltage even under unbalanced dc links. The unequal dc voltages appeared due to asymmetric maximum point of power trackings (MPPTs) are controlled by proper injection of zero-sequence voltage to the common mode voltage, while the total dc voltage is regulated based on the voltage commands generated by the MPPT of each string. Thus, both PV strings are able to be operated based on their MPPTs while there is almost no low-order harmonic distortion at the inverter output current. Compared with the previous methods, the high capability of the proposed method is evaluated by simulation study and experimental tests. [ABSTRACT FROM AUTHOR]

This paper presents an improved analytical model for estimating the high-frequency current ripple of interior permanent magnet synchronous machines due to pulsewidth modulation (PWM) switching. The proposed model accounts for the impact of slotting effect, magnetic saturation, and cross-coupling between the $d$ - and $q$ -axis. The model is subsequently used to investigate several factors that influence the PWM-induced current ripple. These include the PWM switching frequency, fundamental frequency (i.e., machine speed), dc-bus voltage, current control angle (i.e., γ angle), and the excitation current amplitude (i.e., saturation level). Experiments have been conducted to verify the analytical prediction results. These results show that the analytical model can predict the PWM-induced current ripple waveshape very well for many operating conditions and accurately estimate its rms value over a complete fundamental period. [ABSTRACT FROM AUTHOR]

Inverter dead-time is known to make open-loop induction motor drives oscillatory, while operating at light-loads in particular. While dead-time compensation schemes exist, precise compensation of the same is often challenging as it involves factors such as device and driver delays and switching transition times, which are difficult to be quantified accurately. Hence, the effect of dead-time could be under or overcompensated. This paper presents a comprehensive analysis of the impact of such undercompensation and overcompensation on the stability of a 100-kW induction motor drive, along with experimental investigations of the same. The effects of undercompensation and overcompensation on the inverter output voltage are analyzed on a switching-cycle average basis. Further, small-signal models are proposed for an open-loop drive, when it is undercompensated and overcompensated. Stability analysis of the above motor drive is reported, which predicts oscillatory behavior with both under and overcompensation, over certain fundamental frequency ranges, respectively. Further, two different types of oscillatory behavior, characterized by different oscillating frequencies, are observed for the cases of under and overcompensation. The analyses are supported by simulations. Experimental investigations carried out also support the analyses and simulation results. [ABSTRACT FROM AUTHOR]

Inductive power transfer (IPT) for battery charging applications has significant advantages over the traditional plug-in system. Since misalignment between the primary and secondary windings is inevitable, it is of significance to improve the misalignment tolerance of IPT systems with constant-current (CC) and constant-voltage (CV) outputs for battery charging. In this paper, the load-independent output characteristic of the hybrid topology and the function switching between CC and CV of the reconfigurable topology are analyzed. Besides, a hybrid and reconfigurable IPT system with 3-D misalignment tolerance for CC and CV outputs is proposed, simplifying or even canceling control schemes. Moreover, a novel parametric design method is given for the IPT system, which can suppress the fluctuation of the output voltage/current within a certain range of misalignment. In order to validate the performance of the proposed topology, a 1-kW prototype is built, and the corresponding experiments are carried out. In the CC/CV mode, the system can operate with the longitudinal misalignment to 50% when the load varies from 36 to 480 Ω, and the fluctuation of the output current/voltage is within 5%. Similarly, the misalignment in Y- and Z-axis is 12.5% and 33.3%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a novel three-phase DC-link multilevel inverter topology with reduced number of input DC power supplies. The proposed inverter consists of series-connected half-bridge modules to generate the multilevel waveform and a simple H-bridge module, acting as a polarity generator. The inverter output voltage is transferred to the load through a three-phase transformer, which facilitates a galvanic isolation between the inverter and the load. The proposed topology features many advantages when compared with the conventional multilevel inverters proposed in the literatures. These features include scalability, simple control, reduced number of DC voltage sources, and less devices count. A simple sinusoidal pulse-width modulation technique is employed to control the proposed inverter. The performance of the inverter is evaluated under different loading conditions and a comparison with some existing topologies is also presented. The feasibility and effectiveness of the proposed inverter are confirmed through simulation and experimental studies using a scaled down low-voltage laboratory prototype. [ABSTRACT FROM AUTHOR]

Owing to low cost, small size, and low weight, transformerless inverters became prominent in single-phase grid connected photovoltaic (PV) systems. Key issues pertaining to these inverters include suppression of common mode (CM) leakage current and improvement of conversion efficiency. Achieving higher efficiency in single-phase grid-connected photovoltaic systems depends on the number of stages involved in feeding power to the grid, predominantly, if the PV array voltage is less than the peak value of the grid voltage. In this paper, an integrated dc–dc converter based grid-connected transformerless PV inverter is proposed which is aimed at maintaining high efficiency, even if the PV array voltage falls below the peak value of grid voltage (efficient operation at an extended input voltage range). A modulation strategy is discussed in order to minimize the flow of CM leakage current. Further, the efficiencies of certain transformerless inverter topologies are analyzed and compared with that of the proposed topology. Detailed simulation studies are carried out in MATLAB/Simulink environment to verify the analysis. Experimental results for a scaled down laboratory prototype are included as a proof-of-concept to validate the claims. [ABSTRACT FROM AUTHOR]

In this paper, a modular control approach has been proposed for a single- and three-phase differential-mode Ćuk inverter (DMCI) operating with a recently proposed discontinuous-modulation scheme that offers tangible performance benefits over conventional continuous modulation scheme. The modular control scheme uses a combination of a transformation and adaptive control law to meet tracking requirements in the presence of converter nonlinearity. Experimental results for the single- and three-phase DMCI are provided for startup, steady state, load transition, and total harmonic distortion using different types of loads, which validate the efficacy of the implemented modular tracking controller. Further, detailed stability of the closed-loop DMCI module is provided. [ABSTRACT FROM AUTHOR]

This paper investigates a multilevel inverter composed of series/parallel-connected H-bridges. The presented structure can be used for applications in which the use of semiconductor switches with low-voltage and low-current ratings is intended. A comprehensive system model, an overall control strategy to adjust the output voltage with constant magnitude and frequency, and a level-shifted PWM (LS-PWM) strategy based on a voltage vectors unidimensional analysis and a plane analysis are presented. The LS-PWM is capable of mitigating the low-frequency circulating current, thus generating multilevel voltage signals with low harmonic distortion, maximum number of levels, and low dv/dt. In addition, considering a wide range of values of voltages and currents and various power levels, the total converter losses are reduced compared with the conventional multilevel converters. Two multilevel conventional inverters with the same number of semiconductor switches are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. [ABSTRACT FROM AUTHOR]

The requirements for peripheral circuits of power converters are becoming more restrictive due to the enhancement of Si-based power devices and due to practical use of SiC device. In the design of modern high-speed switching converters, the stray inductances and capacitances both in the device package and in the gate drive circuit in addition to those in the main circuit of the power converter must be considered. In these situations, the gate driving technique represents the key technology for enhancement of high-speed switching ability of power devices, as there are design limitations to reduce the stray inductances and capacitances. So far, several active gate control methods have been proposed. Most conventional active gate drivers are configured using analog circuits such as transistors and diodes. Thus, it is difficult to reconfigure their control parameters to fit the stray inductances and capacitances after the implementation of power converter and gate circuits. As a solution to these problems, the authors have proposed a programmable gate driver IC, which is a digitally controlled circuit. This gate driver IC can control the gate current at 63 separate levels, operated by programmable fully digital 12-bit and clock signals. In this paper, an active gate current control based on the load current in a half-bridge inverter with two programmable gate driver ICs is demonstrated. This developed gate control is different to the general current feedback control followed the reference value. It is verified that the proposed active gate control can effectively improve the tradeoff relationship between the surge voltage and switching loss of the pulsewidth modulation half-bridge inverter circuit. [ABSTRACT FROM AUTHOR]

This paper proposes new angles constraint for selective harmonic elimination-pulsewidth modulation (SHE)-PWM utilized in single-phase inverter applications. The proposed angles constraint naturally eliminates all triplen harmonics, whereas they conventionally appeared in all single-phase output voltages. The harmonic amplitude formula is developed based on the obtained angles constraint, and then modified single-phase SHE equations are defined to eliminate only specified low nontriplen harmonics. Therefore, more harmonics would be eliminated with the same switching frequency in modified SHE-PWM. Five-level voltage waveform has been opted to implement the introduced method, but it can be applied on all multilevel voltage waveforms such as seven-level with even number of angles. Unlike the conventional SHE technique, THD is analyzable in modified SHE to find optimum values for switching angles in order to control noneliminated harmonic amplitudes and minimize THD. Moreover, the cancellation of triplen harmonics empowers a single-phase inverter to supply nonlinear loads beside linear ones. Some experimental tests are accomplished using a single-phase five-level modified packed U-cell (MPUC) inverter. Results are discussed to prove the excellent performance of a single-phase MPUC inverter under both normal and harmonic loads and accurate elimination of determined triplen and nontriplen harmonics by applying the presented angles constraint. [ABSTRACT FROM AUTHOR]

In order to prevent the power switching devices (e.g., an insulated-gate bipolar transistor, IGBT) from shoot-through in voltage-source converters during a switching period, the dead time is added either in the hardware driver circuits of the IGBTs or implemented in software in pulse width modulation (PWM) schemes. Both solutions will contribute to a degradation of the injected current quality. As a consequence, the harmonics induced by the dead time (referred to as “dead-time harmonics” hereafter) have to be compensated in order to achieve a satisfactory current quality, as required by standards. In this paper, the emission mechanism of dead-time harmonics in single-phase PWM inverters is, thus, presented considering the modulation schemes in detail. More importantly, a repetitive controller has been adopted to eliminate the dead-time effect in single-phase grid-connected PWM converters. The repetitive controller has been plugged into a proportional-resonant-based fundamental-frequency current controller so as to mitigate the dead-time harmonics and also to maintain the control of the fundamental-frequency grid current in terms of dynamics. Simulations and experiments are provided, which confirm that the repetitive controller can effectively compensate the dead-time harmonics and other low-order distortions, and also, it is a simple method without hardware modifications. [ABSTRACT FROM AUTHOR]

This paper presents a model-based method to diagnose single- and multiple-transistor open-circuit (OC) faults in grid-tied three-phase voltage-source inverters (VSIs). The method is based on calculated average bridge arm pole-to-pole (PTP) voltages and error-adaptive thresholds. Only existing signals for closed-loop control are needed; thus, this method can be easily embedded in the system without extra sampling and circuits. Average PTP voltage deviations are chosen as diagnosis variables, which show considerable distinction quickly after fault. Consequently, fast fault diagnosis speed can be achieved. The fault diagnosis time for single fault can be as short as two switching periods. Besides, diagnosis variables show the same faulty characteristics in inverter mode and rectifier mode; thus, this method is effective in both modes. Moreover, for the first time, the variation of inductance caused by conducted current is considered to obtain a more accurate variable-inductance model, and the thresholds are updated according to mathematically estimated diagnosis variable calculation errors from sampling error, inductance error, dead time, and delay time, which maintains high robustness as well as fast speed. Finally, the effectiveness of the proposed method is validated with experiments. [ABSTRACT FROM AUTHOR]

In this paper, a novel platform for the single phase switched-capacitor multilevel inverters (SCMLIs) is presented. It has several advantages over the classical topologies, such as an appropriate boosting property, higher efficiency, lower number of required dc voltage sources, and other accompanying components with less complexity and lower cost. The basic structure of the proposed converter is capable of making nine-level of the output voltage under different kinds of loading conditions. Hereby, by using the same two capacitors paralleled to a single dc source, a switched-capacitor (SC) cell is made that contributes to boosting the value of the input voltage. In this case, the balanced voltage of the capacitors can be precisely provided on the basis of the series–parallel technique and the redundant switching states. Afterward, to reach the higher number of output voltage levels, two suggested SC cells are connected to each other with a new extended configuration. Therefore, by the use of a reasonable number of required power electronic devices, and also by utilizing only two isolated dc voltage sources, which their magnitudes can be designed based on either symmetric or asymmetric types, a 17- and 49-level of the output voltage are obtained. Based on the proposed extended configuration, a new generalized version of SCMLIs is also derived. To confirm the precise performance of the proposed topologies, apart from the theoretical analysis and a complete comparison, several simulation and experimental results are also given. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid pulse width modulation-based discontinuous modulation (D-HPWM) strategy with dc-link voltage balancing for a three-level neutral-point-clamped (NPC) traction inverter drive. The results are then compared with continuous-hybrid-PWM (C-HPWM) to check the performance improvement. The HPWM strategy uses both the advantages of carrier- and space-vector-based PWM strategies. The duty cycles are generated using the carrier-based strategy to reduce the computational time and complexity of the system and redundant vector states are used to keep the two dc-link capacitor voltages balanced. As discontinuous PWM (DPWM) reduces the switching losses considerably compared to the continuous PWM, the DPWM strategy is developed in this paper for the HPWM-based strategy. Detailed comparison studies are then carried out in MATLAB/Simulink and PLECS to show the conduction and switching loss distribution with change in modulation index for different power switches. A 54.0-kW surface permanent magnet synchronous machine (PMSM) is used for this simulation studies. Moreover, the total inverter loss and losses in each insulated gate bipolar transistor (IGBT) are also compared. Detailed experimental performance analysis is also carried out with a scaled down prototype of a 6.0-kW surface PMSM, NPC inverter, and real-time emulator DSpace, to show the capacitor voltage deviation with both control strategies. [ABSTRACT FROM PUBLISHER]

This paper characterizes the sampling effect in digital sinusoidal pulse width modulation (SPWM) of voltage source inverter (VSI). The time-domain analysis presented in this paper establishes the relation between the fundamental frequency, carrier frequency, and the sampling frequency at different modulation indices of the SPWM. The analysis investigates the effect of sampling frequency of the digital controller on the output of the VSI. It is shown that the low-frequency harmonic components appear in the frequency spectrum of the VSI output voltage due to sampling. As a result, the output current of digitally controlled VSI is stepped in nature. The double Fourier integral solution of the switched waveform for inner and outer integral limits has been used to derive the expression. The integral solution is obtained using Jacobi-Anger expansions. The generalized results developed in this paper are useful to investigate the sampling effect in high switching frequency DSPWM. The proposed sampling effect has been analyzed for SPWM of single-phase H-bridge inverter. The analytical results are verified using simulation and experimental results. The experimental results have been obtained with the use of field-programmable gate array (FPGA) as a digital controller. [ABSTRACT FROM PUBLISHER]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

This paper presents a new multilevel cascaded-type dynamic voltage restorer (MCDVR) with a fault current-limiting function. This topology can operate in two operational modes: 1) a compensation mode for voltage fluctuations and unbalances and 2) short-circuit current-limiting mode. The current-limiting function of the MCDVR is performed by activating antiparallel thyristors during the short-circuit fault, and deactivating them during normal operation. The mathematical model of the MCDVR system is also established in this paper. The control scheme design and optimal parameter selection are outlined based on the detailed theoretical analysis of the converter. The transient states of the MCDVR in the compensation mode and current-limiting mode are also analyzed. Simulation results based on the PSCAD/EMTDC software, and experimental results on a laboratory setup help to validate the proposed topology and the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents a new application of power and voltage balance control schemes for the cascaded H-bridge multilevel inverter (CHMI)-based solid-state transformer (SST) topology. To reduce load on the controller and simplify modulation algorithm, a master–slave control (MSC) strategy is designed for the dual active bridge (DAB) stage. The master controller executes all control and modulation calculations, and the slave controllers manage only device switching and protection. Due to the inherent power and dc-link voltage unbalance in cascaded H-bridge-based SST, this paper presents a compensation strategy based on three-phase dq decoupled current controller. An optimum zero-sequence component is injected in the modulation scheme so that the three-phase grid currents are balanced. Furthermore, to tightly regulate the output voltage of all the DAB modules to target value, a dynamic reference voltage method is also implemented. With this proposed control method, the three-phase grid currents and dc-link voltage in each module can be simultaneously balanced. Finally, simulation and experimental results are presented to validate the performance of the controller and its application to microgrid SST. [ABSTRACT FROM PUBLISHER]

The traditional space-vector pulsewidth modulation (SVPWM) maximum voltage transfer ratio (VTR, i.e., the ratio of the output voltage fundamental amplitude to the input voltage fundamental amplitude) is 0.866 in a linear modulation region. In this paper, the output voltage fundamental amplitude and total harmonic distortion (THD) affected by a basic vector and a hexagon vector in traditional indirect SVPWM overmodulation are analyzed. The traditional indirect SVPWM overmodulation usually focuses on the inverter stage to improve the VTR, and there are few methods considering both of the inverter and rectifier stages to improve the overmodulation performance of a matrix converter (MC), including output voltage error, and output and input current THDs. In this paper, a new overmodulation method based on indirect SVPWM is presented. Both the output performance and input performance of the MC with the proposed and traditional overmodulation methods are emulated and tested. Simulation results indicate that the output voltage error and the input current THD are smaller and lower, respectively, with the proposed method. Experimental results verify that theoretical analysis is right, and the proposed overmodulation method is feasible. [ABSTRACT FROM PUBLISHER]

A four-level five-phase open-end winding (OeW) drive topology is introduced in this paper. The drive comprises a five-phase induction machine with open-end stator windings, supplied using two two-level voltage-source inverters with isolated and unequal dc-link voltages, in the ratio 2 : 1. The topology offers the advantages of a modular structure with fewer semiconductor components and has a greater potential for fault tolerance, as compared with an equivalent single-sided four-level drive. Due to the large number of switching states, development of a suitable space vector pulsewidth-modulation (PWM) method can be challenging. Hence, this paper examines the implementation of two-level-shifted carrier-based PWM methods. The effect of dead time on the drive performance is discussed, and it is shown that simultaneous PWM switching of both inverters can lead to degraded output phase voltage waveforms. Detailed analysis of this phenomenon is presented, a solution is proposed, and the modified modulation techniques are incorporated in an experimental setup, at first in conjunction with $V/f$ control. Once the proof of concept has been provided, full field-oriented control is implemented in this OeW drive topology for the first time; detailed experimental testing is conducted, and results are reported. [ABSTRACT FROM AUTHOR]

A virtual space vector modulation technique reducing both magnitude and third-order harmonic component of the common-mode voltage (CMV) in a two-level voltage-source inverter (VSI) is proposed in this paper. The presented method employs a set of virtual space vectors constructed from original stationary space vectors to conduct modulation. Since the created virtual vectors have the lowest instantaneous and zero average CMVs, both the magnitude and third-order harmonic component of the generated CMV are reduced, contributing to better overall CMV performance and common-mode filter design in VSI applications. Three variants of the proposed modulation method using different virtual space vector combinations are presented. The concept of the virtual space vector modulation technique demonstrated with two-level inverter in this paper can also be extended to multilevel inverters. Simulation and experimental results, as well as comparisons with existing methods are provided to verify the proposed technique. [ABSTRACT FROM AUTHOR]

Based on the Z-source inverter, this paper proposed a novel approach to zero-crossing point (ZCP) detections during the shoot-through vectors for sensorless brushless dc motor (BLDCM). The proposed approach separates the ZCP detections from speed adjustment, and makes the shoot-through vector not influence the motor speed-adjustment directly, while the zero-vectors and active-vectors are used exclusively to adjust the speed of BLDCM. With the proposed approach, the sensorless BLDCM can operate in a wide speed range without switching the detection points and the reference levels, and it is unnecessary to change the reference levels according to the PWM technique. The terminal voltages limited by diode can be directly compared with the reference zero level during the shoot-through vectors, so as to reduce the detection error caused by attenuation. Moreover, Z-source inverter not only provides boost voltage for sensorless BLDCM drive system, but also improves the utilization rate of dc source voltage and the safety of the drive system. In addition, this paper analyzed the terminal voltages of the floating phase during each vector. The experimental results verified the correctness of above theories and proved the effectiveness of the proposed approach. [ABSTRACT FROM AUTHOR]

Pulse width modulation (PWM) converters generate switching common-mode voltages (CMVs) across the load terminals. These voltages cause common-mode currents, leading to bearing failure in motor loads and electromagnetic interference problems. This paper presents a generalized carrier-based PWM technique for open-end winding motor drives that completely eliminates switching CMV. The proposed method is applicable to both dual two-level voltage source inverter and dual matrix converter-based open-end winding drives. Detailed analysis shows that the carrier-based method requires significantly less computation compared to the corresponding space vector implementation. This paper also outlines the relationship between the two implementations. The carrier-based method is shown to achieve superior performance in terms of resource requirements and execution time when implemented on a field-programmable gate array-based real-time control platform. Simulation and experimental results have been presented to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a vector control strategy for independent control of two permanent-magnet synchronous motors (PMSMs) using a single four-leg inverter (4LI). An expanded two-arm modulation to obtain a balanced three-phase output voltage is described. This paper also proposes a method to compensate for the fluctuations in the neutral point voltage of two split capacitors in the dc link. The experimental results show that independent speed and position control of two PMSMs can be achieved using a single 4LI with the proposed vector control method. [ABSTRACT FROM AUTHOR]

This paper presents a new multilevel selective harmonic elimination pulse-width modulation (MSHE-PWM) technique for transformerless static synchronous compensator (STATCOM) system employing cascaded H-bridge inverter (CHI) configuration. The proposed MSHE-PWM method optimizes both the dc-voltage levels and the switching angles, enabling more harmonics to be eliminated without affecting the structure of the inverter circuit. The method provides constant switching angles and linear pattern of dc-voltage levels over the modulation index range. This in turns eliminates the tedious steps required for manipulating the offline calculated switching angles and therefore, easing the implementation of the MSHE-PWM for dynamic systems. Although the method relies on the availability of the variable dc-voltage levels which can be obtained by various topologies, however, the rapid growth and development in the field of power semiconductor devices led to produce high-efficiency dc-dc converters with a relatively high-voltage capacity and for simplicity, a buck dc-dc converter is considered in this paper. Current and voltage closed loop controllers are implemented for both the STATCOM and the buck converter to meet the reactive power demand at different loading conditions. The technique is further compared with an equivalent conventional carrier-based pulse-width modulation to illustrate its enhanced characteristics. The effectiveness and the theoretical analysis of the proposed approach are verified through both simulation and experimental studies. [ABSTRACT FROM AUTHOR]

In this paper, the conventional I- and T-type three-level neutral-point-clamped (3L-NPC) inverter for low-voltage renewable energy systems is first investigated. Literature research shows that the T-type inverter improves I-type's insulated-gate bipolar transistor (IGBT) $+$ IGBT current paths. However, the IGBT $+$ diode paths are the same. The calculation in this paper further reveals that the IGBT $+$ diode current paths dominate the conduction losses and even the whole semiconductor losses. Based on the aforementioned recognitions, a novel T-type inverter is presented as an alternative to be applied in the low-voltage renewable energy systems. In the proposed 3L-NPC, four CoolMosfets replace the IGBT $+$ diode middle bidirectional switch. In the proposed topology, there is no diode involved in the current path supposing the unity power factor. In this way, the conduction loss is expected to be reduced compared with that from the conventional T-type 3L-NPC, particularly in the low and medium power ranges. [ABSTRACT FROM PUBLISHER]

Leakage current minimization is one of the most important considerations in transformerless photovoltaic (PV) inverters. In the past, various transformerless PV inverter topologies have been introduced, with leakage current minimized by the means of galvanic isolation and common-mode voltage (CMV) clamping. The galvanic isolation can be achieved via dc-decoupling or ac-decoupling, for isolation on the dc- or ac-side of the inverter, respectively. It has been shown that the latter provides lower losses due to the reduced switch count in conduction path. Nevertheless, leakage current cannot be simply eliminated by galvanic isolation and modulation techniques, due to the presence of switches' junction capacitances and resonant circuit effects. Hence, CMV clamping is used in some topologies to completely eliminate the leakage current. In this paper, several recently proposed transformerless PV inverters with different galvanic isolation methods and CMV clamping technique are analyzed and compared. A simple modified H-bridge zero-voltage state rectifier is also proposed, to combine the benefits of the low-loss ac-decoupling method and the complete leakage current elimination of the CMV clamping method. The performances of different topologies, in terms of CMV, leakage current, total harmonic distortion, losses and efficiencies are compared. The analyses are done theoretically and via simulation studies, and further validated with experimental results. This paper is helpful for the researchers to choose the appropriate topology for transformerless PV applications and to provide the design principles in terms of common-mode behavior and efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a fast and generalized space vector pulse width modulation (SVPWM) scheme for any multilevel inverter. The SVPWM scheme generates all the available switching states and switching sequences based on two simple and general mappings, and calculates the duty cycles simply as if for a two-level SVPWM, thus independent of the level number of the inverter. Because the switching states, duty cycles, and switching sequences are all obtained by simple calculation in the proposed SVPWM scheme, no lookup table is needed and the scheme is computationally fast. The generalized method of generating the switching states (first mapping), calculating the duty cycles, and determining the switching sequence (second mapping) is described in this paper. The scheme is suitable for any reference vector with any modulation index, and can be conveniently extended to meet specific requirements, such as symmetric switching sequences. Compared with prior methods, the SVPWM scheme proposed in this paper provides two more degrees of freedom, i.e., the adjustable switching sequences and duty cycles, thus offering significant flexibility for optimizing the performance of multilevel inverters. The influence of redundant switching sequences in the output phase voltage of inverters is demonstrated for a nine-level inverter. This paper also thoroughly compares the proposed SVPWM scheme with prior methods. Both simulation and experimental results are given. [ABSTRACT FROM AUTHOR]

Three optimized pulse-width modulated (PWM) techniques for the overmodulation region of two-level inverter-fed ac drives are introduced and investigated from the harmonic loss minimization point of view. The optimization is elaborated for the lowest loss-factor, which is proportional to the square of the root mean square value of current harmonics. The loss-factors are computed for different switching numbers as the function of the motor fundamental voltage. It is shown that, with respect to the motor heating and torque ripples, the acceptable drive condition can be guaranteed by a relatively low value of an inverter switching frequency up to 96%–97% of maximal possible motor voltage. Furthermore, it is shown that the so-called three-vector methods have considerably better performance in the lower part of the overmodulation region than the so-called two-vector method for the same number of switching. The performance of the techniques is compared with other existing PWM techniques. This paper discusses the implementation details of the proposed optimal PWM techniques. The theoretical results are verified by experimental and simulation tests. [ABSTRACT FROM AUTHOR]

This paper presents a new compact three-phase cascaded multilevel inverter (CMLI) topology with reduced device count and high-frequency magnetic link. The proposed topology overcomes the predominant limitation of separate dc power supplies, which CMLI always require. The high-frequency magnetic link also provides a galvanic isolation between the input and output sides of the inverter, which is essential for various grid-connected applications. The proposed topology utilizes an asymmetric inverter configuration that consists of cascaded H-bridge cells and a conventional three-phase two-level inverter. A toroidal core is employed for the high-frequency magnetic link to ensure compact size and high-power density. Compared with counterpart CMLI topologies available in literature, the proposed inverter has the advantage of utilizing the least number of power electronic components without compromising the overall performance, particularly when a high number of output voltage levels is required. The feasibility of the proposed inverter is confirmed through extensive simulation and experimentally validated studies. [ABSTRACT FROM AUTHOR]

A constant switching frequency hysteresis controller based on current error space vector (CESV) for two-level voltage source inverter fed induction motor (IM) drive is proposed in this paper. Here the stator voltages along the α- and β-axes are estimated using current error information and steady-state model of IM. Estimated stator voltages, switching dwell times, and instantaneous voltage error vectors are used in the online hysteresis boundary computations. The steady-state CESV boundaries and the phase voltage normalized harmonic spectrum of the proposed hysteresis controller at different speeds resembles that of a constant switching frequency voltage-controlled bus clamping pulse-width modulation-based drive. The proposed controller exhibits adjacent voltage vector switching, fast dynamic response under transient conditions, and has a simple controller implementation. The superior performance of the proposed controller is simulated using MATLAB/Simulink platform and experimentally verified on a three-phase 2.2 kW IM drive. [ABSTRACT FROM AUTHOR]

Generally, single-stage buck–boost inverters consist of distinct circuits operating individually in buck/boost or positive/negative modes, the latter definitely leading to crossover distortion in the output current. This paper proposes a switching strategy that changes the bimodal operation of a single-stage buck–boost topology to a single-mode inverter. This is due to the consequent voltage gain that ensures that the output voltage polarity, apart from its magnitude, is an exclusive function of the duty ratio. Operational principle and salient hardware design are explained with the help of equivalent circuits. Details about the dynamic model are presented, based on which controller design is carried out for both stand-alone and grid-connected operation. Experimental results obtained from a 300-W, 110-V laboratory prototype are presented to validate the performance of the proposed switching strategy. [ABSTRACT FROM PUBLISHER]

In this paper, the remedial operation of switch faults will be investigated comprehensively for T-type-three-level-inverter-fed dual three-phase motor drives. The open-circuit switch faults in multiple phase legs are discussed at first. The faulty conditions are classified into five categories. Different remedial strategies, namely Type-I to Type-V schemes, are proposed for different faulty conditions. In particular, three kinds of Type-III fault-tolerant control schemes are proposed by using medium-voltage vectors to synthesize small-voltage vectors, in such a way that the mid-point voltage in a dc link can be stabilized well. Then, the short-circuit faults in both clamping switches and half-bridge switches are investigated. By analysis, their operation conditions are equivalent to conditions loss of both P and N voltage levels and open-phase faults, respectively. Thus, the corresponding remedial strategies can be applied accordingly. Particularly, a voltage compensation control method is proposed for conditions, where open-switch faults coexist with open-phase operation induced by short-circuit faults in half-bridge switches. The validity of all of theoretical analysis and the proposed remedial strategies has been verified by experiments. [ABSTRACT FROM PUBLISHER]

In trasformerless grid-connected photovoltaic (PV) systems, common-mode voltage (CMV) fluctuations cause leakage current flow through the stray capacitance of the PV panels. Shoot-through states in a quasi-Z-source inverter (q-ZSI) increase the amplitude of high-order harmonics of CMV. In this paper, by using the modulation technique based on odd pulse width modulation and minor change in the Z network of the three-phase q-ZSI, the leakage current is blocked. No extra semiconductor element is added. By the proposed technique, CMV is kept nearly constant during switching cycles. The experimental results for CMV analysis in a \text1\;\textkW prototype are presented to verify the theoretical analysis. [ABSTRACT FROM PUBLISHER]