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This paper presents a new highly integrable hybrid step-down converter that merges switched-inductor and switched-capacitor operations and significantly reduces onboard loss by using the input cable's parasitic inductance as its main inductor. This converter has the inductor placed at the input with a smaller voltage swing, leading to possible use of a smaller inductor and low-voltage rating switches that generally translate to reduced conduction losses. Analyses of converter operation and losses to reveal its original characteristics and design guidelines are presented to facilitate the components optimization. The converter architecture is verified by a proof-of-concept 15-W inductor-less lithium-ion battery charger prototype that uses a 1-m USB 3.0 cable as inductor. The converter, switched at 2 MHz from a 5-V input, experimentally achieves 89.7% peak efficiency and 6% higher efficiency at full load than a Buck converter counterpart. This high efficiency and zero onboard inductor yield a relative 45.7% onboard loss reduction at full load, promising excellent integration feasibility and superior system thermal management. [ABSTRACT FROM AUTHOR]

This paper presents a method that overcomes the problem of the confusion during fast irradiance change in the classical maximum power point tracking (MPPT) as well as in model predictive control (MPC)-based MPPTs available in the literature. The previously introduced MPC-based MPPTs take into account the model of the converter only, which make them prone to the drift during fast environmental conditions. Therefore, the model of the photovoltaic (PV) array is also considered in the proposed algorithm, which allows it to be prompt during rapid environmental condition changes. It takes into account multiple previous samples of power, and based on that is able to take the correct tracking decision when the predicted and measured power differ (in case of drift issue). After the tracking decision is taken, it will be sent to a second part of the algorithm as a reference. The second part is used for following the reference provided by the first part, where the pulses are sent directly to the converter, without a modulator or a linear controller. The proposed technique is validated experimentally by using a buck converter, fed by a PV simulator. The tracking efficiency is evaluated according to EN50530 standard in static and dynamic conditions. The experimental results show that the proposed MPC-MPPT is a quick and accurate tracker under very fast changing irradiance, while maintaining high tracking efficiency even under very low irradiance. [ABSTRACT FROM AUTHOR]

This paper presents a multi-period frame transient switching control (MP-TSC) scheme for buck converter with a controlled coupled inductor, aiming at improving the load transient response. The proposed buck converter utilizes a controlled coupled inductor as the output inductor. During a load transient, the coupled inductor is controlled as a small equivalent inductance so as to achieve fast transient regulation. While in the steady state, the coupled inductor behaves as a large inductance to reduce the output current ripple. Furthermore, on the basis of the proposed variable inductance circuit, an MP-TSC control scheme is proposed and implemented in a digital form. With the proposed control scheme, the load transient event is divided into n + 1 sub-periods, and in each sub-period, the capacitor-charge balance principle is used to determine the switching time sequence. Moreover, the control principle design and transient response index analysis are provided. Furthermore, its feasibility is validated in simulation and experiment with a 12–3.3V low-voltage high-current synchronous buck converter. Experimental results demonstrate that the voltage deviation of the proposed MP-TSC scheme (coupled coefficient of the controlled coupled inductor is 0.52) has improved by more than 79% compared to that with the auxiliary circuit disabled. [ABSTRACT FROM AUTHOR]

In this paper, several new coupled-inductor-based soft-switching dc–dc converters are proposed. These converters are obtained by changing the coupled branch of several existing dc–dc converters. Meanwhile they have similar characteristics to these existing converters, and provide more choices for the practical application. Then by applying an existing efficiency improvement method, which is used in the buck-type soft-switching converter, to all abovementioned converters, several new converters with efficiency improvement characteristics are obtained. This efficiency improvement method utilizes the low conduction performance of the transistor to reduce the loss. In addition, this method has the same control complexity to original topologies, because the auxiliary transistor has the same control timing to one of main transistors. The characteristic of new converters and efficiency improvement method are presented by analyzing two new topologies (boost-type converters). Finally simulation and experimental results are given and analyzed by designing a prototype. Based on these results, soft-switching conditions and efficiency improvement capability are verified. [ABSTRACT FROM AUTHOR]

Using a photovoltaic (PV) emulator (PVE) simplifies the testing of the PV generation system. However, conventional controllers used for PVEs suffer from oscillating output voltage, requiring a high number of iterations, or being too complex to be implemented. This paper proposes a controller based on a resistance feedback control strategy that produces a stable and fast converging operating point for the PVE. The resistance feedback control strategy requires a new type of PV model, which is the current–resistance (I–R) PV model. This model is computed using a binary search method at a fast convergence rate. It is combined with a closed-loop buck converter using a proportional-integral controller to form the resistance feedback control strategy. The PVE's controller is implemented into dSPACE ds1104 hardware platform for experimental validation. The acquired experimental results show that the proposed PVE is able to follow the current–voltage characteristic of the PV module accurately. In addition, the PVE's efficiency is more than 90% under maximum power point operation. The transient response of the proposed PVE is similar to the PV panel during irradiance changes. [ABSTRACT FROM AUTHOR]

Medium-voltage (MV) silicon carbide (SiC) devices have opened up new areas of applications which were previously dominated by silicon-based IGBTs. From the perspective of a power converter design, the development of MV SiC devices eliminates the need for series connected architectures, control of multilevel converter topologies which are necessary for MV applications, and the inherent reliability issues associated with it. However, when SiC devices are used in these applications, they are exposed to a high peak stress (5–10 kV) and a very high $dv/dt$ (10–100 kV/ $\mu$ s). Using these devices calls for a gate driver with a dc–dc isolation stage that has ultralow coupling capacitance in addition to be able to withstand the high isolation voltage. This paper presents a new MV gate driver design to address these issues while maintaining a minimal footprint for the gate driver. An MV isolation transformer is designed with a low interwinding capacitance, while maintaining the clearance, creepage, as well as insulation standards. A dc isolation test has been performed to validate the integrity of the insulating material. The key features include low input common mode current, and a short-circuit protection scheme specifically designed for 10 kV SiC mosfets. The performance of the gate driver is evaluated using double pulse tests and continuous tests. Experimental results validate the advantages of the gate driver and its application for MV SiC devices exhibiting very high $dv/dt$. The proposed gate driver concept is aimed at providing an efficient and reliable method to drive MV SiC devices. [ABSTRACT FROM AUTHOR]

In this paper, a sequence switching control (SSC) scheme based on an auxiliary parallel inductor is proposed to improve the transient performance of buck converters. The proposed SSC scheme introduces a small controlled inductor in parallel with the output inductor, so as to increase the inductor-current slew rate when it is activated during a load transient. Furthermore, an “n+ 1” sequence switching strategy is proposed to control the auxiliary parallel inductor. The proposed scheme divides the transient event inton+ 1 periods. In the formernperiods, the same small output voltage deviations are designed, while in the last period, a smaller deviation is done for a smooth transition from the transient to the steady state. The switching sequence is derived applying the capacitor–charge balance principle for each ofn+ 1 periods. For a given buck converter in the experiment, the settling time and the output voltage deviation of the proposed SSC scheme enhance more than 50% and 67%, respectively, over those of the time-optimal control for a 3-A load step. [ABSTRACT FROM AUTHOR]

In this paper, a nonisolated high step-down converter is proposed. Energy transfer capacitor and built-in transformer are employed to achieve a very high step-down conversion ratio. Due to the interleaved technique, small values of output inductance can be used, leading to a fast transient response. Furthermore, the use of a coupled inductor reduces inductor current ripples, which implies lower losses. Two main switches and two synchronous rectifiers are used in the converter and all can achieve zero-voltage-switching. As no floating switches are employed, grounded gate drivers and boost strap drivers can be used, avoiding the use of complex isolated gate drivers. In addition, if the switches are shorted, the high input voltage does not appear at the output; thus, the load is protected. A 48 V/1 V 30 A prototype was built, and experimental results are provided to verify the performance of the converter. [ABSTRACT FROM AUTHOR]

This paper presents a delta-sigma modulation control scheme for buck converters that features a reconfigurable loop filter with a scalable sampling frequency for effective switching noise reduction and high conversion efficiency. Depending on the load current, the proposed controller changes the sampling frequency along with the delta-sigma modulator (DSM) structure to transform between third- and second-order loop filters. Thus, it maintains a robust noise shaping capability and reduces the power consumption over a wide load range. The loop filters are implemented with a single op-amp resonator to reduce multiple integrators into a single element and enhance controllability of the resonance. More power-efficient operation is obtained by a switching node assisted deadtime controller (SADTC) that regulates the body-diode conduction. The proposed DSM-based buck converter was fabricated on a 180 nm CMOS. A spurious-free output spectrum with a noise floor below −81 dBm was achieved across all sampling frequencies. It operated at a wide range sampling frequencies of 3.75–15 MHz and regulated the output in the range of 1.0–2.4 V with input voltages of 2.5–5.5 V. The output voltage ripples were maintained under 19 mV. The converter showed a conversion efficiency of better than 80% over a load range of 1–1000 mA with a peak efficiency of 95.4% at 125 mA. [ABSTRACT FROM AUTHOR]

The detuning of an inductive power transfer (IPT) system caused by the component tolerance and aging of the inductors and capacitors can decrease the system efficiency, accordingly. To tune the receiver circuit of the IPT system dynamically, an inductor is parallelly connected with a diode full-bridge rectifier cascaded with a buck converter serving as a tuning circuit in this paper. By changing the duty cycle of the buck converter, the impedance of the tuning circuit can be adjusted to compensate the reactance caused by detuning. The tuning range of the proposed method is analyzed in detail. A corresponding control method, in which an auxiliary measurement coil is utilized, is proposed to tune the receiver circuit dynamically while regulating the output voltage. Because the buck converter is with the dc side of the receiver, no synchronization is required for the switches of the buck converter, and the switching frequency of the buck converter can be much lower than the inverter frequency. A 400 W prototype is established to validate the proposed method. The experimental results show that with 15% tolerance of the resonant capacitor in the receiver side, the system efficiency with the proposed tuning method can reach 91% with an improvement by 7.9% compared to the detuned system. [ABSTRACT FROM AUTHOR]

This paper proposes an interleaved buck converter (IBC) with continuous input current, extremely low output current ripple, low switching losses, and improved step-down conversion ratio. Unlike the conventional IBC, the proposed converter has a continuous input current, and its output current ripple is extremely low. The proposed converter has a lower voltage stress in comparison to the conventional IBC and can also provide a high step-down ratio, which makes it a proper choice for high-power applications where a nonisolated step-down converter with low output current ripple and continuous input current is required. Also, the proposed converter can provide current sharing between two interleaved modules without using additional current-sharing control method. All of these benefits are obtained without any additional stress on the circuit components. A prototype converter with 200-V input and 24-V–10-A output is implemented to verify the theoretical analysis. Operational principles and experimental results are presented in this paper. [ABSTRACT FROM PUBLISHER]

V2Ic control provides very fast dynamic performance to the Buck converter both under load steps and under voltage reference steps. However, the design of this control is complex since it is prone to subharmonic oscillations and several parameters affect the stability of the system. This paper derives and validates a very accurate modeling and stability analysis of a closed-loop V2Ic control using the Floquet theory. This allows the derivation of sensitivity analysis to design a robust converter. The proposed methodology is validated on a 5-MHz Buck converter. The work is also extended to V2 control using the same methodology, showing high accuracy and robustness. The paper also demonstrates, on the V2 control, that even a low bandwidth-linear controller can affect the stability of a ripple-based control. [ABSTRACT FROM AUTHOR]

A continuous-conduction mode (CCM) noninverting buck–boost (NBB) converter with a fast duty-cycle calculation (FDCC) control and duty-cycle locking strategy is proposed in this paper. Utilizing auxiliary and adjustable slopes of the modulation signal, the FDCC control not only rapidly determines an accurate duty cycle but also keeps the compensator output constant when the input voltage changes. The theoretical dc value of the numerator of the closed-loop line-to-output voltage transfer function is equal to zero whether the CCM NBB converter operates in boost or buck mode. It indicates that adopting the FDCC control can achieve ideal feedforward compensation for CCM buck and boost operations. Consequently, the output transient ripple of the CCM NBB converter with FDCC control can be eliminated significantly regardless of the unit-gain bandwidth of the NBB converter. To alleviate pulse skipping and to avoid changing buck and boost modes frequently, a duty-cycle locking method is adopted in the transition region of the buck and the boost. Hence, the duty-cycle locking method enhances power conversion and maintains the output voltage. The experimental results demonstrate that the proposed control schemes not only effectively reduce the line transient ripple but also obtain high efficiency in a wide range of input voltage. [ABSTRACT FROM AUTHOR]

The visible light communication (VLC) can provide data transmission via the illumination light emitting diodes (LED). This paper introduces a new model to analyze the bit error rate (BER) of binary phase modulation in VLC for an arbitrary modulation depth and data duty cycle while taking into account both the Gaussian and signal-dependent shot noise. The impact of the driver design on the BER and its impact on ripple have not been considered in detail before. We compare two different LED driver schemes, namely directly adapting the driver control loop and binary shunting. We address data rate, BER, and power efficiency, for which we propose to use the extra energy per symbol above unmodulated light. We further introduce an analysis of the effect that (truncated) ripple interference has in the (matched or other) filter of the receiver. Ripple causes a harmful interference in VLC, and thus a BER expression is derived to include its effect. Two approximations are proposed to model the ripple interference, and their accuracies are compared by simulations. A low-pass filtering is proposed to alleviate the impact of ripple interference in VLC system. [ABSTRACT FROM PUBLISHER]

GaN power switches provide remarkable performance in terms of power-density, reduced parasitics, and high-thermal handling capability that enable the realization of very efficient and compact dc/dc converters. Despite exhibiting state-of-the-art channel conductivity, GaN high electron mobility transistor (HEMT) devices are affected by the degradation of the dynamic on-Resistance (RON) at increasing off-state voltages and operative temperatures. In this paper, a novel laboratory setup and characterization procedure for the dynamic RON of GaN HEMT switches in the presence of thermal- and trapping-effects is presented. The proposed setup allows the study of RON transients after the switching event at variable off-state voltages and temperatures. The use of custom-designed differential amplification stages and a voltage-controlled current source enables the accurate characterization of RON even on large periphery devices. At first, the proposed setup is tested with a well-established and mature device technology such as a Si MOSFET. Degradation of the RON up to 120% due to temperature variation is observed with the presented setup. The setup is then used for the characterization of commercial-grade GaN-on-SiC and GaN-on-Si HEMTs. For both technologies dynamic RON degradations up to 75% and 20% are observed for temperature and off-state voltage variations, respectively. These characterization data are fundamental for the accurate estimation of conduction losses during the design of switching-mode power converters. [ABSTRACT FROM PUBLISHER]

Automotive point-of-load dc–dc converters have a wide input voltage range from 4.5 to 42 V and, in order to avoid the AM band interference and comply with the strict CISPR-25 standard for electromagnetic interference (EMI) performance, the switching frequency is desired to be higher than 2 MHz. Buck converter is currently employed for such applications owing to its simplicity and low cost, but it has low efficiency at high switching frequencies and high EMI noise emission due to hard switching. A new active-clamp buck converter is proposed in this paper, which features zero-voltage-switching for main and auxiliary switches, and soft turnoff for synchronous rectifier over a wide input voltage range. The detailed operating principle analysis and several important design considerations are presented. Extensive design equations that can be adapted for other specifications and applications are also derived. A 2.2 MHz, 5V/5A prototype converter with only Silicon mosfets has been designed, built, and tested. The experimental results verify the converter operation and demonstrate the superior performance of the proposed active-clamp buck converter. [ABSTRACT FROM PUBLISHER]

Lifetime is an important performance factor in the reliable operation of power converters. However, the state-of-the-art LC filter design of a buck dc–dc converter is limited to the specifications of voltage and current ripples and constrains in power density and cost without reliability considerations. This paper proposes a method to optimize the design of the LC filters from a reliability perspective, besides other considerations. An enhanced model is derived to quantify the lifetime of the capacitor in the filter considering the electrothermal stress on it. Furthermore, the influence of different design aspects such as the value of capacitance, the value of inductance, and the type of the capacitor have been discussed, focusing on their impacts on the key design objectives, which are the cutoff frequency, lifetime, and volume. Based on the analysis, an optimized design is proposed among different parameter sets. A 1-kW converter prototype is applied to verify the theoretical analysis and simulation. [ABSTRACT FROM AUTHOR]

This paper presents a digital hybrid ripple-based constant on-time control scheme for voltage regulator modules (VRMs). Due to the sampling effects of the digital implementation, the stability issue becomes worse than the analog ripple-based control schemes, especially when the composite output capacitors are utilized. In order to stabilize the system and to fulfill the output impedance requirement of adaptive voltage positioning (AVP), a hybrid ramp compensation strategy, which includes the external ramp and the estimated current ramp, is proposed in this paper. No complicated compensators are required as the conventional voltage-mode control. The small-signal model of the proposed architecture is derived to provide the design guideline for the ramp compensation gains with different output capacitors. Besides, the oversampling effect of the output voltage by using analog-to-digital converters (ADCs) are also analyzed by using the presented model. Simulation and experimental results show that the proposed digital ripple-based control architecture can achieve fast load transient performance and to fulfill the AVP design requirements of single-phase VRMs. [ABSTRACT FROM AUTHOR]

All the interconnected regulated systems are prone to impedance-based interactions making them sensitive to instability and transient-performance degradation. The applied control method affects significantly the characteristics of the converter in terms of sensitivity to different impedance interactions. This paper provides for the first time the whole set of impedance-type internal parameters and the formulas according to which the interaction sensitivity can be fully explained and analyzed. The formulation given in this paper can be utilized equally either based on measured frequency responses or on predicted analytic transfer functions. Usually, the distributed dc–dc systems are constructed by using ready-made power modules without having thorough knowledge on the actual power-stage and control-system designs. As a consequence, the interaction characterization has to be based on the frequency responses measureable via the input and output terminals. A buck converter with four different control methods is experimentally characterized in frequency domain to demonstrate the effect of control method on the interaction sensitivity. The presented analytical models are used to explain the phenomena behind the changes in the interaction sensitivity. [ABSTRACT FROM AUTHOR]

This paper proposes a new digital enhanced V^2 -type constant on-time control architecture for solving the ripple oscillation issues when using low-equivalent series resistance (ESR) capacitors in a buck converter. Instead of directly sensing the inductor current, an inductor current ramp estimator with the drift compensation is presented as adding a virtual ESR ripple to the output voltage. Only the input and output voltages are required to be sampled with analog-to-digital converters (ADCs) for estimating the inductor current ramp. Since the sampling rate and resolution requirements of ADCs for voltage sensing are usually less critical with compared to direct current sensing, the proposed digital control architecture is practical for low-cost applications. Besides, the limit-cycle oscillations due to the sampling effects can also be improved by using the estimated current ramp. Furthermore, the small-signal model of the proposed digital enhanced V ^2 control architecture is provided to design the estimated current ramp amplitude to stabilize the system and to optimize the system performance. The drift compensation effect is also analyzed in this paper. The effectiveness of the proposed control architecture with the current ramp estimator has been verified with simulation and experimental results by using an FPGA-based hardware platform. [ABSTRACT FROM AUTHOR]

To overcome the traditional buck converter, which is difficult to achieve a high step-down gain with an appropriate duty cycle, a coupled-inductor-based step-down converter, named ultrahigh step-down converter, is proposed by Hwu et al. [11]. As compared with the buck converter, the ultrahigh step-down converter can achieve a much higher step-down gain, which can be determined by not only the duty cycle but also the turns ratio of the coupled inductor. However, the ultrahigh step-down converter is designed at a fixed input voltage of 48 V. In the telecommunication applications, the high dc bus voltage varies in a wide range, not kept at a fixed nominal voltage of 48 V. The experimental results show that as the input voltage increases, the efficiency of the ultrahigh step-down converter decreases. Therefore, in this paper, an improved ultrahigh step-down converter with a wide input voltage range is presented. According to the topology exchange, the voltage gain can be changed to a suitable one when the input voltage changes. By doing so, as compared with the ultrahigh step-down converter [11], the duty cycle of the proposed converter can be extended, and hence the efficiencies of the proposed converter can be improved. The proposed converter is verified by a wide input voltage (18–54 V), with an output voltage of 1.2 V and a rated output current of 10 A. [ABSTRACT FROM AUTHOR]

This paper presents a new buck converter with optimum-damping and dynamic-slope compensation techniques. The optimum-damping control is a well-known current control method, and the proposed dynamic-slope generator can achieve frequency compensation to prevent subharmonic oscillation. When the system is disturbed, the proposed dynamic-slope generator can stabilize the circuit in a single cycle. Hence, the dynamic-slope compensation can be used to replace traditional extra slope compensation in the optimum-damping-control circuit. The measured transient time of the load current is 2 μs from 50 to 500 mA, and 3 μs from 500 to 50 mA. The optimum-damping-control techniques can rapidly reach desired output voltage in 2–3 switching cycles. The experimental and simulation results confirm that the proposed approach can achieve the slope compensation and accelerate the transient response. The proposed converter has been fabricated with TSMC 0.18 μm CMOS 1P6M technology. The converter's operating frequency is 1 MHz, the maximum output current is 500 mA, and the peak power efficiency is 89.68% under 300-mA load current. The chip area is only 1.0376 mm × 1.0599 mm (include PADs). [ABSTRACT FROM PUBLISHER]

Due to the simplicity and high reliability, brushless dc (BLDC) motors are widely used in space application. High-reliability levels are the vital aspect for ensuring the long-term stable operation of the BLDC motor system, which is used in aerospace applications. The fault-tolerant control of the BLDC motor is of great importance for its continuous operating capacity even under the faulty situation. This paper proposes a fault-tolerant topology composed of an additional phase leg and a fault-protective circuit for the high-speed low-inductance BLDC motor. Based on the analysis of the overcurrent and overvoltage phenomenon after the switch faults, a novel fault isolation and system reconfiguration method is presented. The method can achieve safe isolation and reconfiguration to avoid the secondary fault caused by direct switch of the redundant switch and the faulty switch after the fault-diagnosis process. Both simulation and experimental results confirm the feasibility and effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

A two-switch semiquadratic fifth-order buck converter belonging to a minimum-phase family is proposed in this paper. The proposed converter exhibits better dynamic performance, steady-state voltage gain in between conventional buck and quadratic buck converter. In view of this characteristic, it gives more bucking than the traditional buck converter. A time-domain analysis is formulated to predict the converter's steady-state performance. Also, the equations for designing the energy storage elements are established. Salient performance features, voltage bucking and source current ripples, of the proposed converter are compared to other competing/reported buck topologies. Transfer functions are obtained through state-space models, and then these are used in the controller design studies. The converter stabilization characteristics are studied through simulations. The analytical predictions and key features of the proposed converter are verified through experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a new power conversion scheme for paralleled server power supplies. The snubber capacitor voltage is utilized for the secondary voltage source, from which bidirectional buck converter provides output power to the load under a very light-load condition. To increase the energy of the secondary voltage source, an additional voltage bus is connected between the snubber capacitors from each power supply. The main advantage of the proposed scheme is that high efficiency can be achieved especially under a very light-load condition because of the low switching and core loss achieved by using the buck converter instead of the conventional structure composed of a primary inverter, an isolation transformer, and a secondary rectifier. Furthermore, the buck converter is integrated into the secondary rectifier circuits, so additional components are minimized. The validity of the proposed converter is confirmed by the experimental results from two 12-V/750-W prototype modules. [ABSTRACT FROM PUBLISHER]

This paper proposes a new interleaved buck converter (IBC) having low switching losses and improved step-down conversion ratio, which is suitable for the applications where the input voltage is high and the operating duty is below 50%. It is similar to the conventional IBC, but two active switches are connected in series and a coupling capacitor is employed in the power path, such as Cuk, Sepic, and Zeta converters. The proposed IBC shows that since the voltage stress across all the active switches is half of the input voltage before turn-on or after turn-off when the operating duty is below 50%, the capacitive discharging and switching losses can be reduced considerably. This allows the proposed IBC to have higher efficiency and operate with higher switching frequency. In addition, the proposed IBC has a higher step-down conversion ratio and a smaller output current ripple compared with a conventional IBC. The features, operation principles, and relevant analysis results of the proposed IBC are presented in this paper. The validity of this study is confirmed by the experimental results of prototype converters with 150-200 V input, 24 V/10 A output. [ABSTRACT FROM AUTHOR]

Linear small-signal models of a dc–dc converter often ignore switching dynamics; thus such models are insufficient to fully explore the performance objective under large signal transients. Linear/nonlinear hybrid controllers are promising alternatives; however, they require structurally different hardware resources along with extra antiwindup arrangements. This paper proposes a geometric tuning method in a digitally current-mode-controlled buck converter under continuous-conduction mode. This considers a proportional-integral voltage controller along with a load current feedforward in the digital domain, while the inductor current has a traditional analog implementation. This resembles a first-order switching surface with near load-invariant regulation; thus a (fixed) small integral gain is sufficient to minimize the steady-state error. Using phase-plane geometry, the objective is to tune the controller gain in a way to achieve proximate time optimal recovery using a fixed-frequency pulse-width modulator and also to retain the large-signal stability. The effects of parameter variation and finite sampling are analyzed. The proposed tuning is implemented using an FPGA device. [ABSTRACT FROM AUTHOR]

This paper proposes a novel wavelet transform-based approach for electromagnetic interference (EMI) noise mitigation in power electronics topologies. The switching action of power semiconductor devices generates EMI in power converter modules which exceeds the noise limit set by the regulation of CISPR11. In order to cancel the EMI noise, the wavelet transform-based time-frequency localization approach has been used for generating a noise cancellation signal. The effectiveness of the proposed method has been evaluated in the terms of signal-to-noise ratio (SNR). Further, the effect of variance of the noise amplitude has been taken into consideration on the SNR. A relationship between the standard deviation, which is proportional to square root of the variance of the signal, and the SNR has been established. The proposed method has been implemented on the different power electronics topologies such as buck converter, boost converter, three-phase voltage source inverter, and Z-source inverter-based ac drive. The proposed method achieves the reduction of noise level below the safe limit set by CISPR11. [ABSTRACT FROM PUBLISHER]

This paper presents a study of a bendable transformer for wearable electronics. Printed on a thin and bendable film, this transformer is bendable to wrap around body limbs such as the forearm. A model using a partial equivalent circuit theory has been developed to analyze the characteristic of an inductor and a bendable transformer. The mutual inductance and self-inductance for the bendable transformer over a range of bent curvatures have been calculated based on the model and compared favorably with measurements. Simulation and experimental results of applying the bendable inductor and transformer in dc–dc converters as a 5-V 500-mA power supply are included to confirm the usefulness of the transformer and the validity of the model. [ABSTRACT FROM AUTHOR]

A novel bipolar current source driver (CSD) for power MOSFETs is proposed in this paper. The proposed bipolar CSD alleviates the gate current diversion problem of the existing CSDs by clamping the gate voltage to a flexible negative value (such as -3.5 V) during turn-off transition. Therefore, the proposed driver is able to turn off the MOSFET much faster with a higher effective gate current. The idea presented in this paper can also be extended to other CSDs to further improve the efficiency with high output currents. The experimental results verify the benefits of the proposed CSD. For buck converters with 12 V input at 1 MHz switching frequency, the proposed driver improves the efficiency from 80.5% using the existing CSD to 82.5% (an improvement of 2%) at 1.2 V/30 A, and at 1.3 V/30 A output, from 82.5% using the existing CSD to 83.9% (an improvement of 1.4%). [ABSTRACT FROM AUTHOR]

This paper proposes a new control technology that enables a synchronous rectifier (SR) buck converter to realize zero voltage switching (ZVS) in light load condition. The SR control technique is applicable to dc low voltage output because the replacement of output rectifier diode by MOSFET can minimize conduction losses and increase the efficiency of the whole circuit. However, the technique cannot achieve good efficiency in light load condition. The control technique introduced in this paper enables an SR buck converter to carry out ZVS in light load condition to increase efficiency. No extra auxiliary switches or RLC passive components are required; thus, it is low cost and easy to control. The output of buck converter with 5 V/25 W featured by SR is developed in this paper; the availability of the technique introduced, herein, is also proven. The experimental results are satisfactory. [ABSTRACT FROM AUTHOR]

The critical conduction mode (CRM) control has some disadvantages such as the increase of switching loss and conduction loss of the main switch at extreme high/low voltage conversion applications. In this paper, a CRM buck converter with tapped inductor is proposed to overcome these problems. In this converter, both the active switch and the diode have soft switching operation by the resonance between the switch parasitic capacitors and the filter inductor. Furthermore, the peak current of the main switch is reduced by tapped inductor operation, thus the conduction loss and switching loss levels of the main switch are lowered. Consequently, this tapped inductor scheme with CRM control alleviates the severe power stress and enhances device utilization. For the proposed converter evaluation, this paper provides the operation analysis and design procedures of the converter, and also presents the hardware verification for a 50-W prototype operating at maximum 70 kHz. Finally, a new topology family derived by combination of CRM operation with the basic tapped-inductor converter is included. [ABSTRACT FROM AUTHOR]

This paper presents an energy-efficient buck-type capacitor charger integrated circuit (IC) that can deliver high instantaneous power from a low-capacity battery using a capacitor as an energy buffer. The prototype IC, which was designed and fabricated in 250-nm CMOS, reduces capacitor charging losses by driving the buck converter with gradually increasing pulsewidths and then recycles the remaining energy by operating the buck converter in the reverse direction. The presented digital pulsewidth modulator (DPWM) supports a wide range of duty cycles from 4% to 96% with a fine resolution of 0.36% and a high switching frequency of 1.5 MHz. The optimal switching frequency and transition time that can minimize the charging/discharging losses are analyzed. The prototype charger IC can charge a 10\text-\upmuF capacitor to 4.2 V with a transition time of 1.25 ms with a peak charging efficiency of 93% while operating at a 1.5-MHz switching frequency. [ABSTRACT FROM PUBLISHER]

Active magnetic bearings (AMBs) have been proved superior to conventional bearings in many ways. However, the AMB system will lose magnetic force if the power fails which may cause fatal damage to the rotor and the backup bearings. In order to improve the reliability of the AMB system, a power failure compensation control (PFCC) method is proposed in this paper. A novel hardware composition of PFCC is designed to cooperate with the motor drives using either pulse-width modulation (PWM) or pulse-amplitude modulation techniques. Once the power fails, the motor works as a generator and the back electromotive force (back EMF) is rectified by the antiparallel diodes of the inverter. Meanwhile, a buck converter is utilized to convert the voltage from dc-link of the inverter to the supply voltage for the AMB system. When the motor speed is too low to supply high back EMF for the buck converter, the switches of the inverter are used to boost the dc-link voltage with the motor windings. Furthermore, a hybrid controller combining sliding mode control with PID algorithm is introduced to improve the transient response of the buck converter. Several experimental results confirm the feasibility and effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

The Navy's future and near-term high-energy sensors and energy weapons will consume a large portion of the resources of the intended ship platform. Many of these new systems will have extreme dynamic power profiles, including both periodic and aperiodic characteristics. These dynamics can cause sudden changes in power at the prime power system that can be stressing to platform systems, both to the generators and prime movers as well as other loads sharing the common distribution bus. This paper presents the use of a new adaptive power system (APS) to mitigate the negative impacts levied on the platforms resulting from large dynamic loads. A notional size of the hardware required to implement the APS design is presented along with simulation results verifying the concept. [ABSTRACT FROM AUTHOR]

This paper proposes a single-phase high-power-factor ac/dc converter with soft-switching characteristic. The circuit topology is derived by integrating a boost converter and a buck converter. The boost converter performs the function of power-factor correction to obtain high power factor and low current harmonics at the input line. The buck converter further regulates the dc-link voltage to provide a stable dc output voltage. Without using any active-clamp circuit or snubber circuit, the active switches of the proposed converter can achieve zero-voltage switching-on transition together with high power factor that satisfies the IEC 61000-3-2 standards over a wide load range from 30% to 100% rated power. The steady-state analysis is developed and a design example is provided. A prototype circuit of 60 W was built and tested. Experimental results verify the feasibility of the proposed circuit with satisfactory performance. [ABSTRACT FROM PUBLISHER]

Unpredictable continuous conduction mode switching frequency variation that occurs commonly in ripple-based control can lead to serious electronic–magnetic interface noise problems and thus increase the effort required for designing noise filters. Sensorless load current correction and dynamic tolerance window techniques are proposed in this paper to reduce the frequency variations caused by conduction losses without employing complicated circuits such as phase-locked loop or current sensors. The proposed dc–dc buck converter with input voltage ranging from 2.7 to 3.6 V and an output voltage between 1.0 and 1.2 V was fabricated using a standard 0.18-μm CMOS process, and the converter achieved excellent adaptive voltage positioning function. Experimental results show that the switching frequency variation improved approximately 60% over traditional techniques in constant on-time control when the load current was changed from 150 to 1000 mA. The measurement results also show that frequency variation across the entire input/output and loading ranges was lowered to only ±2.6%. The maximum power efficiency was 88.2% at 150 mA with an input voltage of 2.7 V. [ABSTRACT FROM AUTHOR]

As electrolytic capacitor is apt to fail in power circuits, it is very important to identify its electrical parameters, mainly the equivalent series resistance (ESR) and capacitance (C). A noninvasive online identification method of capacitor's ESR and C for continuous-conduction-mode (CCM) buck converter is proposed in this paper. Based on the ac component of capacitor voltage, the calculation model is founded. By sampling the pulse width modulation signal and output voltage, the method needs no current sensor and is effective for the CCM buck converter operating at different conditions. Implementation of the identification system is presented. The tests are carried out for different aged capacitors and ambient temperatures. The experimental results validate the effectiveness of the method. [ABSTRACT FROM AUTHOR]

With the recent development and availability of wide bandgap devices in the market, more and more power converters are being designed with such devices. Given their fast commutation, when compared to their equivalent Si-based counterparts, these new devices allow increasing the converter's efficiency and/or power density. However, in order to fully avail these new devices, one should precisely know their switching characteristics and exploit it the best way possible. This paper recalls our own precise method to measure separately turn-on and turn-off energies of wide bandgap devices. This method is applied to commercially available SiC and GaN transistors and results show that they present much lower turn-off than turn-on energies. For that reason, we show that a SiC-based buck converter must have high current ripple in the output filter inductor in order to decrease transistor losses. Analysis of these losses as well as experimental results are presented. Finally, the precise design of a 2-kW SiC-based buck converter for aircraft applications is performed for different current ripples and switching frequencies. We show that current ripple higher than 250% of the dc load current significantly decreases the converter's losses, and consequently allows the increase of the switching frequency, which reduces the system volume and weight. [ABSTRACT FROM AUTHOR]