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In recent years, embedded dynamic random-access memory (eDRAM) technology has been implemented in last-level caches due to its low leakage energy consumption and high density. However, the fact that eDRAM presents slower access time than static RAM (SRAM) technology has prevented its inclusion in higher levels of the cache hierarchy. This paper proposes to mingle SRAM and eDRAM banks within the data array of second-level (L2) caches. The main goal is to achieve the best trade-off among performance, energy, and area. To this end, two main directions have been followed. First, this paper explores the optimal percentage of banks for each technology. Second, the cache controller is redesigned to deal with performance and energy. Performance is addressed by keeping the most likely accessed blocks in fast SRAM banks. In addition, energy savings are further enhanced by avoiding unnecessary destructive reads of eDRAM blocks. Experimental results show that, compared to a conventional SRAM L2 cache, a hybrid approach requiring similar or even lower area speedups the performance on average by 5.9 percent, while the total energy savings are by 32 percent. For a 45 nm technology node, the energy-delay-area product confirms that a hybrid cache is a better design than the conventional SRAM cache regardless of the number of eDRAM banks, and also better than a conventional eDRAM cache when the number of SRAM banks is an eighth of the total number of cache banks. [ABSTRACT FROM AUTHOR]

Attackers target many different types of computer systems in use today, exploiting software vulnerabilities to take over the device and make it act maliciously. Reports of numerous attacks have been published, against the constrained embedded devices of the Internet of Things, mobile devices like smartphones and tablets, high-performance desktop and server environments, as well as complex industrial control systems. Trusted computing architectures give users and remote parties like software vendors guarantees about the behaviour of the software they run, protecting them against software-level attackers. This paper defines the security properties offered by them, and presents detailed descriptions of twelve hardware-based attestation and isolation architectures from academia and industry. We compare all twelve designs with respect to the security properties and architectural features they offer. The presented architectures have been designed for a wide range of devices, supporting different security properties. [ABSTRACT FROM PUBLISHER]

For advanced features of next generation vehicles, the real-time programs in automotive embedded systems are dramatically increasing. For such large volume program codes, this paper proposes a novel framework to use high-density and low-cost nonvolatile memory, i.e., NAND flash memory, as a low-cost means of storing and executing hard real-time programs. Regarding this, one challenge is that NAND flash memory allows only 2 KB page-based read operations not per-byte random accesses, which requires RAM as working storage for code executions. This paper proposes two solutions, i.e., partitioned RAM solution and shared RAM solution, that minimize the RAM size required to deterministically guarantee the deadlines of all the hard real-time tasks. The proposed solutions are verified with the actual real-time programs for unmanned autonomous driving. To the best of our knowledge, this is the first work that allows us to use NAND flash memory for hard real-time program executions with the minimal usage of RAM. [ABSTRACT FROM PUBLISHER]

In this paper, we deal with the problem of efficiently assessing the higher order vulnerability of a hardware cryptographic circuit. Our main concern is to provide methods that allow a circuit designer to detect early in the design cycle if the implementation of a Boolean-additive masking countermeasure does not hold up to the required protection order. To achieve this goal, we promote the search for vulnerabilities from a statistical problem to a purely symbolical one and then provide a method for reasoning about this new symbolical interpretation. Eventually we show, with a synthetic example, how the proposed conceptual tool can be used for exploring the vulnerability space of a cryptographic primitive. [ABSTRACT FROM AUTHOR]

In this paper, we describe the high-performance implementation of an optical-flow algorithm that takes advantage of the processor's architecture. Tuning the code, i.e., adapting it to take full advantage of the processor, is challenging, time consuming, and requires efficient programming at different levels but can lead to significant improvements in performance. The optimized implementation presented here is highly interesting for a number of applications since it delivers real-time motion estimations at high-image resolution on a PC or in an embedded system based on a general-purpose processor. In a 2.83 GHz Core 2 Quad PC, it achieves a speedup of 14 compared to our first code version and 2052.7 f/s for the well-known 252 × 316 Yosemite sequence, and a speedup of 17.6 and 68.5 f/s for a 1016 × 1280 sequence. But the description of how this high-performance is achieved goes beyond a specific application since the paper presented here illustrates how inherently dense, low-level visual algorithms (pixel-wise computation) can be structured and improved to take full advantage of a standard processor. The implementation is compared with other hardware (based on FPGAs and GPUs) and software (based on clusters, PCs, and special-purpose processors) optical-flow implementations, showing that it outperforms them. [ABSTRACT FROM AUTHOR]

Second order Differential Power Analysis (20-DPA) is a powerful side-channel attack that allows an attacker to bypass the widely used masking countermeasure. To thwart 2O-DPA, higher order masking may be employed but it implies a nonnegligible overhead. In this context, there is a need to know how efficient a 2O-DPA can be, in order to evaluate the resistance of an implementation that uses first order masking and, possibly, some hardware countermeasures. Different methods of mounting a practical 2O-DPA attack have been proposed in the literature. However, it is not yet clear which of these methods is the most efficient. In this paper, we give a formal description of the higher order DPA that are mounted against software implementations. We then introduce a framework in which the attack efficiencies may be compared. The attacks we focus on involve the combining of several leakage signals and the computation of correlation coefficients to discriminate the wrong key hypotheses. In the second part of this paper, we pay particular attention to 2O-DPA that involves the product combining or the absolute difference combining. We study them under the assumption that the device leaks the Hamming weight of the processed data together with an independent Gaussian noise. After showing a way to improve the product combining, we argue that in this model, the product combining is more efficient not only than absolute difference combining, but also than all the other combining techniques proposed in the literature. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid scheduling methodology for task graphs to multiprocessor embedded systems. The proposed methodology is designed for task graphs that are dynamic in nature due to the presence of conditional tasks and tasks whose execution times are unpredictable but bounded. We have presented the methodology as a three-phase strategy, in which task nodes are mapped to the processors in the first (static mapping) phase. In the second (selective duplication) phase, some critical nodes are identified and duplicated for possible rescheduling at runtime, depending on the code memory constraints of the processors. The third (online) phase is a runtime scheduling algorithm that performs list scheduling based on the actual dynamics of the schedule up to the current time. We show that this technique provides better schedule length (up to 20 percent) compared to previous techniques, which are predominantly static in nature, with low overhead and a complexity comparable with existing online techniques. The effects of model parameters like the number of processors, memory, and various task graph parameters on performance are investigated in this paper. [ABSTRACT FROM AUTHOR]

Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern microelectronics products. This paper discusses a design strategy that eases the implementation of embedded fuzzy controllers as systems on programmable chips. The development of the controllers is carried out by means of a reconfigurable platform based on field-programmable gate arrays. This platform combines specific hardware to implement fuzzy inference modules with a general-purpose processor, thus allowing the realization of hybrid hardware/software solutions. As happens to the components of the processing system, the specific fuzzy elements are conceived as configurable intellectual property modules in order to accelerate the controller design cycle. The design methodology and tool chain presented in this paper have been applied to the realization of a control system for solving the navigation tasks of an autonomous vehicle. [ABSTRACT FROM AUTHOR]

The complexity of many embedded software applications and their stringent performance requirements have reached a point where they can no longer be supported by conventional embedded-system architectures based on a single general-purpose processor. Nanometer fabrication technologies have made it feasible to integrate several embedded processors on a single chip to create multiprocessor systems-on-chip (MPSoCs) for a wide range of applications. It is already well known that, for embedded systems, customizing the processor to the application can significantly increase performance and energy efficiency. Single-chip heterogeneous multiprocessors, where the different processors are customized to the tasks they perform, are thus attracting attention. Despite their significant potential, a primary bottleneck to their adoption remains the development of programming paradigms and tools to alleviate the design complexity. Some advances have been made in the areas of custom multiprocessor architecture, tool support, and design methodology in order to reduce the design turnaround time. However, because of the heterogeneity of the custom processors, the designers are still required to manually map the application tasks to the different processors and, at the same time, customize each processor so that the overall performance requirements are satisfied. A multilevel custom multiprocessor-synthesis methodology to perform the assignment and scheduling of the application tasks on the various processors together with processor customization in an integrated manner is proposed. This paper focuses on extensible processors, which provide a good tradeoff between efficiency, flexibility, and design turnaround time, by combining a configurable base processor with hardware that implements custom instructions to extend its instruction set. This paper motivates the need for such an integrated approach by demonstrating that custom-instruction selection has complex interdependencies with task assignment and scheduling, and performing these steps independently often results in significant degradation in the quality of the synthesized multiprocessor architecture. The methodology presented here uses an iterative improvement algorithm to first assign and schedule tasks on processors and then select custom instructions along the critical path. It utilizes the concept of ‘expected execution time’ to connect these two steps. It not only considers the currently selected custom instructions for the current task assignment and schedule, but also the possibility of better custom instructions being selected in future iterations. The methodology presented here is also enhanced to integrate task-level software pipelining to further increase the parallelism in the task graph and provide opportunities for multiprocessing. In this paper, the proposed heterogeneous multiprocessor-synthesis methodology is implemented in the context of a commercial extensible-processor design flow, using the Xtensa platform from Tensilica Inc. The presented tool was evaluated by automatically generating custom multiprocessor architectures for several complex embedded software benchmarks. The results show that architectures synthesized by the proposed methodology demonstrate an average speedup of 2.0 × (up to 2.9 ×) compared to symmetric multiprocessor architectures in which the processors have not been augmented with custom instructions. To the best of the authors' knowledge, this is the first tool for the synthesis of custom MPSoCs using extensible processors. [ABSTRACT FROM AUTHOR]

Continuous advances in silicon technology enable the development of complex System-on-Chip as cooperation among Digital Signal Processors (DPSs), General Purpose Processors (GPPs), and specific hardware components. The impact of this choice is not only limited to the target architecture, but also encompasses the overall system specification. It is thus crucial to manage such a complexity using high-level specification languages and a tool chain supporting the designer throughout a set of strategic decisions, such as the identification of a set of possible target architectures, the verification of the correctness of the specification, and the partitioning of the specification onto a set of computational resources. This paper addresses this type of problem by proposing a design flow supporting the system-level design of heterogeneous multiprocessor system-on-chip (MP-SoC), by extracting information from the system description (e.g., SystemC)—statically and in a fast manner—and by providing a set of quantitative measures correlating the type of executor, the functionality, and a timing estimation. Partitioning and architecture selection are built on top of this data and the final analysis of the selected Hardware-Software solution over the identified candidates is finally submitted to a timing verification via simulation. Note that the possibility of actually performing a comprehensive design space exploration, in general, is tightly influenced by the interaction between partitioning/architecture-selection and timing simulation in the design flow; for this reason, the description of this aspect is particularly emphasized in the presentation of the methodology. To show the applicability of the proposed methodology, two relevant case studies are described in the paper. [ABSTRACT FROM AUTHOR]

With more embedded systems networked, it becomes an important problem to effectively defend embedded systems against buffer overflow attacks. Due to the increasing complexity and strict requirements, off-the-shelf software components are widely used in embedded systems, especially for military and other critical applications. Therefore, in addition to effective protection, we also need to provide an approach for system integrators to efficiently check whether software components have been protected. In this paper, we propose the HSDefender (Hardware/Software Defender) technique to perform protection and checking together. Our basic idea is to design secure call instructions so systems can be secured and checking can be easily performed. In the paper, we classify buffer overflow attacks into two categories and provide two corresponding defending strategies. We analyze the HSDefender technique with respect to hardware cost, security, and performance. We experiment with our HSDefender technique on the SimpleScalar/ARM simulator with benchmarks from MiBench, an embedded benchmark suite. The results show that our HSDefender technique can defend a system against more types of buffer overflow attacks with less overhead compared with the previous work. [ABSTRACT FROM AUTHOR]

Due to the critical role played by data memory subsystems in the performance and energy efficiency of embedded systems, the design of energy-efficient data memory architectures has received considerable attention in recent years. In this paper, we propose a novel special-purpose data memory subsystem called Xtreain-Fit which is aimed at achieving high energy-delay efficiency for streaming media applications. A key novelty of Xtream-Fit is that it exposes a single customization parameter, thus enabling a very simple and yet effective design space exploration methodology. A second key contribution of this paper is the ability to achieve very high energy-delay efficiency through a synergistic combination of: 1) special purpose memory subsystem components, namely, a streaming memory and a scratch-pad memory and (2) a novel task-based execution model that exposes/enhances opportunities for efficient prefetching, and aggressive dynamic energy conservation techniques targeting on-chip and off-chip memory components. Extensive experimental results show that Xtream-Fit reduces the energy-delay product by 22% to 61%, as compared to general-purpose memory sub- systems enhanced with state of the art cache decay and SDRAM power-mode control policies. [ABSTRACT FROM AUTHOR]

This paper introduces a new class of finite memory compaction schemes called convolutional compactors (CCs). They provide compaction ratios of test responses in excess of 100 ×, even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. The CCs can also be used to significantly enhance conventional multiple input signature registers. Experimental results presented in the paper demonstrate the efficiency of convolutional compaction for several industrial circuits. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient hardware architecture to accelerate adaptive deblocking filter of H.264/AVC video coding. Compact data access unit, Line-of- Pixel (LOP) is defined in this paper. Line-of-Pixel and build- in data buffer are employed to simplify data exchange between deblocking filter and outside data memory. Edge filter, which is designed to process each group of pixels on both sides of one edge, is kernel of deblocking filter. It is implemented in multiple parallel pipelines to increase efficiency. By carefully design, the proposed deblocking filter can be embedded in general-purpose processor or DSP to support special instructions for acceleration of software codec. This filter also can be used to full hardware H.264/AVC codec. [ABSTRACT FROM AUTHOR]

In recent years, the advances in wireless communication and electronics have accelerated to develop many wireless network solutions to replace existing wired networks. A wireless network solution can support mobility and flexibility of nodes in a network. Especially in sensor networks, it has many advantages to replace cables with wireless logical links. On the other hand, Bluetooth is generally considered as a promising short-range wireless technology because of its inexpensive cost, low power and small size, and thus Bluetooth has been gaining increasing interest from various industries. For the above reasons, we adopt Bluetooth technology for a wireless sensor network which is designed for security systems. Since Bluetooth will continue to be a feature found in many devices, it is worthwhile to investigate its use in wireless sensor networks. In this paper, we describe a Bluetooth wireless sensor network for security systems, which includes the implementation issues about system architecture, power management, self- configuration of network, and routing. We think that the methods or algorithms described in this paper can be easily applied to other embedded Bluetooth applications for wireless networks. [ABSTRACT FROM AUTHOR]

Application-specific instruction set processor (ASIP) design is a promising technique to meet the performance and cost goals of high-performance systems. ASIPs are especially valuable for embedded computing applications (e.g., digital cameras, color printers, cellular phones, etc.) where a small increase in performance and decrease in cost can have a large impact on a product's viability. Sutherland, Sproull, and Molnar originally proposed a processor organization called the counterflow pipeline (CFP) as a general-purpose architecture. We observed that the CFP is appropriate for ASIP design due to Its simple and regular structure, local control and communication, and high degree of modularity. This paper describes a new CFP architecture, called the wide counterflow pipeline (WCFP), that extends the original proposal to be better suited for custom embedded instruction-level parallel processors. This work presents a novel and practical application of the CFP to automatic and quick turnaround design of ASIPs. The paper introduces the WCFP architecture and describes several microarchitecture capabilities needed to get good performance from custom WCFPs. We demonstrate that custom WCFPs have performance that is up to four times better than that of ASIPs based on the CFP. Using an analytic cost model, we show that custom WCFPs do not unduly increase the cost of the original counterflow pipeline architecture, yet they retain the simplicity of the CFP. We also compare custom WCFPs to custom VLIW architectures and demonstrate that the WCFP is performance competitive with traditional VLIWs without requiring complicated global interconnection of functional devices. [ABSTRACT FROM AUTHOR]

Cyber-Physical Systems (CPS) integrate discrete-time computing and continuous-time physical-world entities, which are often wirelessly interlinked. The use of wireless safety-critical CPS requires safety guarantees despite communication faults. This paper focuses on one important set of such safety rules: Proper-Temporal-Embedding (PTE), where distributed CPS entities must enter/leave risky states according to properly nested temporal pattern and certain duration spacing. Our solution introduces hybrid automata to formally describe and analyze CPS design patterns. We propose a novel leasing based design pattern, along with closed-form configuration constraints, to guarantee PTE safety rules under arbitrary wireless communication faults. We propose a formal procedure to transform the design pattern hybrid automata into specific wireless CPS designs. This procedure can effectively isolate physical world parameters from affecting the PTE safety of the resultant specific designs. We conduct two wireless CPS case studies, one on medicine and the other on control, to show that the resulted system is safe against communication failures. We also compare our approach with a polling based approach. Both approaches support PTE under arbitrary communication failures. The polling approach performs better under severely adverse wireless medium conditions; while ours performs better under benign or moderately adverse wireless medium conditions. [ABSTRACT FROM AUTHOR]

Several courses on embedded systems have been planned and taught to students in Electrical Engineering and Computer Science Master's programs. The tutorials play an important role in these courses, not only to motivate the students, but also to expose them to the difficulties and challenges of designing real embedded systems. This paper presents a complete lab project used over the last 15 years in a semester-long course on embedded systems that, for historical reasons, was titled Computer Electronics. This project involves all the topics studied in this course, namely programmable, configurable and dedicated processors, memory technology and organization, peripherals, and the design and implementation of complete embedded systems. Targeting image processing as a case study, in this lab project students use field programmable gate arrays (FPGAs) to design real-time embedded systems based on soft-cores, hardware accelerators, and specific input and output peripherals. Analyzing the results over the last years, it can be concluded that the inclusion of this transversal lab project boosts the interest in this Master's course and encourages the students to learn the topics required to design real embedded systems. [ABSTRACT FROM AUTHOR]

The application of model checking for the formal verification of distributed embedded systems requires the adoption of techniques for realistically modeling the temporal behavior of such systems. This paper discusses how to model with timed automata the different types of relationships that may be found among the computer clocks of a distributed system, namely, ideal clocks, drifting clocks, and synchronized clocks. For each kind of relationship, a suitable modeling pattern is thoroughly described and formally verified. [ABSTRACT FROM PUBLISHER]

Addressing power and energy consumption related issues early in the system design flow ensures good design and minimizes iterations for faster turnaround time. In particular, optimizations at software level, e.g., those supported by compilers, are very important for minimizing energy consumption of embedded applications. Recent research demonstrates that voltage islands provide the flexibility to reduce power by selectively shutting down the different regions of the chip and/or running the select parts of the chip at different voltage/frequency levels. As against most of the prior work on voltage islands that mainly focused on the architecture design and IP placement related issues, this paper studies the necessary software compiler support for voltage islands. Specifically, we focus on an embedded multiprocessor architecture that supports both voltage islands and control domains within these islands, and determine how an optimizing compiler can automatically map an embedded application onto this architecture. Such an automated support is critical since it is unrealistic to expect an application programmer to reach a good mapping correlating multiple factors such as performance and energy at the same time. Our experiments with the proposed compiler support show that our approach is very effective in reducing energy consumption. The experiments also show that the energy savings we achieve are consistent across a wide range of values of our major simulation parameters. [ABSTRACT FROM AUTHOR]

In this paper, we present the systematic design and implementation of a robust real-time embedded vision system for an unmanned rotorcraft for ground target following. The hardware construction of the vision system is presented, and an onboard software system is developed based on a multithread technique capable of coordinating multiple tasks. To realize the autonomous ground target following, a sophisticated feature-based vision algorithm is proposed by using an onboard color camera and navigation sensors. The vision feedback is integrated with the flight control system to guide the unmanned rotorcraft to follow a ground target in flight. The overall vision system has been tested in actual flight missions, and the results obtained show that the overall system is very robust and efficient. [ABSTRACT FROM PUBLISHER]

The precision time synchronization protocol daemon (PTPd) is a software package that realizes a PTP. In this paper, a traceable PTPd measurement system is examined. The key component of the proposed time measurement system is the PTPd. It runs in a Linux kernel-based network. The PTPd operation mode is free running. A stable clock (i.e., an embedded system oscillator in our experiments) plays the role of a master clock. Measured clocks (i.e., desktop system time in our experiments) play the roles of slave clocks. From our results, we find that the system clock of an embedded system and desktop computers all accord with the demand of the PTPd, and the PTPd can be used as a software time measurement tool in the submicrosecond range. [ABSTRACT FROM AUTHOR]

A basic understanding of technology is recognized as important knowledge even for students not connected with engineering and computer science. This paper shows that embedded system concepts can be taught in a technological literacy course. An embedded system teaching block that has been used in an electronics module for non-engineers is presented. It comprises 1 h of lecturing and 3 h of hands-on lab work. Feedback and evaluation show that students are able to gain a basic understanding of the topic even in such a limited time. [ABSTRACT FROM AUTHOR]

Early exposure to embedded computing systems is crucial for students to be prepared for the embedded computing demands of today's world. However, exposure to systems knowledge often comes too late in the curriculum to stimulate students' interests and to provide a meaningful difference in how they direct their choice of electives for future education and careers. This paper describes an experience with integrating embedded computing systems education into high school and early undergraduate curricula to give students that needed early exposure. It provides assessment data that illustrates the success and limitations of the efforts described as well as the lessons they hold for a reform of the undergraduate curriculum and its impact on high school education. [ABSTRACT FROM AUTHOR]

In this paper, we aim to improve the performance and power metrics of packet-switched network-on-chips (NoCs) and benefits from the scalability and resource utilization advantages of NoCs and superior communication performance of point-to-point dedicated links. The proposed method sets up the virtual point-to-point (VIP) connections over one virtual channel which bypasses the entire router pipeline) at each physical channel of the NoC. We present two schemes for constructing such VIP circuits. In the first scheme, the circuits are constructed for an application based on its task-graph at design time. The second scheme addresses constructing the connections at runtime using a light-weight setup network. It involves monitoring the NoC traffic in order to detect heavy communication flows and setting up a VIP connection for them using a run-time circuit construction mechanism. The proposed mechanism is compared to a traditional packet-switched NoC and some modern switching mechanisms and the results show a significant reduction in the network power and latency over the other considered NoCs. [ABSTRACT FROM AUTHOR]

This paper presents the design of distributed embedded systems using the synchronous multiclock model of the SIGNAL language. It proposes a methodology that ensures a correct-by-construction functional implementation of these systems from high-level models. It shows the capability of the synchronous approach to apply formal techniques and tools that guarantee the reliability of the designed systems. Such a capability is necessary and highly worthy when dealing with safety-critical systems. The proposed methodology is demonstrated through a case study consisting of a simple avionic application, which aims to pragmatically help the reader to understand the manipulated formal concepts, and to apply them easily in order to solve system correctness issues encountered in practice. The application functionality is first modeled as well as its distribution on a generic hardware architecture. This relies on the endochrony and endo-isochrony properties of SIGNAL specifications, defined previously. The considered architectures include asynchronous communication mechanisms, which are also modeled in SIGNAL and proved to achieve message exchanges correctly. Furthermore, the synchronizability of the different parts in the resulting system is addressed after its deployment on a specific execution platform with multirate clocks. After all these steps, a distributed code can be automatically generated. [ABSTRACT FROM AUTHOR]

Wireless sensor networks are typically deployed to monitor phenomena that vary over the spatial region the sensor network covers. The sensor readings may also be dual-used for additional purposes. In this paper, we propose to use the inherent spatial variability in physical phenomena, such as temperature or ambient acoustic energy, to support localization and position verification. We first present the problem of localization using general spatial information fields, and then, propose a theory for exploiting this spatial variability for localization. Our Spatial Correlation Weighting Mechanism (SCWM) uses spatial correlation across different phenomena to isolate an appropriate subset of environmental parameters for better location accuracy. We then develop an array of algorithms employing environmental parameters using a two-level approach: first, we develop the strategies on how the subset of parameters should be chosen, and second, we derive mapping functions for position estimation. Our algorithms support our theoretical model for performing localization utilizing environmental properties. Finally, we provide an experimental evaluation of our approach by using a collection of physical phenomena measured across 100 locations inside a building. Our results provide strong evidence of the viability of using general sensor readings for location-aware applications. [ABSTRACT FROM AUTHOR]

Although many data hiding methods are proposed in the literature, all of them distort the quality of the host content during data embedding. In this paper, we propose a novel data hiding method in the compressed video domain that completely preserves the image quality of the host video while embedding information into it. Information is embedded into a compressed video by simultaneously manipulating Mquant and quantized discrete cosine transform coefficients, which are the significant parts of MPEG and H.26x-based compression standards. To the best of our knowledge, this data hiding method is the first attempt of its kind. When fed into an ordinary video decoder, the modified video completely reconstructs the original video even compared at the bit-to-bit level. Our method is also reversible, where the embedded information could be removed to obtain the original video. A new data representation scheme called reverse zerorun length (RZL) is proposed to exploit the statistics of macroblock for achieving high embedding efficiency while trading off with payload. It is theoretically and experimentally verified that RZL outperforms matrix encoding in terms of payload and embedding efficiency for this particular data hiding method. The problem of video bitstream size increment caused by data embedding is also addressed, and two independent solutions are proposed to suppress this increment. Basic performance of this data hiding method is verified through experiments on various existing MPEG-1 encoded videos. In the best case scenario, an average increase of four bits in the video bitstream size is observed for every message bit embedded. [ABSTRACT FROM AUTHOR]

This paper presents new embedded system architecture (ESA) for improving the voice quality in a WLAN/Cellular dual-mode mobile phone. The proposed architecture is based on a dual-core scheme and its main functional blocks are composed of VoIP Remote Procedure Call (VRPC), an audio bridging scheme, and a Server-Assisted Call Management (SACM) algorithm. In order to illustrate the aims of the proposed approach, prototype systems are implemented, and evaluated by measuring average Mean Opinion Score (MOS), and Mouth-To-Ear (M2E) delay. The experimental results show that the proposed approach results in greatly improved voice quality. [ABSTRACT FROM AUTHOR]

The use of NAND flash memory for building permanent storage has been increasing in many embedded systems due to idiosyncrasies such as non-volatility and low energy consumption. The persistent requirements for high storage capacity have given rise to the increase of bit density per cell as in multi-level cells but this has come at the expense of performance and has resulted in degradation of durability. in this paper, we introduce a complementary approach to boost the performance and durability of MLC-based storage systems by employing a non-volatile buffer that temporarily holds the data heading to MLCs. We also propose algorithms to efficiently eliminate unnecessary write and erase operations in MLCs by performing a pre-merge in the buffer. Our experiments show that the proposed approach can decrease average response time by up to 4 times and increase durability by 4 times by adding only a small hardware cost. [ABSTRACT FROM AUTHOR]

This paper presents the novel development of an embedded system that aims at digital TV content recommendation based on descriptive metadata collected from versatile sources. The described system comprises a user profiling subsystem identifying user preferences and a user agent subsystem performing content rating. TV content items are ranked using a combined multimodal approach integrating classification-based and keyword-based similarity predictions so that a user is presented with a limited subset of relevant content. Observable user behaviors are discussed as instrumental in user profiling and a formula is provided for implicitly estimating the degree of user appreciation of content. A new relation-based similarity measure is suggested to improve categorized content rating precision. Experimental results show that our system can recommend desired content to users with significant amount of accuracy. [ABSTRACT FROM AUTHOR]

NAND flash memory has been widely used for storage in embedded systems and recently in enterprise computing environment, owing to its shock-resistance, non- volatile, low energy consumption, and high I/O speed. In addition, flash memory has the characteristics of not-in-place update and asymmetric I/O costs among read, write, and erase operations, in which the cost of write/erase operations is much higher than that of read operation. Hence, the buffer replacement algorithms in flash-based systems should take the asymmetric I/O costs into account. Previous solutions to this issue, such as CFLRU and LRU-WSR, used a clean-first scheme to first evict clean pages from the buffer. Although they outperform the traditional LRU policy in performance, they do not consider the access frequency of clean page, which will consequently result in poor I/O performance. In order to solve this problem, we present a new buffering algorithm in this paper, called CCF-LRU, which enhances the previous CFLRU and LRU-WSR methods by differentiating clean pages into cold and hot ones, and evicting cold clean pages first and delaying the eviction of hot clean pages. We conduct a trace-driven experiment on a flash memory simulation environment, and use six types of synthesized traces as well as a real OLTP trace. The results show that the CCF-LRU algorithm outperforms LRU, CFLRU and LRU-WSR in write count and runtime in all experiments. In particular, it provides more than 20% improvement over its competitors both in write count and runtime, when running the real OLTP trace. [ABSTRACT FROM AUTHOR]

This paper presents a hardware realization of an adaptive fuzzy controller (AFC) for a permanent-magnet linear synchronous motor (PMLSM) drive system based on the field- programmable gate-array (FPGA) technology. First, a mathematics model of the PMLSM drive is defined; then, to increase the performance of the PMLSM drive system, an AFC constructed by a fuzzy basis function and a parameter-adjustable mechanism is applied to the position-control loop of the PMLSM drive system to cope with the effect of the system dynamic uncertainty and the external load. A point-to-point (PTP) motion trajectory designed with the trapezoidal velocity profile is considered to smooth the move of the PMLSM at the start and stop conditions. Second, a finite-state machine (FSM) joined by a multiplier, an adder, a lookup table, and some comparators and registers is presented to model the overall AFC, and a VHSIC hardware description language is adopted to describe the circuit of the FSM. In addition, a Nios II embedded processor is used to implement the function of the PTP motion-trajectory algorithm by software. Finally, an experimental system is established to verify the effectiveness of the proposed FPGA-based AFC and the PTP motion-control system, and some experimental results are confirmed theoretically. [ABSTRACT FROM AUTHOR]

The memory system presents one of the critical challenges in embedded system design and optimization. This is mainly due to the ever-increasing code complexity of embedded applications and the exponential increase seen in the amount of data they manipulate. The memory bottleneck is even more important for multiprocessor-system-on-a-chip (MPSoC) architectures due to the high cost of off-chip memory accesses in terms of both energy and performance. As a result, reducing the memory-space occupancy of embedded applications is very important and will be even more important in the next decade. While it is true that the on-chip memory capacity of embedded systems is continuously increasing, the increases in the complexity of embedded applications and the sizes of the data sets they process are far greater. Motivated by this observation, this paper presents and evaluates a compiler-driven approach to data compression for reducing memory-space occupancy. Our goal is to study how automated compiler support can help in deciding the set of data elements to compress/decompress and the points during execution at which these compressions/decompressions should be performed. We first study this problem in the context of single-core systems and then extend it to MPSoCs where we schedule compressions and decompressions intelligently such that they do not conflict with application execution as much as possible. Particularly, in MPSoCs, one needs to decide which processors should participate in the compression and decompression activities at any given point during the course of execution. We propose both static and dynamic algorithms for this purpose. In the static scheme, the processors are divided into two groups: those performing compression/decompression and those executing the application, and this grouping is maintained throughout the execution of the application. In the dynamic scheme, on the other hand, the execution starts with some grouping but this grouping can change during the course of execution, depending on the dynamic variations in the data access pattern. Our experimental results show that, in a single-core system, the proposed approach reduces maximum memory occupancy by 47.9% and average memory occupancy by 48.3% when averaged over all the benchmarks. Our results also indicate that, in an MPSoC, the average energy saving is 12.7% when all eight benchmarks are considered. While compressions and decompressions and related bookkeeping activities take extra cycles and memory space and consume additional energy, we found that the improvements they bring from the memory space, execution cycles, and energy perspectives are much higher than these overheads. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel distributed interleaved random space-time code (IR-STC) designed for multisource cooperation (MSC) employing various relaying techniques, namely, amplify-forward, decode-forward, soft decode-forward, and differential decode-forward. We introduce a two-phase communication regime for our IR-STC-aided MSC and propose a novel structured embedded (SE) random interleaver- generation method. We also characterize the achievable performance of our proposed IR-STC design in conjunction with various relaying techniques communicating over different intersource Nakagami-m fading channels. [ABSTRACT FROM AUTHOR]

Recent field-programmable gate array (FPGA) architectures are heterogeneous, owing to the presence of millions of gates in configurable logic blocks (CLBs), block RAMs, and multiplier blocks (MULs) which can host fairly large designs. While their physical design calls for floorplanning, the traditional algorithms for application-specific integrated circuits (ASIC) do not suffice. In this paper, we propose a three-phase algorithm for unified floorplan-topology generation and sizing on heterogeneous FPGAs. The method consists of a recursive balanced bipartitioning followed by the generation of slicing topologies and finally the allocation of CLBs and RAM/MULs to modules by a greedy heuristic and minimum-cost maximum-flow method, respectively. Experimental results on benchmark circuits show that our method HeteroFloorplan produces feasible floorplans within a few seconds with total half-perimeter wirelength (HPWL) improvement of 18%-52% over the very few previous approaches. We also compare our locally greedy CLB allocation with a network-flow formulation to establish its effectiveness. [ABSTRACT FROM AUTHOR]

This paper presents an embedded digital system for incremental encoders allowing for high dynamic performance and accuracy speed measurement in all the operating conditions for the application in digital servo drives. The idea aims at embedding processing capabilities inside traditional position transducers in order to develop a smart measuring system. The base processing algorithm employs a novel mixed time and frequency measurement technique of the encoder signals. The iterative formulation of the algorithm and the limited hardware requirements allows its implementation by means of a standard microcontroller (e.g., TMS32OF24x) or by dedicated hardware. Communication between the smart sensor and the servo drive is preliminarily realized via high-speed serial peripheral interface. [ABSTRACT FROM AUTHOR]

Embedded systems are constrained by the available memory. Code-compression techniques address this issue by reducing the code size of application programs. It is a major challenge to develop an efficient code-compression technique that can generate substantial reduction in code size without affecting the overall system performance. We present a novel code-compression technique using bitmasks, which significantly improves the compression efficiency without introducing any decompression penalty. This paper makes three important contributions. 1) It develops an efficient bitmask-selection technique that can create a large set of matching patterns. 2) It develops an efficient dictionary-selection technique based on bitmasks. 3) It proposes a dictionary-based code-compression algorithm using the bitmask-and dictionary-selection techniques that can significantly reduce the memory requirement. To demonstrate the usefulness of our approach, we have performed code compression using applications from various domains and compiled for a wide variety of architectures. Our approach outperforms the existing dictionary-based techniques by an average of 20%, giving a compression ratio of 55%-65%. [ABSTRACT FROM AUTHOR]

Looping operations impose a significant bottleneck in achieving better computational efficiency for embedded applications. In this paper, a novel zero-overhead loop controller (ZOLC) supporting arbitrary loop structures with multiple-entry and multiple-exit nodes is described and utilized to enhance embedded RISC processors. A graph formalism is introduced for representing the loop structure of application programs, which can assist in ZOLC code synthesis. Also, a portable description of a ZOLC component which can be exploited in the scope of register transfer level (RTL) synthesis for enabling its utilization is given in detail. This description is designed to be easily retargetable to single-issue RISC processors, requiring only minimal effort for this task. The ZOLC unit has been incorporated into different RISC processor models and research ASIPs at different abstraction levels (RTL VHDL and ArchC) to provide effective means for low-overhead looping without negative impact to the processor cycle time. Average performance improvements of 25.5 percent and 44 percent are feasible for a set of kernel benchmarks on an embedded RISC and an application-specific processor, respectively. A corresponding 10 percent speedup is achieved on the same RISC for a subset of MiBench applications, not necessarily featuring the examined performance-critical kernels. [ABSTRACT FROM AUTHOR]

Deeds is a simulation environment for e-learning in digital electronics. The simulators cover combinational and sequential logic networks, finite state-machine design, and microcomputer interfacing and programming. They are integrated together, and therefore allow the design and test of embedded digital systems. The environment guides students' activities by delivering learning materials through specialized browsers. An extensive collection of learning materials is available. This paper includes an example of activity on a problem assignment. [ABSTRACT FROM AUTHOR]

In this paper, modular design of embedded feedback controllers using field-programmable gate array (FPGA) technology is studied. To this end, a novel distributed-arithmetic (DA)-based proportional—integral—derivative (PID) controller algorithm is proposed and integrated into a digital feedback control system. The DA-based PID controller demonstrates 80% savings in hardware utilization and 40% savings in power consumption compared to the multiplier-based scheme. It also offers good closed-loop performance while using less resources, resulting in cost reduction, high speed, and low power consumption, which is desirable in embedded control applications. The complete digital control system is built using commercial FPGAs to demonstrate the efficiency. The design uses a modular approach, so that some modules can be reused in other applications. These reusable modules can be ported into Matlab/Simulink as Simulink blocks for hardware/software cosimulation or integrated into a larger design in the Matlab/Simulink environment to allow for rapid prototyping applications. [ABSTRACT FROM AUTHOR]

Selective Huffman coding has recently been proposed for efficient test-data compression with low hardware overhead. In this paper, we show that the already proposed encoding scheme is not optimal and we present a new one, proving that it is optimal. Moreover, we compare the two encodings theoretically and we derive a set of conditions which show that, in practical cases, the proposed encoding always offers better compression. In terms of hardware overhead, the new scheme is at least as low-demanding as the old one. The increased compression efficiency, the resulting test-time savings, and the low hardware overhead of the proposed method are also verified experimentally. [ABSTRACT FROM AUTHOR]

High-speed datapaths in microprocessors and embedded processors contain complex floating-point (FP) arithmetic units which have a critical role in the processor's performance. Although the FP units' complex structure consists of classic integer arithmetic components, the embedded components encounter serious testability problems due to their limited accessibility from the FP unit ports and testability loss due to FP unit inherent operations, such as rounding and normalization. In this paper, we analyze the testability problems and present scalable test generation for FP units using as a demonstration vehicle the popular, high-speed, two-path architecture of the most complex unit, the FP adder. The key feature of the presented methodology is the identification of testability conditions that guarantee effective test pattern application and fault propagation for each of the components of the FP adder. The identified test conditions can be utilized with respect to any fault model and are independent of the internal structure and the size of the components. Thus, they can be applied to FP adders of various exponent and significand sizes (single, double, and custom precision), as well as to other types of FP units, which also consist of classic integer arithmetic components similarly interconnected. [ABSTRACT FROM AUTHOR]

In this paper, we present the simulation-based validation approach that we used during the design of ThumbPod-2, a portable fingerprint authentication system. The particular nature of secure system design has considerable impact on the simulation requirements and design flow. We present two key contributions. We will first show that rigorous design of secure digital systems requires a multilevel validation approach, meaning validation at multiple steps in the design flow. Indeed, an attacker chooses the easiest entry point and does not stick with one abstraction level. Second, we show the use of a cosimulation and codesign environment called GEZEL that can support this type of multilevel validation. We will illustrate this multilevel design validation strategy with the verification of security of the ThumbPod-2 device. [ABSTRACT FROM AUTHOR]

Truncation in digit-precision is a very important and common operation in embedded system design for bounding the required finite precision and for area-time-power savings. In this paper, we present the use of online arithmetic to provide truncated computations with communication systems as one of the applications. In contrast to truncation in conventional arithmetic, online arithmetic can truncate dynamically and produce both area and time benefits due to the digit-serial nature of computations. This is of great advantage in communication systems where the precision requirements can change dynamically with the environment. While truncation in conventional arithmetic can have significant truncation errors, especially when the output precision is less than the input precision, the redundancy and most significant digit first nature of online arithmetic restricts the truncation error to only the least significant digit of the truncated result. As an application that uses significant truncation in precision, a code matched filter detector for wireless systems is designed using truncated online arithmetic. The detector can provide both hard decisions and soft(er) decisions dynamically as well as interface with other conventional arithmetic circuits or act as a DSP coprocessor. Thus, optimized communication receivers with coexisting conventional arithmetic for saturation and online arithmetic for truncation can now be built. The truncated online arithmetic detector was also verified with a VLSI implementation in an AMI 0.5 # MOSIS tiny chip process. [ABSTRACT FROM AUTHOR]

Rich requirements from High Definition Television (HDTV) decoder argue the supports of complex architecture and Operating System (OS). As an embedded system, mult-processor System-on-a-Chip (MPSoC) is an ideal implementation of the decoder. Open source OS has many advantages to be ported to embedded fields. This paper describes the detailed process of its porting, including building environment, kernel modification, and debug. The porting specifications are constrained by the resources on the HDTV SoC platform, development period, debug efforts, and system robustness, etc. As an application of the open source OS, our work shows the joint of industry practice and theory research. [ABSTRACT FROM AUTHOR]

The VMEbus is an IEEE standard architecture upon which many embedded and real-time systems are built. The VMEbus architecture has existed for nearly 25 years and has been used extensively for military, industrial, and aerospace applications. This paper describes the general characteristics of the VMEbus architecture, specifically relating these characteristics to aspects of embedded systems education included as components of the IEEE/ACM CE2004 computer engineering model curriculum. Portions of this model curriculum are currently being implemented at universities across the country as part of an increasing effort to address the need for embedded systems education. This evaluation will identify the strengths and weaknesses of this architecture as a general-purpose embedded systems educational tool. The VMEbus architecture is used in the laboratory component of an undergraduate embedded systems course at the University of Alabama (UA), Tuscaloosa. The assessment results evaluating its effectiveness are presented. Index Terms-Computer architecture, computer engineering education, educational technology, embedded systems. [ABSTRACT FROM AUTHOR]

Existing approaches for modular manufacturing test of core-based system-on-a-chip (SOC) devices do not provide any explicit mechanism for delivering two-pattern tests in the broadside mode, which is necessary to achieve reliable coverage of delay and stuck-open faults. Although wrapper input cells can be enhanced with two memory elements to address this problem, this will incur a large test area overhead. This paper proposes a novel architecture for broadside two-pattern test of core-based SOCs without any loss in fault coverage and without increasing the size of the wrapper input cells. The proposed solution combines the dedicated bus-based test access mechanism and functional interconnects for test data transfer in order to provide full controllability of the wrapper input cells in the two consecutive clock cycles required by two-pattern testing. New algorithms for test access mechanism design and test scheduling are proposed and design trade-offs between test area and testing time are discussed using experimental results. [ABSTRACT FROM AUTHOR]

The sheer complexity of today's embedded systems forces designers to start with modeling and simulating system components and their interactions in the very early design stages. It is therefore imperative to have good toots for exploring a wide range of design choices, especially during the early design stages, where the design space is at its largest. This paper presents an overview of the Sesame framework, which provides high-level modeling and simulation methods and tools for system-level performance evaluation and exploration of heterogeneous embedded systems. More specifically, we describe Sesame's modeling methodology and trajectory. It takes a designer systematically along the path from selecting candidate architectures, using analytical modeling and multiobjective optimization, to simulating these candidate architectures with our system-level simulation environment. This simulation environment subsequently allows for architectural exploration at different levels of abstraction while maintaining high- level and architecture-independent application specifications. We illustrate all these aspects using a case study in which we traverse Sesame's exploration trajectory for a Motion-JPEG encoder application. [ABSTRACT FROM AUTHOR]

In this paper, error-resilient video coding schemes based on data-embedding techniques are proposed for the H.263+ codec. Data embedding, popularly applied to secret hiding and digital watermarking, is now used to convey error recovery information to the decoder via a covert channel, without causing significant increase in transmission bitrate. Our embedded information provides implicit macroblock (MB) delimiters for resynchronization in presence of channel errors. In this way, the decoder is capable of isolating erroneous MBs with the extracted information. A set of variational schemes is proposed, extensively analyzed, and compared to the competitive counterparts (e.g., the original H.263+ TMN8 and its synchronization-enhanced version) at the same bitrate. Experimental results show that our data embedding process decreases the average peak signal-to-noise ratio (PSNR) in error-free conditions by 0.3 dB (light data embedding) to 1.8 dB (heavy data embedding), but it is capable of achieving a significant PSNR improvement up to 2 and 9.5 dB when the bit error rate is 10-5 and 10-3 respectively. We also provide suggestions of how to adaptively apply the proposed schemes for different channel error conditions and different video contents. [ABSTRACT FROM AUTHOR]