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This paper presents a novel control strategy to significantly reduce the high-frequency transformer loss in a modular solid-state transformer (SST) based converter system. The modular SST design is based on an ac–dc power-electronic building block comprised of an H-bridge at the ac input and a bidirectional soft-switching isolated dc–dc converter with a medium-voltage insulated high-frequency transformer. The ac terminals of input H-bridges are connected in series and directly coupled to the medium-voltage ac line, while the output dc terminals are all connected in parallel at a low voltage. The key innovation described in this paper, without sacrificing the output performance, is the control scheme that reduces core and winding losses associated with the dc–dc resonant stage by turning off the selected dc–dc converters in synchronism with the line voltage. The prototype for the test described in this paper is based on a modular SST where each module is rated at 50 kVA, with a 200 kHz transformer using 1.7 kV silicon carbide discrete mosfets, but the described control concepts are more broadly applicable to similar topologies. [ABSTRACT FROM AUTHOR]

This paper presents a new six-level flying capacitor based (FC-based) multilevel converter with one dc source and the capability of operating in all power factors and modulation indexes. Multilevel converters with one dc voltage source are attractive in many applications as they do not need rather expensive and bulky multiwinding input transformer connection at the dc side. On the other hand, not all classic multilevel converters with one dc source can produce any desirable number of output voltage levels at all power factors and/or modulation indexes. In this paper, a hybrid structure is proposed in which six voltage levels can be realized at the ac terminals. The modulation technique and the control strategy for the FC voltage balancing are presented. To show the advantages of the proposed converter, different performance criteria, such as switch count and rating, the size of capacitors, switching frequency, and power losses, are compared with other existing six-level topologies. The results indicate that the proposed structure is superior to other six-level converters from different standpoints. Simulation results are used to further evaluate the performance of the proposed converter. A laboratory-type experimental setup is used to validate the theoretical results. [ABSTRACT FROM AUTHOR]

Induction motor drives operated with a low ratio of the switching frequency to the fundamental frequency (i.e., pulse number) are prone to have high magnitudes of low-order torque harmonics. This paper proposes a method to analytically evaluate the harmonic torque spectrum based on the pulsewidth-modulated voltage waveforms for low pulse number operation. The predicted torque harmonic spectra for different pulsewidth-modulated waveforms are validated through simulations and experiments. This paper also reports optimal switching angles to minimize the total rms value of torque harmonics of order 6, 12, 18 $,\dots,$ $6(N-1)$ , considering the number of switching angles per quarter ($N$) to be 4 and 5. Compared to sine triangle pulsewidth modulation and selective harmonic elimination pulsewidth modulation with the same pulse number, the proposed optimal switching angles significantly reduce the total rms value of all harmonic torques of order lower than $6N$. Extensive simulation and experimental results on a 3.7-kW induction motor drive are presented to demonstrate the superior performance of the proposed optimal pulsewidth modulation. [ABSTRACT FROM AUTHOR]

The selective harmonic current mitigation pulsewidth modulation (SHCM-PWM) technique can be used in cascaded multilevel converters to extend the harmonic reduction spectrum, reduce the coupling inductance and increase the efficiency. The offline SHCM-PWM technique has small number of switching transitions as its switching angles can only change once in a fundamental cycle and relatively long time delays because it uses FFT. As a result, its dynamic response has a lot to desire. As it will be proven in this paper, in four-quadrant power converters, to have a good transient dynamic response, both active and reactive power must be controlled at least two times in a fundamental cycle. In this paper, a hybrid modulation technique is introduced. The proposed technique uses SHCM-PWM under steady state and phase-shift PWM (PSPWM) under transient. In addition, in order to extend the modulation index range and ensure that SHCM-PWM can process four-quadrant active and reactive power, the constraints of the switching angles for the SHCM-PWM are modified. Simulations and experiments are conducted on a seven-level cascaded H-bridge converter to verify the proposed technique. [ABSTRACT FROM PUBLISHER]

Wide bandgap semiconductor switches have been increasingly utilized to improve the power density and efficiency of power converters, as such devices are able to operate at very high frequencies, e.g., up to 100 MHz, with reduced power losses. However, such a high-frequency operation may impose a challenge to the digital control system, and the system clock frequency should be up to 100 GHz in high-precision applications, which is difficult to realize in low-cost microprocessors. Instead of using extremely high-frequency clocks, preprocessing-based solutions that utilize digital pulse-width-modulated (DPWM) dither techniques can also enhance the DPWM resolution with moderate frequency clocks. Unfortunately, this is usually achieved at the expense of introducing low-frequency harmonics, which may complicate system controller and output filter design. In this paper, an optimal dither technique is proposed to enhance the resolution of DPWM power converters. The concepts of positive dither and negative dither are first proposed in this paper. Furthermore, vector-diagram-based analysis indicates that with proper utilization of positive dithers and negative dithers and carefully selected dither sequences, the lowest order harmonic introduced by the conventional dither technique can be completely eliminated when the dither period is multiples of six switching periods. In other cases, the proposed optimal dither technique can produce minimized lowest order harmonic. Finally, experimental results obtained from a Gallium Nitride (GaN) devices-based synchronous buck converter validate the feasibility of the proposed dither technique. [ABSTRACT FROM PUBLISHER]

This paper proposed a new half-bridge (HB) LLC resonant converter family with pulse-width modulated (PWM) auxiliary switch (sLLC converter) for hold-up mode operation. The proposed sLLC converters could operate with synchronous rectifier, which is suitable for low-output voltage applications. In the proposed converters, an auxiliary switch is added at the primary side to provide charging path for the series resonant inductor. For nominal 400-V input, sLLC achieves same performance as conventional LLC converter, and all the good features such as soft switching are naturally retained. For slight input voltage fluctuation, frequency modulation is used to regulate the output voltage. When the input voltage reduces further, HB switches will operate at constant minimum frequency, and the auxiliary switch will operate in the PWM mode to energize the resonant inductor with the bus voltage directly during hold-up period. Thus, the converter achieves higher voltage gain, and the output voltage can be maintained at desired level. To verify the effectiveness of the proposed sLLC converter, operational principle and equivalent circuits will be carefully explained and analyzed in this paper. A 300-W prototype is built for 250–400-V input 12-V output application. [ABSTRACT FROM AUTHOR]

The three-level neutral point-clamped (NPC) converter has attracted much attention in high-power medium-voltage applications, but it is well-known that the NPC topology suffers from unequal power loss distribution among its semiconductor devices. The power loss unbalance problem becomes especially severe when the converter is operating at low fundamental frequencies. To overcome the loss unbalance problem of the NPC converter, the active NPC (ANPC) technique was introduced. However, it is demonstrated in this paper that in many cases, the conventional modulation method for the ANPC converter only marginally relieves the loss unbalance problem. This paper proposes a new modulation scheme (named the adaptive doubled frequency modulation) for the three-level ANPC converter, which significantly improves the power loss and thermal sharing among the semiconductor devices. The basic idea of the proposed scheme is adaptively adjusting the duty cycles of the switching states for every switching cycle, so as to optimize the power loss distribution. Simulation and experimental results verify this new method. [ABSTRACT FROM AUTHOR]

This paper proposes a multilevel series compensator (MSC) to deal with voltage sags/swells, harmonic compensation, or reactive power compensation. Such a device can be considered as a dynamic voltage restorer or a series active power filter (Series-APF). The MSC can improve the power quality of loads located in stiff systems. The configuration is based on three-phase bridge (TPB) converters connected by means of cascaded single-phase transformers. This arrangement permits the use of a single dc-link. A generalization for $K$ -stages in which $K$ -transformers are coupled with $K$-TPB converters is presented. The topology permits generating a high number of levels in the voltage waveforms with a low number of power switches in comparison with a classic topology. The multilevel waveforms are generated by the converters through a suitable pulsewidth modulation (PWM) strategy that takes into consideration the transformer turns ratios. Modularity and simple maintenance make the proposed MSC an attractive solution compared with some conventional configurations. Model, PWM strategy, and overall control are discussed in this paper. Simulation and experimental results are presented as well. [ABSTRACT FROM PUBLISHER]

Pulse-width-modulated (PWM) converters have been widely applied for power processing, and they are typically the stems of other types of converters, such as quasi-resonant, Z-source, and switched-inductor hybrid converters. Development of PWM converters has been spanning over a century, starting from the buck converter. The well-known PWM converters include buck, boost, buck–boost, Ćuk, single ended primary inductive converter (SEPIC), zeta, Z-source, quasi-Z source, etc. Many attempts have been proposed to develop these converters based mostly on canonical cell concepts and by introducing extra LC filters to the cells. This paper presents an enhancement to the layer and graft schemes by introducing the ideas of dc voltage/current offsetting, capacitor/inductor component splitting, diode grafting, and inverse operation of PWM converters. The PWM converters, which can be operated in continuous conduction mode (CCM) or discontinuous conduction mode (DCM), therefore can be synthesized systematically according to decoded transfer gains. Decoding and synthesizing PWM converters uniquely bridge transfer gains to converter topologies and provide readers a comprehensive understanding of PWM-converter evolution from the original converter, the buck converter. Additionally, in this paper, the Ćuk, SEPIC, and zeta converters all with the same transfer gain of $D/(1 - D)$ are proved to be equivalent to the buck–boost converter with an extra LC filter. For further illustrating the proposed approaches, various types of Z-source converters, switched-capacitor/switched-inductor hybrid converters, and a single-stage interleaved converter are reviewed, and new PWM converters are developed. [ABSTRACT FROM AUTHOR]

In this paper, three generalized configurations of three-phase pulsewidth modulated (PWM) rectifiers are presented. They are composed of cascaded cells, each formed by a three-phase bridge of switching devices and a three-phase transformer to cascade the cells and isolate the load from the power source. One configuration is bidirectional, whereas the other two are unidirectional alternatives that replace power switches for diodes in some legs. The turns ratios of transformers from each cell are designed in order to provide the required gain and number of levels in the inverted multilevel voltage, enhancing power quality while attending requirements for proper operation in each case. Configurations with two and three cells are compared by means of simulations between themselves and with three conventional three-phase PWM rectifiers: the two-level insulated gate bipolar transistor bridge and the multilevel neutral point clamped (NPC) bridge and NPC H-bridge. Many degrees of asymmetry between the transformers in each cell, determined by the turns ratios, are considered to evaluate their impact on the topologies with relation to performance and cost. It is shown that proposed multilevel rectifiers present lower harmonic distortion, semiconductor losses, and switching stress, and some options with intermediate asymmetry are considered as good alternatives to the most asymmetrical cases. Experimental results are also provided for configurations with two cells, to demonstrate their lower harmonic distortion and power losses compared to the conventional isolated two-level PWM rectifier. [ABSTRACT FROM AUTHOR]

Most photovoltaic (PV) systems are composed of series and parallel inverters. The electromagnetic interference (EMI) mainly comes from the off–on of inverter switches with pulsewidth modulation (PWM). The output EMI peaks of PV systems would increase markedly due to the interference superposition effect caused by parallel inverters, whose carrier initial phases are in phase or close to each other. In this paper, an auto-screening carrier phase-shift scheme is proposed to weaken the superposition effect of EMI peaks and to get the result of reverse offset at its best. In a PV system, through voltage detections and spectrum estimations of each inverter with a series of phase-shift carriers, a best carrier phase of each inverter is obtained automatically to minimize EMI peaks of the PV system. In order to avoid the conflict that the screening processes of two or more inverters are underway at the same time, a specific frequency signal is output temporarily as an occupancy mark in one of the inverters. The feasibility and effectiveness of the proposed scheme are verified by experimental results in a PV system composed of four parallel single-phase inverters. [ABSTRACT FROM AUTHOR]

In this paper, a new method is applied to predict the average value of the phase currents of a two-level voltage source converter. The method uses a suitable model of the converter, the modulation method, and the measurement. The samples given by the analog-to-digital converter (ADC) are used to predict the time progress of the currents in every switching cycle and then calculate its average. This allows removal of the delay introduced by filtering and avoids aliasing in the measurements. The average prediction is contrasted with the pulsewidth modulation (PWM) synchronous sampling method and the sigma-delta ADC with a moving average filter. Applied to a load observer, the method effectively reduces its estimation error. The findings are verified experimentally. [ABSTRACT FROM AUTHOR]

High step-down voltage conversion is necessary to bridge the voltage gap between main power converters and low-voltage auxiliary electronics in power conversion systems. Switched capacitor converters (SCCs) are an attractive candidate as a high step-down converter, but their poor voltage regulation capability may limit their applications. Pulsewidth modulation (PWM) SCCs with adjustable high step-down voltage conversion are proposed in this paper. The proposed PWM SCCs can be derived from traditional SCCs by replacing an energy transfer capacitor with a switched-capacitor-inductor (SCL) cell that comprises inductors, capacitors, and diodes to realize PWM-controllable voltage conversion. The voltage step-down ratio of the proposed PWM SCCs is not only PWM controllable but also adjustable with structures of SCCs and SCL cells. Two representative PWM SCCs were taken as examples to perform the operational analysis. The prototypes of both representative PWM SCCs were built and tested to demonstrate the proposed concept. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) is known as a major cause of premature motor failures. The form and amplitude of the CMV generated by any converter depends on both the circuit topology and modulation technique. Among single stage ac–ac converters employed in drive applications, the Z-source ultra sparse matrix converter (ZSUSMC) is a desirable choice due to reduced number of switches in its structure and voltage boosting capability. Based on these considerations, this paper aims to: 1) theoretically determine and compare the CMV of the ZSUSMC with four well-known impedance networks, namely, cascaded, switched-inductor, quasi, and series, in its structure and 2) propose modulation techniques for CMV reduction in the ZSUSMCs. To this end, first, it is shown that the ZSUSMC, depending on the impedance network used in its structure, provides more freedom to choose from redundant switching states compared to the ultra sparse matrix converter. Then, by taking advantage of this feature, novel modulation strategies that attenuate the CMV without affecting the boosting capability are developed. The proposed modulation schemes are based on avoiding the switching states most contributing to the CMV during a switching period. Through hardware-in-the-loop studies, the effectiveness of the proposed modulation strategies in reducing the CMV of the ZSUSMCs is verified. [ABSTRACT FROM AUTHOR]

In voltage-source inverters (VSIs), dead time is used to prevent shoot-through over switching devices. However, the existence of the dead time will distort the output phase current, which degrades the performance of the inverter as well as influences the common-mode voltage (CMV), particularly in CMV elimination relevant modulation schemes, such as zero-common-mode (CM) pulsewidth modulation (PWM)-based paralleled inverters. In the light of the situation that the normal sampling-based dead-time compensation (DTC) methods are often disturbed by the current ripple, this paper introduces a novel DTC method for the VSI, which can mitigate the impact of the current ripple and improve the accuracy of DTC. The proposed method deduces the real-time current ripple, which can reconstruct the actual trajectory of phase-leg currents, and the peak values corresponding to rising and falling edges for PWM signals can be predicted. In this way, DTC can be implemented based on the direction of relevant instantaneous switching currents and finally improves the accuracy. Especially, the current-ripple-prediction-based DTC can help to improve the CMV distortion caused by the dead time for paralleled inverters with zero-CM PWM. Simulation and experimental results are provided to validate that the proposed method can be applied to different topologies and modulation schemes with good performance. [ABSTRACT FROM AUTHOR]

In this paper, a novel direct ac–ac converter based on the coupled inductor Z-source networks is proposed that offers a wide range of buck–boost operation. A total of two Z-source networks, called the coupled switched inductor and the modified switched coupled inductor, are employed that enable the ac–ac converter to deliver a wide voltage range. The proposed converter with both networks provides free-wheeling current paths for the inductors currents during the state transitions, which results in solving the commutation problems and the need for snubber circuits. A simple switching strategy is then proposed that helps to share a common magnetic core between the coupled inductors. For any particular voltage gain, the proposed structures require a smaller duty cycle compared to the conventional ones; therefore, a smaller inductance is required. Simulation and experimental results are provided to confirm the theoretical achievements. [ABSTRACT FROM AUTHOR]

Recent power systems, such as renewable energy systems consisting of solar panels and rechargeable batteries, contain multiple power sources and need multiple converters in proportion to the number of power sources, resulting in increased system complexity and cost. This paper proposes a multiport converter (MPC) integrating a bidirectional PWM converter and series-resonant converter. Not only is the switch count halved with the proposed MPC, but also magnetic components can be integrated, reducing the circuit complexity and volume. A 150-W prototype of the proposed MPC was built for the experimental verification. The measured voltage conversion characteristics and transient responses demonstrated that the proposed MPC could control load and battery voltages independently by pulse width modulation and pulse frequency modulation controls, respectively. [ABSTRACT FROM AUTHOR]

Application of pulse width modulation (PWM) is known to produce sideband effects. The accuracy of the models of dc–dc converters can be improved if essential information of the sideband effects of PWM can be incorporated. In this paper, the aliasing effect of the sideband components on the closed-loop control is analyzed, and an effective representation of the transfer function of the pulse-width modulator is derived. Applying this transfer function to the dc–dc converter, an extended-frequency-range small-signal model is obtained, which can be conveniently used for deriving the loop gain of a PWM-controlled dc–dc converter. Furthermore, for wideband control applications, the large switching ripple in the modulation signal necessitates adjustment of the representation of the gain of the pulse-width modulator, which is dependent on the controller. Despite being highly accurate for stability assessment, the extended-frequency-range model is relatively complex after incorporating the effects of the sideband components and the large switching ripple. An approximate approach is introduced to simplify the loop gain expression and to provide physical insights into the effects of the sideband components and large modulation ripple amplitude. Experimental verification of the extended-frequency-range model is provided for a buck converter and a boost converter. [ABSTRACT FROM AUTHOR]

This paper proposes a space vector modulation (SVM) strategy for asymmetrical cascaded multilevel converters operating under fault conditions on the power cells. During each switching interval, one voltage vector is chosen to be implemented by the high voltage cells. It is then subtracted from the reference, resulting in a new reference for the low voltage cells. However, under fault conditions, if the high voltage vectors are not properly chosen, the converter may saturate. This paper presents a comparison between the choice of the high voltage vector as the nearest one to the reference, and as the one whose domain encompasses it. It is shown that the second choice is better, as it avoids saturation of the converter as much as possible. The proposed SVM is performed in the output line-to-line voltages coordinate system, in which the converter voltage vectors have only integer entries. The algorithm is presented considering as an example a converter with two cells per phase: one of 1 pu that switches with PWM, and one of 2 pu, switching at the fundamental frequency, respectively called low-voltage-high-frequency and high-voltage-low-frequency cells. Finally, experimental results are given to demonstrate and validate the good performance of the proposed SVM. [ABSTRACT FROM AUTHOR]

This paper presents a comparison of two modulation methods for the seven-level switched-capacitor (SC) inverter using series/parallel conversion (SCISPC). The SCISPC is a multilevel inverter which has the less number of switching devices than the conventional multilevel inverters. The level-shifted pulsewidth modulation (PWM) (LS-PWM) was applied to the seven-level SCISPC in the previous research. In this paper, the level- and phase-shifted PWM (LPS-PWM) and the LS-PWM are applied to the seven-level SCISPC, and LPS-PWM is compared with LS-PWM for the seven-level SCISPC. The LPS-PWM has both the characteristics of the phase-shifted PWM (PS-PWM) and the LS-PWM. The voltage reduction during the discharging term of the SCs is reduced by means of the shorter discharging period compared to LS-PWM. The voltage ripple of the capacitors is also reduced, which leads to higher power conversion efficiency. The difference of the two modulation methods is confirmed by the theoretical approach, simulation with PSIM, and circuit experiment. [ABSTRACT FROM PUBLISHER]

Soft switching pulse-width modulation (PWM) dc–dc full-bridge converter with controlled rectifier on the secondary side of the high-frequency power transformer is presented in this paper. An active secondary switch, including new nondissipative passive energy recovery turn-off snubber on the secondary side and modified PWM control algorithm, provide conditions for zero-voltage and zero-current turn-on and zero-current turn-off of IGBT transistors on the primary side of the high-frequency dc–dc converter. The simple passive energy recovery snubber ensures also zero-voltage turn-off of the transistor on the secondary side of the power transformer. The principle of operation is explained and analyzed and consequently verified on a 2 kW, 50 kHz laboratory model of the converter. [ABSTRACT FROM PUBLISHER]

This paper presents a general space vector modulation (SVM) method for the modular multilevel converter (MMC). Compared with earlier modulation methods, the proposed SVM method not only utilizes the maximum level number (i.e., $2n+ 1$, where $n$ is the number of submodules in the upper or lower arm of each phase) of output phase voltages, but also leads to an optimized control performance in terms of capacitor voltage balancing, circulating current suppression, and common-mode voltage reduction. The maximum level number is achieved by introducing a new equivalent circuit of the MMC, and the optimized control is obtained by selecting the optimal redundant switching states. Since the computational burden of the SVM scheme is independent of the voltage level number, the proposed method is well suited to the MMC with any number of submodules. Simulation and experimental results are presented to validate the proposed method. [ABSTRACT FROM PUBLISHER]

Interleaved converter legs are typically modulated with individual carriers per leg and phase-shifted pulse width modulation (PS-PWM) as it facilitates current balancing amongst the legs. Phase-disposition PWM (PD-PWM), despite the better harmonic performance, cannot be directly used due to the resulting current imbalance that may damage the converter. This paper addresses the current sharing issue and proposes a sorting algorithm implementation that enables single-carrier PD-PWM technique for interleaved two-level converter legs. An extension of the proposed algorithm through a switching state feedback loop, limiting the average switching frequency, is also developed. In both cases, the output current is of high quality and shared amongst the phase-legs, while the deviation between the phase-leg currents is well regulated. Simulation results demonstrate the general function of method for multiple interleaved legs as well as its current sharing capabilities for high-power applications. Experimental results from a low-power laboratory prototype validate the operation of the proposed approach. [ABSTRACT FROM PUBLISHER]

Neutral-point (NP) voltage imbalance is an inherent problem of three-level neutral-point clamped (NPC) converter. To solve this problem, an improved virtual space vector pulse width modulation (VSVPWM) is proposed in this paper. A new repartitioning of the space vector sectors is proposed for three-level NPC converter by considering the amplitude variations of small vectors under NP voltage imbalance. The factor k of the NP voltage imbalance is introduced. The small vector favorable to the NP voltage balance is selected based on the factor k and phase current direction to achieve precise control and balancing of NP voltage. The proposed method can effectively maintain NP voltage balance and eliminate the low frequency oscillation of the NP voltage over the whole modulation index range. The improved VSVPWM also has advantages of good dynamic performance. The method has been tested and verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

The noninverting buck–boost converter has attracted significant attention in the photovoltaic (PV) module integrated application, as it offers high efficiency while maintaining a low cost and a simple topology. When this converter is employed, special care must be taken at the transition between buck and boost operating modes, as a dead-zone in the voltage transfer function can cause abrupt perturbations in the controlled voltage, decreasing the regulation quality and ultimately lowering the power conversion efficiency. In this paper, a new dead-zone compensation technique is proposed with the scope of smoothing the transition between operating modes, eliminating the voltage ripple and improving the regulation performance, while maintaining high efficiency. The converter under analysis is studied together with its gate driving circuit, which is based on a bootstrap capacitor power supply for the high-side switches. The proposed dead-zone compensation technique is deduced by using the principle of maintaining the ideal voltage gain function across the converter operating range. The technique is analyzed, implemented and tested on a purposely built PV module integrated noninverting buck–boost converter. The experiments reveal a sensible improvement of the voltage regulation during mode transition, confirming the effectiveness of the proposed technique and its fitness for the PV application. [ABSTRACT FROM AUTHOR]

Five-level hybrid-clamped (5L-HC) converter is a newly proposed topology which is suitable for high-performance medium-voltage high-power conversions without switches directly connected in series. The critical issue of this converter is that two flying capacitor voltages of each phase and two neutral-point potentials of the dc-link need to be balanced. This paper presents a decoupled voltage balancing method for this 5L-HC converter based on modified phase-shifted pulse width modulation (PS-PWM) and optimal zero-sequence voltage injection. The voltages across the central dc-link capacitor and two flying capacitors are balanced first by adjusting the width of four PWM signals. Second, the relationship between the neutral-point currents and the output phase voltage is studied and the upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection. Both steady-state and dynamic-state simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

Power conversion systems based on double-delta sourced winding (DDSW) had an optimization issue in terms of pulsewidth modulation (PWM). This issue was about inefficient employments of voltage levels during PWM and had to be considered for minimizing voltage stresses and current ripples on DDSW. In this paper, a novel method has been proposed to improve the performance of PWM in DDSW-based systems. The proposed method can be simply implemented as a carrier-based PWM and its principles are neatly summarized with equations. Finally, the effectiveness of the proposed method is demonstrated with experimental results, which were obtained by using a transformer and an induction machine. [ABSTRACT FROM PUBLISHER]

Presently, the neutral-point potential offset is an inherent problem for three-level converters on three-phase four-wire active power filters. The conventional three-dimensional space vector pulse width modulation (3-D-SVPWM) strategy is adopted as a normal solution to the problem, but the selection of space vector sectors for four-wire converter is both abstract and complicated in practice. This paper proposes a new PWM strategy accordingly to simplify the selection process and the calculation of duration. Compared to the conventional 3D-SVPWM, the proposed method locates the sector of optimal vector directly with the polarity of three-phase reference voltage. Then, by applying voltage–second balance rule, it can perform a fast calculation of the duration and generate PWM signals to control the switching devices’ on/off. As an approach to correct the imbalance dc-link capacitor voltage, this strategy reconstructs the switching sequence. A portion of state O duration is disassembled into states P and N to suppress the neutral-point potential offset. The proposed strategy is validated with a range of experiments. The results indicate that this simplified PWM strategy can effectively reduce the computational burden, and also the dc-link capacitor voltage is well controlled. [ABSTRACT FROM PUBLISHER]

In this paper, dual-buck structured single-stage buck–boost inverters that use power MOSFETs to achieve high efficiency are presented. The proposed inverters require fewer switches, and half of the switches have reduced current stresses. They have no shoot-through problem; therefore, high system reliability can be obtained. The dead-time in PWM signals can be minimized or eliminated, which improving the quality of the output ac voltages and increasing the efficiency. In the proposed inverters, MOSFETs can be used without reverse-recovery issues of their body diodes to boost the efficiency and increase the switching frequency. To further improve the efficiency and stability of the proposed single-phase inverter, PWM strategies combining high- and low-frequency modulation are presented. A hardware prototype of the single-phase inverter was built and tested using resistive, inductive, and nonlinear loads. Experimental results for a 300-W prototype inverter show a 97.4% peak efficiency with a 25 kHz switching frequency. [ABSTRACT FROM AUTHOR]

Cascaded bidirectional dc–ac converters are commonly used in uninterruptible power supply applications and battery chargers for electric vehicles. Power conversion units for such applications employ a large electrolytic capacitor at high-voltage dc bus, which not only reduces the lifetime but also adds to the weight of the converter. In this paper, a novel bidirectional dual active bridge cascaded three-phase converter (DABCC) with six-pulse dc link is proposed. Also, a new closed-loop control scheme to implement the six-pulse modulation (SPM) technique in DABCC is proposed. The advantages of the proposed control scheme in DABCC are that the electrolytic capacitor is eliminated and is replaced with a low-value film capacitor resulting in increased reliability, compactness, and reduced cost. SPM technique also increases the dc bus utilization and decreases the inverter average switching frequency to 33% when compared with the conventional sine pulse-width modulation (SPWM). Harmonic components introduced in the pole voltages of the SPM-modulated DABCC due to inverter dead time are analyzed, and a resonant controller is designed to mitigate them. Also, root mean square current stress for high-voltage dc-link capacitor is studied, and it is shown that the capacitor requirement for SPM modulation is lower than the conventional SPWM. To validate the proposed control scheme, an 800-W proof-of-concept laboratory hardware prototype is fabricated and experimental results are demonstrated. [ABSTRACT FROM PUBLISHER]

In this paper, a new zero-voltage switching and resonant core reset pulse width modulation forward converter with a simple auxiliary circuit is introduced. The proposed auxiliary circuit can be applied to both single-switch and two-switch forward converters. The main and the auxiliary mosfets of the proposed converters operate under soft switching condition independent of line and load variation. Also, due to the capability of operating at duty cycles higher than 0.5, the proposed converters can be used for wide input voltage applications. In comparison to the existing zero-voltage transition (ZVT) forward converters, this auxiliary circuit has low number of components and also does not require any additional magnetic element which has improved the power density. The proposed converter is compared with exiting ZVT forward converters in details. The converter steady-state operation is analyzed and various operating modes are explained. Also, in addition to a design example, a comprehensive design procedure is presented. The experimental results of a laboratory prototype of the converter with 85–180 V input voltage and 24 V output voltage at 150 W are provided which verify the theoretical analysis and confirm the converter operation. The overall efficiency of 93.5% is achieved for the proposed converter at full load. [ABSTRACT FROM PUBLISHER]

The impedance-source network converter, utilizing a unique LC network and previously forbidden shoot-through states, provides the ability to buck and boost the input voltage in a single stage. However, the inrush shoot-through current (STC) in startup or transient process might cause undesired current stresses on converter devices. This paper focuses on the STC sensing for an effective inrush current limitation by the combined current sensing technique in the quasi-Z-source inverter. STC and phase currents for the inverter control strategy are obtained simultaneously. No extra hardware is needed and the effects of current sensor bandwidth and duty cycle on the sensing accuracy are analyzed mathematically. The voltage spike gets avoided by integrating the stray inductance into the impedance network. Finally, an STC control loop based on proposed method are embedded in the field-oriented control strategy. The inrush STC and the device current stress in the transient process get suppressed. Simulation and experimental results from a quasi-Z-source inverter validate the feasibility of the proposed methods. [ABSTRACT FROM PUBLISHER]

The main objective of this paper is to examine the operation of a fundamental buck-based three-phase single-stage ac–dc full-bridge converter. In this paper, the operation of this fundamental converter is explained and analyzed, and a procedure for the design of its key components is derived and demonstrated with an example. The performance and characteristics of the converter are shown with experimental results that have been obtained from a prototype, and general concluding remarks comparing buck-based and boost-based three-phase single-stage ac–dc full-bridge converters are made. [ABSTRACT FROM PUBLISHER]

Neutral-point (NP)-clamped three-level inverter, which is a widely used topology of multilevel converters, suffers from the NP voltage drift as its main technical drawback. The nearest-three-virtual-vector (\NTV^2) modulation method can control the NP voltage balance for any load over the full range of inverter output voltage. However, compared with the nearest-three-vector (NTV) modulation method, \NTV^2 increases the switching frequency. This paper combines \NTV^2 with NTV, and the two methods are used alternately in a fundamental cycle. The duty-cycle coefficients of the redundant small vectors are analyzed to explore the intervals where NTV can control the NP voltage balance in a fundamental cycle. The proportional parameter, which represents the combination of the two methods in hybrid space vector pulsewidth modulation, can be selected to achieve a high-performance NP balance control and low switching frequency. The steady- and transient-state behaviors of the proposed strategy are analyzed in this paper. The experimental results verify the validity of the proposed strategy. [ABSTRACT FROM PUBLISHER]

An open-winding power conversion system with two conventional six-switch voltage-source converters (VSC) affords operation with a lower volt-ampere (VA) rating of each device for a given power rating, as well as a degree of fault tolerance. The disadvantages of such a configuration include a higher total device VA rating and increased conduction loss as compared to a single Y/Δ-connected VSC. In certain ac-dc applications, such as telecommunications, wind, and aerospace generator drives, it is desired to have regulated input currents and output voltage, but regenerative operation is either not required or prohibited. For such applications, an alternative open-winding power converter is proposed in this paper where half-controlled converter (HCC) is employed at each end of an open-winding structure. The resultant total switch count and total VA rating are reduced by half, compared to using full bridges. Besides, the basic advantages of an open-winding configuration, use of HCCs also guarantees immunity to dc-bus shootthrough and simplifies the gate drive circuit. The total VA rating of the proposed topology is found to be 42% less than a six-switch VSC. The operating principle, control method, and analysis with simulation and experimental results of the proposed topology in both a grid-tied rectifier application and a PM generator application are illustrated in this paper. [ABSTRACT FROM AUTHOR]

Part I of this paper has proposed a duty-cycle-space-vector (DCSV)-based modulation strategy for three- and four-leg matrix converters (MCs). This paper develops a digital DCSV-based modulation strategy for the three- and four-leg MCs based on the results of Part I of this paper. The digital DCSV-based modulation strategy is implemented in a DSP–field programmable gate array (FPGA) platform. The objective is to reduce the calculation time of the modulation algorithm by performing the following: 1) reducing the total number of instructions needed to implement the modulation algorithm in the DSP and 2) implementing parts of the modulation algorithm in an FPGA to generate the switching pattern. Therefore, the calculation process of the modulation algorithm is split between the DSP and the FPGA. [ABSTRACT FROM PUBLISHER]

This paper proposes a pulse-width modulation three-level converter with reduced filter size using two transformers. The proposed converter has many advantages. All switches sustain only the half of the input voltage and since the secondary rectified voltage is a three-level waveform, the output filter inductor can be reduced. Also, because of the power sharing of transformer and reduced output inductor, high efficiency can be obtained. The operational principle, analysis, and design considerations of the proposed converter are presented in this paper. The validity of this study is confirmed by the experimental results from a prototype with 600 W, 500-600 V input, and 60 V output. [ABSTRACT FROM AUTHOR]

During the design phase of a modular multilevel converter (MMC), an accurate loss evaluation of the submodule (SM) plays an important role. In this paper, a method based on the analytical description of the MMC key waveforms that allows to directly obtain the average semiconductor and capacitor losses that each SM will experience is introduced, under different operating conditions or control schemes. To verify the proposed concept, the results are compared with the losses obtained from a switched model with closed-loop control, where the analytical MMC key waveforms are approached in steady state. The proposed method provides a great flexibility and a significant reduction of the simulation/computational time otherwise needed to evaluate SM losses under various operating conditions. [ABSTRACT FROM PUBLISHER]

This paper addresses the inverter nonlinearity of a three-level T-type inverter. The main causes of the nonlinearity are pulse shaping, pulse skipping due to narrow pulses for the dead time, and voltage drop of the switching devices. Although the same causes have existed in two-level inverters, the pulse skipping phenomenon and results are quite different in the case of the three-level T-type inverter. The effects of pulse shaping and skipping have been investigated and discussed. In addition, the voltage drop of the switching devices has been considered in conjunction with the conduction path of the T-type inverter. Compensation methods based on the pulse width modulation (PWM) of T-type inverter to alleviate the inverter nonlinearity have been proposed from research results. The proposed methods could be easily implemented by adding appropriate offset voltages to the voltage references of the inverter in PWM. Furthermore, a neutral voltage balancing method of a three-level T-type inverter has been proposed in conjunction with the proposed PWM methods using offset voltage. Through extensive experimental tests, the fifth- and seventh-harmonic components of the current are conspicuously reduced along with the even harmonics. The neutral voltage of the inverter can be balanced effectively with the proposed offset voltage adjustments as well. [ABSTRACT FROM AUTHOR]

This paper proposes and investigates a multilevel ac six-phase motor drive. The system is composed of five isolated three-leg voltage source inverters feeding the open-end windings of an asymmetrical six-phase induction motor (SPIM), which is adequate to generate multilevel voltages for high-power systems with voltage rating restrictions. A simple space vector pulse-width modulation (PWM) based on three similar individual planes and its implementation by means of equivalent level-shifted PWM are presented. A space vector pattern with a high number of voltage vectors redundancies is obtained. These redundancies and the application sequence of the voltage vectors are selected to minimize the amount of changes in the switching states and to decrease the harmonic distortion of the generated voltages. The vector pattern of this optimal modulation is obtained by analyzing only one plane and applied in the same way to the three planes as if they were independent. The developed PWM techniques have low computational complexity and are suitable for low-cost hardware implementations. Simulation results are used to compare the proposed topology with a conventional configuration in terms of harmonic distortion and semiconductor losses. Experimental results demonstrate the feasibility of the proposed drive system. [ABSTRACT FROM AUTHOR]

Multilevel cascaded H-bridge converters have become a mature technology for applications where high-power medium ac voltages are required. Normal operation of multilevel cascaded H-bridge converters assumes that all power cells have the same dc voltage, and each power cell generates the same voltage averaged over a sampling period using a conventional phase-shifted pulse width modulation (PWM) technique. However, this modulation method does not achieve good results under unbalanced operation per H-bridge in the power converter, which may happen in grid-connected applications such as photovoltaic or battery energy storage systems. In the paper, a simplified mathematical analysis of the phase-shifted PWM technique is presented. In addition, a modification of this conventional modulation method using variable shift angles between the power cells is introduced. This modification leads to the elimination of harmonic distortion of low-order harmonics due to the switching (triangular carrier frequency and its multiples) even under unbalanced operational conditions. The analysis is particularized for a three-cell cascaded H-bridge converter, and experimental results are presented to demonstrate the good performance of the proposed modulation method. [ABSTRACT FROM PUBLISHER]

In this paper for power factor correction (PFC), a modified Landsman converter is introduced. The application is targeted for high-brightness (HB) projection application with brightness control for HB red–green–blue (HB-RGB) light-emitting diode (LED). A pulse-width modulation (PWM) technique is used for intensity control to achieve brightness control of the LED driver. The proposed PFC converter is used to feed a dual output flyback dc–dc converter that supplies power to the forced cooling unit and the LED module with galvanic isolation. The brightness control of LED is performed by synchronous buck converter. The modified Landsman converter operates in discontinuous output inductor current mode for PFC at universal ac mains. A prototype of the proposed LED driver is experimentally verified. The performance of proposed driver is evaluated at full and light-load condition for universal ac mains (90–265 V) over a full range of brightness. The power quality parameters are found within the acceptable limits of harmonic standard IEC 61000-3-2 for universal ac mains. [ABSTRACT FROM PUBLISHER]

In an asymmetrical pulse-width-modulated half-bridge (APWM HB) series resonant converter, an auxiliary LC network is provided for ensuring zero-voltage switching (ZVS) over a wide range of line and load variations. However, it comes at the cost of increased number of components and reduced efficiency and reliability. This paper presents a novel design methodology for the standard APWM HB resonant topology, which uses the magnetizing current and eliminates the need for extra components. The converter with the proposed design methodology operates at the resonant frequency of the tank and features load-independent ZVS for a wide range of input voltage variation with minimal magnetizing current. Empirical formulae are derived to design the resonant network and the magnetizing inductance of the high-frequency transformer systematically in a flowchart-based manner. The proposed design is validated by using simulations as well as experiments and is compared with a reference APWM HB series resonant converter design that uses an auxiliary LC circuit for ZVS. Two separate experimental prototypes of the two converters rated for 30 W, 48 V/5 V with a switching frequency of 500 kHz were built and tested in the laboratory. It was found that the converter with the proposed design methodology, apart from having lower component count, is about 3% more efficient than the reference topology at the rated power. [ABSTRACT FROM PUBLISHER]

This paper presents a new high-frequency modulation method for multilevel converters. The proposed method provides a broad linear operating range and can be digitally implemented with minimal computational effort. This modulation method creates a phase voltage composed of a rectangular component superimposed on the top of a quasi-square-shaped reference function. The reference functions are defined such that the utilization of the dc-link voltage is maximized in any modulation index, while the dv/dt of the switches is always the minimum possible value. In order to implement the proposed method, an update time that is much shorter than the fundamental period is defined in the algorithm for updating the rectangular components of the reference voltage. The high-frequency rectangular component can then be imposed on the reference function to generate the final switching function by switching between two voltage levels during the time between two update instances. Several experimental results are provided to evaluate the performance of the proposed method and to compare its operation to conventional methods. [ABSTRACT FROM PUBLISHER]

Cascaded converters are adopted in many power systems to manage sources and loads at different voltage levels simultaneously. DC bus capacitor is one of the key components in these converters due to its energy storage and fast response capabilities. However, the ripple current through the capacitor will influence its lifetime and the overall efficiency of the converter. Previous studies showed that the capacitor current of ac systems is optimized when the duty cycles are synchronized under in phase or antiphase condition. In this paper, the bus capacitor ripple current of cascaded two-stage converters for dc systems with different combinations of duty cycles is analyzed. It is found that the optimum capacitor current ripple varies depending on the values of individual duty cycles and the phase-shift angle between them. By properly adjusting the phase shift, the capacitor RMS current value can be reduced without affecting the converter normal operation or the need for extra sensing circuits, hence improving the energy conversion efficiency and prolonging the capacitor lifetime with relatively simple implementation. To illustrate, a case study of a two-stage dc/dc converter is carried out. A laboratory prototype converter confirmed a maximum efficiency improvement of 2.8% if the phase shift is adjusted properly when compared to the same converter with the worst case phase-shift angle. [ABSTRACT FROM AUTHOR]

In this paper, the switching cell concept is extended to isolated ac–ac converters, and a highly reliable double step-down ac–ac converter is proposed with high-frequency transformer (HFT) isolation. By using the switching cell structure and coupled inductors, the proposed converter has no commutation problem as it is immune from both short-circuit and open-circuit problems, even when all the switches are turned on or turned off, simultaneously. Therefore, it does not require pulse width modulation dead times along with bulky and lossy RC snubbers or voltage-sensing circuitry to implement soft-commutation strategies, resulting in high reliability and high quality output waveforms. The HFT in the proposed converter provides electrical isolation and safety which is required in applications such as dynamic voltage restorer (DVR), solid-state transformer (SST), etc., without the need for external bulky line frequency transformer. Moreover, all the passive components experience twice the switching frequency; therefore, their size can be reduced. The proposed converter is very suitable for application as DVR, to compensate both voltage sags and swells, owing to its ability to provide both inverting and noninverting outputs. A detailed theoretical analysis and operation of the proposed ac–ac converter are provided, and its applications as DVR and SST are also discussed. Experimental results with scaled-down prototype are also provided to verify its performance. [ABSTRACT FROM AUTHOR]

A single-phase inverting buck–boost ac–ac converter is proposed in this paper. The proposed converter has no shoot-through and dead-time problems and, like conventional dc–dc converters, it can be operated with simple pulse width modulation (PWM) control. It offers high frequency and high efficiency operation because high speed mosfet can be used as switching device without the reverse recovery issues and losses of its body diode. The proposed converter features quasi-continuous input and output currents, high input power factor, low total harmonic distortion of input and output currents, and high efficiency. A 460 W laboratory prototype was constructed and tested with interleaved and complementary PWM controls using a resistive and inductive load. Detailed experimental results are provided to show the novelty of the proposed converter. Experimental results confirmed that the proposed converter can obtain 93.8% efficiency at 60 kHz switching frequency. [ABSTRACT FROM PUBLISHER]

The device switching frequency of current source converters (CSCs) in high-power medium-voltage (MV) drive applications is normally around 500 Hz. Conventional space vector modulation (SVM) features fast dynamic response but its output contains low-order harmonics with high magnitudes. In this paper, a natural-sampling-based SVM (NS-SVM) scheme is proposed to substantially suppress the low-order harmonics in practical CSC-based drives. This study proposes an equivalent discretization of NS-SVM wherein natural sampling pulse width modulation performance can be achieved with regular sampling frequency (same as a conventional SVM) instead of a high or even infinite sampling frequency. Equations for natural-sampling-based dwell time calculations for each selected vector are developed. The corresponding simplified but precise enough equations are derived on the basis of the Newton–Raphson algorithm to achieve fast online digital implementation. The proposed NS-SVM features superior low-order harmonic performance and inherits the high dynamic response and low sampling frequency of conventional SVM. Simulations and experiments are provided to verify the proposed NS-SVM scheme. [ABSTRACT FROM AUTHOR]

In this paper, an improved model predictive control (MPC) of the modular multilevel converter (MMC) with reduced computational burden is proposed. A mathematical model of the MMC system based on the sum and difference of arm voltages are derived. Instead of determining the switching state of individual submodule (SM), the voltage levels of MMC are considered as control options based on the assumption that the SM capacitor voltages are well balanced. The further reduction of calculation effort is realized by using the tolerance band of capacitor voltages. The proposed MPC has a hierarchical structure. The cost function taking into account the ac-side current control, circulating current elimination and arm energy balancing is presented. The optimal voltage level, selected by the cost function, provides the voltage reference for the pulse width modulation modulator. The SM capacitor voltage balancing is done using a separate control loop. The proposed control strategy is investigated using an MMC high-voltage direct current system with 200 SMs in each arm in real-time simulation and hardware-in-the-loop tests. The performance of proposed method is verified by both steady-state and transient-state operations. [ABSTRACT FROM PUBLISHER]