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The modular multilevel converter (MMC), owing to the presence of a large number of submodules (SMs) and energy storing elements, requires a large footprint and initial investment. To address these issues, this paper proposes the switched modular multilevel converter (SMMC). It consists of two major elements; the chain-links (CLs), consisting of cascade connection of SMs as in MMC, and the single-pole-triple-throw (SPTT) switches, which can be realized using either the T-type or NPC-type switch strings. The SMMC works on the principle of connecting all the phase-legs in series and their respective positions are mutually interchanged. It offers a compact structure as the SMs count is reduced to 33% of MMC, which results in a much lower energy storage requirement. Furthermore, it does not have inter-phase circulating current problem and hence the CL inductors can also be avoided. The SMMC structure, operating principles, control, and modulation schemes are explained in detail. A detailed comparison of SMMC with the other major existing converters is carried out to highlight the important features of SMMC. The efficacy of SMMC is validated using PSCAD simulation studies with a 19-level grid-connected SMMC model. A 3-phase 19-level SMMC laboratory prototype is developed to further validate its feasibility. [ABSTRACT FROM AUTHOR]

DC shipboard power systems have been considered as a promising solution for stricter environmental regulations on ships due to their main benefits in fuel savings with variable speed engines and easy integration of energy storage systems. In order to employ the dc solution in the shipboard power systems, the dc power systems have to be protected from a system fault with protection selectivity to minimize impacts of the fault or to avoid other undesirable situations in the system. For low-voltage dc shipboard power systems, a three-level protection has been proposed: 1) fast action (first)—bus separation by solid-state dc bus-tie switch; 2) medium action (second)—feeder protection by high-speed fuse; and 3) slow action (third)—generator–rectifier fault controls. This paper proposes a new method by means of additional bus capacitance added in main dc buses to help reliable operation of the three-level protection. The principle of the proposed method is introduced and the sizing of the additional bus capacitance is addressed in this paper. With the modeling of the dc shipboard power systems, the analyses of voltage drops for the bus separation failure and fault clearing time for the feeder protection are carried out to verify the proposed method. The results show that the proposed method not only mitigates the voltage drop for the bus separation failure, but also achieves the selectivity and the sensitivity for the feeder protection. [ABSTRACT FROM AUTHOR]

Due to different solar radiation, temperature, and other reasons of modules in the three-phase cascaded H-bridge (CHB) photovoltaic (PV) inverter, the output power among PV modules will be unequal and lead to unbalanced grid currents, which cannot meet the requirements of grid codes. On the other hand, the second-order voltage ripple is aroused in the dc-link capacitor since each phase-leg of the CHB inverter is made up of a single-phase inverter. Concerning these two issues, this paper proposes an optimized third harmonic injection method based on fundamental frequency zero sequence injection (FFZSI), which is a conventional method to handle the slight power imbalance problem. In this paper, the FFZSI is adopted to redistribute the power among three phases, and then the third harmonic is injected into the three-phase combined reference waveforms according to the two requirements: all modules are free from overmodulation and the dc-link voltage fluctuation is mostly reduced. Therefore, the proposed method can reduce the dc-link voltage fluctuation and extend the power balance range of FFZSI at the same time. The validity and effectiveness of the proposed method are verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a novel polygonal voltage space vector structure (SVS) having 30 sides, for a star-connected induction motor drive. The SVS eliminates the presence of harmonics up to 25th order from motor phase voltage throughout the entire modulation range, providing a torque profile devoid of lower order pulsations. Linear modulation is extended till 99.63% of base speed without exceeding the motor phase voltage rating. Topology consists of a dc-link fed primary inverter and two equal low voltage modular capacitor fed secondary inverters. Here the harmonics generated by the primary inverter is canceled by the secondary inverter which acts as a switched capacitive filter. Detailed description of the SVS generation and timing calculations are provided in this paper. Effectiveness of the proposed scheme is validated using experimental results, inverter loss calculations, and harmonic analysis. [ABSTRACT FROM AUTHOR]

In this paper, many impedance-source inverters with coupled inductors have been investigated to obtain a high step-up boost ratio. However, the leakage inductors in these topologies induce great voltage spikes at the dc link, which will increase the voltage stress of switches. Thus, the power level of inverters is limited. Furthermore, the efficiency of the inverters can be degraded by the losses associated with leakage inductors. To address abovementioned issues, this paper proposes a family of low-spike high-efficiency Y-source inverters. The proposed inverters have the ability of eliminating voltage spikes at the dc link and recycling the leakage energy via the additional diode and capacitor. In order to show the excellent characteristics of the proposed topologies, this paper compares the performances of the proposed inverters and the improved-Y-source inverter in many aspects. Simulation and experimental results have verified the abilities of the proposed inverters. [ABSTRACT FROM AUTHOR]

A space vector modulation (SVM) technique of a dual-inverter system for an open-end winding motor drive is described in this paper, where one inverter has a battery power source and the other has an only capacitor across the dc bus. The SVM must be achieved to operate the motor with field-oriented control and simultaneously to control the capacitor voltage at a constant value by using redundant switching states of the dual-inverter system. The control of the capacitor voltage is carried out by selecting a charging or a discharging mode in each redundant switching state, taking the instantaneous motor power factor into account. In addition, it is also required to reduce the error voltage pulses, which are generated in output multilevel voltage waveforms during the dead time. The compensation method of the existing dead-time scheme and the improved SVM sequence to reduce the error voltage vectors are proposed in this paper. The proposed methods are examined through several experimental tests and are confirmed to generate superior output voltage waveforms from the viewpoint of the measured total harmonic distortion and dv/dt. [ABSTRACT FROM AUTHOR]

In this paper, a new family of impedance source inverters is presented. It employs high-frequency electrical isolation between the inverter bridge switches and the load along with voltage clamping across the dc-link voltage. Conventional Z-source inverters (ZSIs) employs an impedance network that consists of inductors and capacitors. It has unique features that realize both step-up/step-down functions and eliminates the need of dead/overlap times. This paper extends this novel concept by using electrical isolation in impedance source inverters. High-frequency isolation has many advantages in terms of immunity and reliability; when applied with impedance source inverters this makes ZSIs a preferable choice for industrial applications. In photo-voltaic systems, the addition of the high-frequency transformer provides safety by avoiding the injection of dc circulating current into the grid, without the need of an external bulky line frequency transformer. The gain of the proposed inverter design can be accurately selected by choosing the turns ratio of the high frequency transformer (HFT) or by adjusting the shoot-through duty cycle (STDC) to the inverter. This allows for greater freedom especially when utilizing a higher modulation index, with the STDC allowing dynamic gain adjusts to be done speedily during operation of the inverter. Additionally, a dc-rail voltage clamping technique for the proposed class of isolated ZSIs is also discussed. This technique provides benefits not only in improving the output voltage quality, but also in reducing voltage stress of the active and passive components by minimizing the voltage spikes across the switching devices. In this paper, several high-frequency isolated ZSIs are presented, and an example isolated improved ΓZSI design is shown and discussed in detail. Simulations are provided for the proposed class of isolated inverters to verify their working. Further experimental investigation has been done for which results for the isolated improved ΓZSI are reported. These empirical results have largely confirmed the expected benefits that were determined through simulation and accurate model-based testing. [ABSTRACT FROM AUTHOR]

This paper presents a novel seven-level inverter topology for medium-voltage high-power applications. It consists of eight active switches and two inner flying capacitor (FC) units forming a similar structure as in a conventional active neutral-point-clamped (ANPC) inverter. This unique arrangement reduces the number of active and passive components. A simple modulation technique reduces cost and complexity in the control system design without compromising reactive power capability. In addition, compared to major conventional seven-level inverter topologies, such as the neutral point clamped, FC, cascaded H-bridge, and ANPC topologies, the new topology reduces the dc-link voltage requirement by 50%. This recued dc-link voltage makes the new topology appealing for various industrial applications. Experimental results from a 2.2-kVA prototype are presented to support the theoretical analysis presented in this paper. The prototype demonstrates a conversion efficiency of around 97.2% ± 1% for a wide load range. [ABSTRACT FROM AUTHOR]

This paper investigates the dependence of the supercapacitor Peukert constant on its terminal voltage, aging condition, and operating temperature. Recent studies show that the charge delivered by a supercapacitor during a constant current discharge process increases when the discharge current decreases if the discharge current is above a certain threshold, i.e., Peukert's law applies. By conducting extensive experiments using three supercapacitor samples with different rated capacitances from different manufacturers, this paper reveals that the Peukert constant increases when the initial voltage of the constant current discharge process is lower, the supercapacitor is more heavily aged, or the operating temperature is lower. The physical mechanisms accounting for the Peukert constant dependence are illustrated by analyzing an $RC$ ladder circuit model. When the supercapacitor terminal voltage is higher, the aging condition is lighter, or the operating temperature is higher, more charge is stored in the supercapacitor. Consequently, when the same discharge current is applied, the discharge time is longer and the branch capacitors are more deeply discharged. Therefore, the relaxation effects of the slow branches are reduced and the supercapacitor behaves more like a single capacitor rather than a distributed capacitor network, which ultimately leads to a lower Peukert constant. [ABSTRACT FROM AUTHOR]

This paper presents a neutral-point deviation and ripple compensating control method applied to a three-level neutral-point-clamped (NPC) converter. The neutral-point deviation and its harmonic components are analyzed with a focus on the average current flowing through the neutral-point of the dc link. This paper also proposes a control scheme compensating for the neutral-point deviation and dominant harmonic components under generalized unbalanced grid operating conditions. The positive and negative sequence components of the switching functions and ac input currents are employed to accurately explain the behavior of three-level NPC converter. Simulation and experimental results are presented to verify the validity of the proposed method. [ABSTRACT FROM AUTHOR]

In this paper, a single-inductor dual-output (SIDO) dc–dc converter is proposed. The significant feature of the proposed converter is feeding a constant power load in low-voltage side (LVS) port, where even feeding a variable load at LVS does not have any cross regulation to high-voltage side port with the desired approximation. Magnificently, both merits are obtained in open-loop manner, which is an outstanding characteristic in comparison with that of the existed converters. In this paper, soft commutation and soft switching of switches and diodes are investigated along with the aforementioned main novelty. Moreover, detailed theoretical analyses of the proposed SIDO dc–dc converter in continuous conduction mode are presented besides the comparisons with some other structures. Finally, theoretical analyses are verified through a 1500 W experimental prototype results. [ABSTRACT FROM AUTHOR]

In this paper, a series-capacitor-based interleaving buck power factor correction (PFC) converter is proposed, the intermediate energy storage capacitance of which is operated at discontinuous capacitor voltage mode (DCVM), and automatic power factor (PF) correction for this converter is obtained. Moreover, the voltage across the series capacitor of the proposed PFC converter is clamped at the input voltage, and thus peak voltage stress existed in the traditional DCVM buck PFC could be relieved. By effectively regulating the charge/discharge time for the series capacitor, ultrahigh step-down conversion ratio of the proposed converter is achieved, the conversion ratio of which is independent of the duty cycle and only related to the switching frequency and circuit parameters. Therefore, high PF can be obtained due to very narrow deadtime of the input current. Meanwhile, the proposed PFC converter can realize the soft turn-on of part power switch and soft turn-off of part power diodes. In addition, comparing with the traditional discontinuous inductor current mode PFC, the input current of the proposed PFC converter is continuous so that the peak value and root-mean-square value of input current can be reduced. The operational principle, performance analysis, and parameter design principle are given in this paper. The analysis results show that the PF and total harmonic distortion are also independent of the duty cycle. Finally, a 220-Vac input, 60 W/15 V output experimental prototype is built to verify the validity of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper proposes an “isolated soft switching current fed LCC-T resonant dc–dc converter for PV/fuel cell applications.” This converter is able to achieve zero voltage switching for front-end inverter switches and zero-current switching for voltage doubler diodes. The majority of dc–dc converters have compact capacitive (C) filter in output, but high harmonic currents through transformer makes them bulky. The proposed converter attempts to improve harmonic content through a transformer under wide load and input variations as well as it can significantly reduce required turns ratio of transformer to achieve required output voltage. For the above reasons, the proposed converter can offer better footprints and therefore it can be a potential candidate for PV/fuel cell applications. This paper presents basic operating principal, detailed analysis, control, and design of the proposed converter with the help of an example. This converter operates in two modes, i.e., constant duty cycle mode and constant frequency mode, depending on load demand, and is explained through operating curves. Finally, experimental results are included for justifying the proposed theory. [ABSTRACT FROM AUTHOR]

This paper describes a bipolar pulsed power supply for strategic mineral exploration. Depending on the operating conditions, the bipolar pulsed power supply is capable of delivering the required high voltage and low current or low voltage and high current when operated, respectively, in either the grounded dipole mode or the loop mode. Based on a 500-V 12.5-A unit module, series and parallel connections of four modules are configured to satisfy both the grounded dipole mode (2000 V) and the loop mode (50 A), respectively. A unit module comprising an LCC resonant converter and a full-bridge-based bipolar pulse-switching unit is designed. In order to achieve high power density, the leakage inductance of the transformer is used as a resonant inductor in place of an external inductor. Accordingly, the resonant tank parameters are designed to give the resonant current a trapezoidal shape to reduce conduction loss and provide high efficiency. In addition, a simple gate-driving algorithm that uses the repetitive short pulse to cover the frequency range from dc to 8 kHz is proposed to allow the compact design of a minimized gate transformer. In this paper, the detailed design of the resonant circuit and the transformer of a unit module is described, and the operation is verified through simulation and experimental results. Finally, the developed LCC resonant converter achieves the maximum efficiency of 95%, the maximum power factor of 0.96, and a high power density of 806.5 W/L. [ABSTRACT FROM AUTHOR]

The capacitance of sub-module capacitor has a great impact on the cost, size, and operation of the modular multi-level converter (MMC). However, the capacitance selected by the existing methods does not always meet the requirement in practice. To find out the reasons for this improper selection, the existing selection methods are analyzed in this paper. Based on the analysis, a new capacitance-selection method is proposed. In the new method, the problems of the existing methods are solved, and the calculation of capacitor voltage is based on a proposed capacitor-voltage model whose calculation error can be smaller than 0.1%. Furthermore, the Secant Method is used in the capacitance selection to quickly calculate the required capacitance. The new capacitance-selection method can be applicable to the MMC not having a circular operating region. In addition, this paper found that the capacitor voltage and the capacitor-voltage ripple reach their maximum values when the power-factor angles of the MMC are –π/2 and π/2, respectively, and the dc component in the capacitor voltage changes according to the operating condition of the MMC. Finally, the proposed selection method and theoretical analyses are verified by both simulation and experiment. [ABSTRACT FROM AUTHOR]

In low-power applications of photovoltaic (PV) systems, the transformerless grid-connected inverters have been preferred to increase the efficiency and reduce the cost, size, and power losses when they are compared to the ones with the transformer. A transformerless single-phase inverter topology with a single dc-link capacitor for the grid-connected PV systems is proposed in this paper. The proposed inverter has been simulated by using a cooperation process of the MATLAB and SPICE package programs and it has been implemented for experimental verification. The proposed inverter reduces the high-frequency common-mode leakage current caused by parasitic capacitances of PV panels, whereas it is controlled with the unipolar sinusoidal pulsewidth modulation. Also, the results show that the common-mode voltage remains constant. The efficiency of the proposed inverter has been compared to that of the most common topologies having the dc-link decoupling during the zero voltage states. This paper is accompanied by a video file demonstrating the power loss distribution in the inverter. [ABSTRACT FROM AUTHOR]

In this paper, a new non-isolated two-input single-output dc–dc converter with high voltage gain is proposed. In the proposed converter, there are two three-winding coupled inductors used to achieve a high voltage gain and ripple-free input currents. The proposed converter has two switches, and their control pulses are the same as the control pulses of the two-phase interleaved converters with a phase shift equal to $\text{180}^{\circ} $. The voltage stresses of switches and diodes are reduced and are always lower than the high output voltage. The proposed converter is extendable to a four-input single-output converter in which the switches have the control pulses the same as those in four-phase converters with phase shifts equal to $\text{90}^{\circ} $. In this paper, the proposed topology is analyzed in all operating modes, and the values of current and voltage stresses of all switches and diodes, voltage gain, and required conditions for input current ripple cancelation are calculated during a switching period. Finally, the accuracy performance of the proposed converter is reconfirmed through experimental results for 225- and 298-W prototypes. [ABSTRACT FROM AUTHOR]

This paper describes a dc-link voltage control method of a single-phase back-to-back cascaded H-bridge inverter (SBCI) for a medium-voltage motor drive system. The main advantage of the SBCI topology over the conventional regenerative cascaded H-bridge topology with a three-phase active front-end (AFE) is a simple system structure, which is composed of an input transformer, a power cell, a current sensor, etc. However, the challenging points of the SBCI are larger voltage ripple in the dc-link capacitor and imbalance of dc-link voltages of each phase. The asymmetric dc-link voltage of each power cells could cause unstable operation such as over-modulation due to the lack of the dc-link voltage of a particular phase and result in over-voltage or under-voltage faults. In this paper, the control strategy of the dc-link voltage for the SBCI that uses the negative-sequence voltage of the converter is described. The proposed control method is verified with a computer simulation whose target is a 6.6-kV–1.25-MW medium-voltage drive system. Also, through the experimental setup with the prototype SBCI whose power rating is 16.2 kVA, the dc-link voltage of each AFE has been controlled within a 0.5% error of its reference value at the full load. [ABSTRACT FROM AUTHOR]

DC microgrid has attracted more and more attention due to its unique characteristics, but the development of a dc microgrid is also facing some challenges, such as interruption and isolation of short-circuit fault currents. Therefore, the dc circuit breaker plays an important role in ensuring the normal work of a dc microgrid. In this paper, a novel bidirectional dc solid-state circuit breaker is proposed to realize the bidirectional flow of energy, which ensures the higher operating efficiency of the dc microgrid. Compared with other solid-state circuit breakers, the proposed novel topology has simpler structure, common ground, and fewer components. First, this paper makes a detailed analysis of the different working stages of the circuit when the fault occurs in combination with simulation results of the circuit topology. Then, the standard of selecting the components through the calculation and analysis of the circuit is given in this paper. Finally, the performance of the novel bidirectional solid-state circuit breaker is verified by experiments. [ABSTRACT FROM AUTHOR]

This paper proposes a capacitor voltage regulation method for the dual converter with a floating bridge for aerospace applications. This topology has previously been reported, but with a constrained voltage utilization factor due to the need for capacitor voltage regulations. In this paper, the effect of switching states on the voltage variation of capacitor is quantitatively modeled and an enhanced space vector modulation scheme with current feedback is proposed to achieve an active control of the floating capacitor voltages. This proposed method also allows further exploitation and utilization of converter voltage. The relationship between the allowed modulation index of dual converter and load power factor is obtained and expressed using a fitted polynomial equation. The advantages of the proposed method include boosted voltage utilization and superior performance in term of capacitor voltage balance. These advantages have been proven through simulation and experimental results on RL loads as well as with an open-end winding induction motor. The proposed modulation scheme can boost the converter voltage utilization by at least 10% while achieving full four-level operation. More importantly, the higher available voltage allows extending the constant torque region of the motor, the further beginning of field weakening operation could be postponed. [ABSTRACT FROM AUTHOR]

A trinary multilevel converter uses a few heterogeneous H-bridge submodules (SMs) to synthesize an output voltage with multiple levels. Two major limitations of this converter are that it needs multiple dc sources and it cannot operate under pulsewidth modulation (PWM). This paper addresses these limitations by adding a low-voltage H-bridge SM to this converter and proposing a new switching algorithm. The resulting PWM-based asymmetric cascaded H-bridge converter uses only one dc source and synthesizes a high-quality output voltage. This improved converter can be a potential choice for real and reactive power support in power system applications. This paper also proposes methods for stability analysis and design of this converter. Experimental case studies evaluate the performance of the proposed converter for both standalone and grid-connected modes of operation. [ABSTRACT FROM AUTHOR]

The switching speeds of next-generation power semiconductor devices, such as those made of silicon carbide and gallium nitride are roughly ten times those of conventional devices (e.g., silicon insulated-gate bipolar transistors). This increases the frequency range of the electromagnetic noise accompanying the switching operations of pulsewidth modulated (PWM) converters and worsens the influence of radiated noise. The authors have previously proposed an active common-mode filter (ACF) that reduces the radiated noise from the power cables connected to a PWM converter and evaluated its effect in reducing radiated noise by using a function generator as a common-mode (CM) noise source. In this paper, the ACF is applied to a motor drive system fed by a three-phase PWM inverter, and the attenuation characteristics of the CM voltage are evaluated. To avoid saturating the ACF, the combination of an active common-noise canceller and the ACF is discussed. The experimental results show that the system constructed in this paper can suppress the CM voltage produced by the PWM inverter over a wide frequency range from 100 to 100 MHz. [ABSTRACT FROM AUTHOR]

Electric motorcycles use a battery storage system and a controlled inverter (motor drive) to drive the wheels. Given that the sale of electric motorcycles is expected to grow significantly over the next decade, the aim of this research is to add a supercapacitor storage system to this simple network in order to extend the autonomy of the motorcycle. This paper analyzes and demonstrates the benefits of two different structures for adding a supercapacitor bank to a lithium-ion battery pack: a passive filter and a buffer for the battery. The advantages of each structure are presented and design guidelines are provided. In addition, we propose a synthetic inductor filter typology based on the two analyzed structures in order to increase the autonomy of the motorcycle. Simulations and experimental results using real data validate the analysis. This paper then uses real data extracted from an electric motorcycle to compare the four topologies: batteries only, the passive filter, the buffer, and the synthetic inductor semi-active hybrid storage system. The comparison shows that battery capacity is extended up to 7.8% with a smoother current profile. However, due to the losses from the added converter in cascade, the net capacity of the whole system is extended only up to 3.7%. Therefore, improvements in the dc/dc converter can further increase the entire system capacity. [ABSTRACT FROM AUTHOR]

This paper analyzes the effects of shunt capacitors installed on the low voltage sides of 10/0.4 kV distribution transformers on the operation of these transformers. Using the results of an extensive measurement campaign, this paper compares: real and reactive power losses, secondary-side current, and primary-side apparent power before and after the installation of transformer capacitors. The following four cases of reactive power compensation are considered and discussed: adequate, conditionally adequate, and total compensation, as well as overcompensation. The presented analysis helps to identify transformer substations where the initial compensation should be changed or adjusted, in order to improve transformers’ operational performance. Voltage dependencies of real and reactive power demands of the transformer-supplied loads are taken into account, based on the previously identified load characteristics in the considered networks as well as voltage dependence of reactive power of shunt capacitors. The result with and without including these voltage dependencies in the analysis is compared and discussed. [ABSTRACT FROM AUTHOR]

The use of LCL filters is a well-accepted solution to attenuate the harmonics created by the pulsewidth modulation. However, inherently LCL filters have a resonance region where the unwanted harmonics are amplified, which can compromise stability. Several techniques have been developed in order to tackle this issue. At first the use of passive damping, by intentionally increasing the resistance of the LCL filter components, is a simple, robust, and straightforward solution; however, it decreases the overall efficiency of the system, and hence in general is unwanted. Alternatively, active damping strategies, where the resonance damping is provided by the current controller, are of major interest. This paper analyzes the robustness of the closed-loop dynamics when different active damping techniques are implemented. The analyzed active damping techniques, which have been selected because of their readiness and simplicity, are: 1) filtered capacitor voltage feedforward and 2) second-order filters in cascade with the main current controller. The impedance/admittance stability formulation is used to model the system, which has been proven to be very convenient for the assessment of robustness. Experimental tests are provided in order to show the accuracy of the analysis and verify the findings. This paper proves that filtered capacitor voltage feedforward is a more robust and reliable solution than implementations based on cascade notch filters. [ABSTRACT FROM AUTHOR]

In this paper, the capacitances of the two-stage bushing that is installed in the 1-MV test bed for neutral beam injectors in the future fusion reactors are calculated by modeling the bushing in a 3-D electrostatic code. One of the modeling results is the stored energy in the bushing, which corresponds to 1/2 CV2. After evaluating the bushing capacitance, a MATLAB/Simulink model is presented to model the possible breakdown in the bushing and between the electrodes in the 1-MV test bed. When a breakdown occurs between anode and cathode, an overcurrent is drawing that can cause damage in the electrode surfaces while an overvoltage takes place when the breakdown happens between the bushing stages. Such damage has been observed experimentally in the past. This paper also presents some of the possible protection against the breakdown in the 1-MV test bed to dissipate the stored energy in order to protect the electrode surfaces and the bushing. The suggested protections presented in this paper are damping resistors, surge arrester individually, and both of them. Also, a coil can be added to the DR either in series or in parallel. [ABSTRACT FROM AUTHOR]

In this paper, an improved postfault strategy is introduced for modular multilevel converters, which utilizes the remaining healthy capacity of the converter more efficiently and increases the line voltage amplitude under these circumstances. Previous works proposed to use the neutral point shift in ac side and dc side of the converter simultaneously. This paper adds a comprehensive and coherent formulation, deep analyzation, and experimental validation. The main improvement of the proposed method is maximizing the line voltage amplitude using the optimum dc component and the best neutral point position. Indeed, fewer restrictions in fault numbers, fewer restrictions in load power factor, and fewer nonsolution conditions are among other improvements of a combined dc and neutral-shift method. Comparative simulation and experimental results verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

The circulating current of modular multilevel converter (MMC) has a great impact on the power losses, the submodule (SM) capacitor voltage ripples, and the rating of power devices. Existing analysis of circulating current has considered the capacitor voltage and the modulation signal. In this paper, the effect of semiconductor devices on the circulating current is further presented. In order to realize the different circulating current injection targets under different conditions, a unified online calculation scheme by using the instantaneous information of MMC is proposed in this paper to generate the circulating current injection references. It avoids detecting the amplitude and phase of the output current or using an extensive lookup table. Besides, a mathematical analysis model is built and it reveals the impact on the capacitor voltage ripple and the rms value of arm current with different injection references, thus guide the determination of the injection ratio. Experimental results based on a three-phase MMC prototype with six SMs per arm are presented to demonstrate the analysis of circulating current and the proposed circulating current injection references generating method is verified by different circulating current control targets with different loads. [ABSTRACT FROM AUTHOR]

This paper proposes a novel dc power electronic transformer (DCPET) topology for locomotive, ac/dc hybrid grid, dc distribution grid, and other isolated medium-voltage and high-power applications. Compared with conventional PET topology, the proposed DCPET has fewer power semiconductor devices and high-frequency isolation transformers, which can improve the power density and reliability. Fault handling or redundancy design can be achieved to further improve the reliability when some dc–dc modules break down. Also, input voltage sharing control can be omitted to simplify the control system and improve the stability. Meanwhile, soft switching is guaranteed for all the switches, which is beneficial to increase switching frequency and improve power density. In this paper, the principle, evolution, and control of the proposed DCPET are respectively presented and studied in detail. Finally, a prototype of the proposed DCPET is built and the experimental results verify the validity and superiority of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper presents a practical strategy for utilizing the submodule (SM) redundancy of a modular multilevel converter (MMC) for its fault tolerance. This strategy provides a systematic framework for balancing the tradeoff between two conventional methods for using the active redundancy and, thus, achieves operational flexibility. One of the existing methods improves SM reliability owing to less voltage stress on the SM components by employing all of the SMs to form the ac or dc voltages (voltage-sharing mode). The other avoids transients by keeping the average SM voltage constant at the cost of slightly increased stress on the SM components (fixed-level mode), which, however, can be controlled to provide the grid-adaptive operation by reserving the energy of the SMs not in service. We, thus, develop a new redundancy management scheme by integrating these two methods and exploiting their technical benefits to meet the PQ requirements and MMC control performance. This research provides a theoretical basis and a technical guide to determining the number of SMs, which can further increase the voltage steps as per the MMC and grid conditions. This paper also connects the remaining PQ capability of the MMC at a particular operating point with the SM redundancy concept by defining a potential redundancy, especially useful when the physical redundancy is exhausted. The theoretical findings and efficacy of the proposed strategy are validated through PSCAD/EMTDC time-domain simulations followed by experiments using a nine-level single-phase MMC system. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method for instantaneous balancing of neutral-point (NP) voltages with stacked multilevel inverters (MLIs) for variable-speed drives. The stacked MLI uses series-connected dc sources and NPs (connecting points of dc sources) to obtain the desired levels. The balancing of NP voltages are obtained by using a low-voltage-capacitor-fed cascaded H-bridge (CHB) per phase of a symmetrical six-phase induction machine (IM), which ensures zero current drawn from NPs (at any given instant). Since no current is drawn from NPs, the single dc-link operation with stacked capacitors is also possible. The scheme is suitable for applications, where low-voltage dc sources and batteries are stacked to form a dc link. A variable-speed operation is done using a seven-level inverter scheme for a symmetrical six-phase IM, which is formed by three dc-link stacked capacitors cascaded with two low-voltage-capacitor-fed CHBs per phase. Furthermore, the method is extended for an open-end IM to obtain a seven-level common-mode eliminated space vector structure using a single dc link. The generalization of this method for any stacked $n$ -level inverter without NP voltage deviation is also presented in this paper. The experimental results and analysis are included to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper introduces an averaging control strategy of the phase-unit losses of modular multilevel converters (MMCs). The quantitative analysis of the MMC phase-unit loss distribution under unbalanced ac conditions is carried out by investigating the individual component of the MMC arm currents. It shows that the unbalanced arm currents will result in unbalanced phase-unit losses. To address this issue, this paper proposes a predictive closed-loop-control-based zero-sequence voltage injection method that results in much averaged loss distribution under unbalanced ac conditions. The essence of the new method is that it adjusts the three-phase sinusoidal references so that the unbalanced arm currents are fully utilized to average phase-unit losses. This paper shows the effectiveness of the new approach by electromagnetic transient simulations on PSCAD/EMTDC. [ABSTRACT FROM AUTHOR]

Harmonic distortions at a point of common coupling (PCC) are caused by the harmonic sources in both supply system and customer facilities. In order to verify compliance with harmonic limits for an operating facility, it is essential to determine the contribution of a facility to the harmonic distortions measured at the PCC. Over the past many years, a significant amount of research work has been conducted in developing different harmonic analysis methods and especially harmonic contribution assessment methods. A common need of this line of research is consistent test systems that can be used to verify/validate a proposed method or to compare different approaches. To address this gap, a benchmark test system representing a typical medium-voltage/low-voltage network supplying industrial loads is proposed in this paper. This paper also includes examples on how to use the system to assess the performance of harmonic contribution determination methods. [ABSTRACT FROM AUTHOR]

This paper discusses a novel methodology to increase the voltage droop compensation range in generalized solid-state bipolar high-voltage Marx modulators with one resonant stage. To maintain the modularity characteristic of bipolar Marx modulators, the imbedding of additional resonant stages is not straightforward. Nevertheless, this paper proposes to add a second resonant stage to the already existing resonant-type voltage droop compensation stage. This second stage increases the voltage droop compensation percentage of a generalized solid-state bipolar Marx generator. The compensation of the bipolar pulse voltage droop is now achieved by adding two auxiliary synchronous compensation resonant voltages, to the output capacitive decaying voltage. Simulation and experimental results are presented for six Marx plus two resonant stages, 16% voltage droop, with 3-kV pulse amplitude, 100- $\mu \text{s}$ pulsewidth, 40-ms relaxation time, and 10-Hz pulse repetition rate. [ABSTRACT FROM AUTHOR]

Power management integrated circuits (PMICs) with on-chip compensation are widely used to power multiple loads in mobile devices with increased power density. However, there are two issues for on-chip compensated PMICs. First, on-chip compensation reconfigurability is required to obtain the appropriate response in various passive components. Second, a converter for a processor requires adaptive voltage positioning (AVP) to reduce the output capacitor size. In this paper, a novel reconfigurable on-chip compensated current-mode buck converter with AVP is proposed to solve the aforementioned issues without requiring high-speed and high-resolution analog-to-digital converter (ADC). A reconfigurable accurate load line control scheme and on-chip compensation are proposed to achieve an accurate load line and AVP in various load lines and passive components. The control scheme, small-signal model, and circuit implementation are illustrated in this paper. The proposed buck converter was implemented into an integrated circuit to verify the analysis. [ABSTRACT FROM AUTHOR]

In this paper, a new soft-switching bridgeless single-phase power factor correction (PFC) converter is presented and analyzed. Employing an auxiliary switch, the input current dead angle that is the main drawback of the existing buck-type PFCs is omitted, and thus, the power factor (PF) is improved, which is the main contribution of the paper. Proposed PFC converter operates under discontinuous conduction mode (DCM) and draws sinusoidal input current from power supply inherently. All switches and diodes are turnedonandoffunder soft switching, which leads to low switching losses and elimination of diode reverse recovery problems. Also, minimum numbers of semiconductor devices are in the power flow path that reduce the conduction losses. A 120-W laboratory prototype is implemented and experimental results verify the validity of theoretical analysis and show efficiency of 92.1%. In addition, total harmonic distortion (THD) of 3.3% is achieved and the input current harmonics complies with IEC61000-3-2 Class D requirements. [ABSTRACT FROM AUTHOR]

Power converters and electric motor drives when tightly regulated behave as constant power loads. These loads are different from resistive loads and have destabilizing negative impedance characteristics, which impact a system's stability. A boost converter is intrinsically nonlinear and is a nonminimum phase system at the output voltage with respect to the control input. The linear approximation of this boost converter loaded with a constant power load has a zero and poles in the right half of the $s$ -plane, making the system unstable and very difficult to control. Control techniques that employ some form of system inversion cannot be implemented for a nonminimum phase system. This paper describes a technique to modify the nonminimum phase boost converter to a minimum phase for a constant power load, further implementing the input–output linearization technique to stabilize the system. This paper also provides a methodological analysis of the problem followed by the proposed solution. Furthermore, it verifies the analysis of the proposed solution through simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a new topology based on a modified class-E resonant inverter used as an LED series current regulator. The proposed topology behaves as a controllable nondissipative impedance that adjusts the current flowing through the lamp. In this circuit, the LED is placed at the dc side of the class-E inverter, in series with the input filter inductance. The power handled by the ac side is sent back to the input by means of two diodes. Despite the addition of these two diodes, the converter maintains all the advantages of the class-E inverter: low component count, simple control, and extremely low switching losses. The LED current can be controlled with a small variation of the operating frequency. This way, the low-frequency current ripple of the lamp can be strongly reduced even when there is a considerably high input voltage excursion, such as the one expected in electrolyticless high-power-factor LED ballast. This paper proposes a simplified methodology based on the fundamental approach aiming to design and build a laboratory prototype. The prototype is designed in order to minimize the effect of LED voltage in the output current. This way, the input voltage ripple can be canceled using a simple feedforward control. [ABSTRACT FROM AUTHOR]

A high step-up dc–dc converter is proposed in this paper. The presented converter benefits from some advantages such as high voltage gain and continuous input current, which makes it suitable for the renewable energy applications. The presented converter is based on the SEPIC converter. However, the converter voltage gain is improved by employing a coupled inductor and two voltage multipliers. A passive clamp circuit is also added to the proposed converter that increases the voltage gain and reduces the voltage stress on the main switch. Thus, a switch with low $R_{{\text{DS(on)}}}$ will be needed that decreases the conduction loss. Besides, the voltage stress on the output diode in the proposed converter is reduced, which alleviates reverse recovery problem. The steady-state analysis of the proposed converter is discussed in this paper. The analysis is verified with experimental results under the output power of 245 W. [ABSTRACT FROM AUTHOR]

This paper proposes a split-capacitor four-wire current source inverter, which is the dual of the split-capacitor four-wire voltage source inverter. Since the midpoint of the dc link is tied to the neutral point of ac filter capacitors, the common-mode voltage (CMV) is reduced significantly. Consequently, the leakage current issue is effectively addressed. The proposed circuit is cost-effective as no extra switch is added. This paper, first, establishes the equivalent common-mode circuit of the proposed inverter. The impact of the neutral line inductance on CMV is also analyzed. Then, a specific modulation is introduced to balance the dc-link voltages/currents. To achieve good input/output performance, a nonlinear control method is developed based on time-domain models. Finally, all the proposed methods and related theoretical analysis are verified by simulations and experimental results. [ABSTRACT FROM AUTHOR]

An important aspect of ensuring the power integrity of a power distribution network (PDN) design is to determine the layout, value, package size, and number of decoupling capacitors. To solve the limitation of the vertical connection of the surface-mounting-type capacitor to the power net area fill, a new concept of a capacitor denoted the Z-directed component (ZDC) is proposed in this paper. There are many applications possible with the ZDC with the first implementation as a decoupling capacitor. The ZDC capacitors can be integrated within the printed circuit board (PCB) substrate directly below the package ball and eliminate the integrated circuit (IC) to decoupling capacitor horizontal distance across the power net area fill. Furthermore, the inductance associated with the vertical current paths on the vias from the IC package to the horizontal power net area fill and similarly for the surface-mounted technology decoupling capacitors is eliminated. Since only the inductance of the ZDC capacitor itself remains, there is the possibility of using far fewer capacitors to achieve a high-frequency target impedance specification. The ZDC is a promising technology that gives the PCB designer the opportunity to integrate low equivalent series inductance decoupling capacitors much closer to the noise source than traditional surface-mount capacitors. In addition, in this paper, a high-order model is introduced for the ZDC capacitor to better understand the high-frequency characteristics of the component and is verified with measurements. [ABSTRACT FROM AUTHOR]

Achieving high efficiency and high power density features of intermediate bus converter (IBC) in data center application is very critical. This paper proposes a nonisolated switched-tank dc–dc converter (STC) to meet the high requirement of IBC. The proposed STC has fixed voltage conversion ratio. Theoretical analysis provides the guideline for designing resonant tank and nonresonant tank as well as selecting proper deadtime for the proposed circuit. With resonant operation feature of the proposed circuit, zero current switching is realized on all switching devices to help the high-efficiency operation of the proposed converter. Through the proposed design methodology in this paper, power loss on switching devices and planar inductors can be minimized. In addition, detailed power loss analysis and breakdown provide hints for further efficiency improvement. Simulation has been performed to validate the operating principle of the proposed STC. A designed 6x STC (450 W nominal/600 W maximum) based on eGaNFETs is demonstrated. With 54 V typical input voltage, the output of the 6x STC is 9 V. The GaN-based prototype achieves a peak efficiency of 98.55%. Also, it achieves 97.18% efficiency and 750 W/in3 power density at 450 W. [ABSTRACT FROM AUTHOR]

This paper presents the design and construction of a sample of Marx pulsed generator based on boost converter (BC) pulse-forming networks (BCPFNs). BCPFN is used instead of the conventional Marx floors for constructing this pulsed generator. BCPFN is carried out by connecting inductors and capacitors in series and parallel modes, respectively, by using solid-state switches, and during this procedure the pulsed generator converts to BC temporarily and increases the voltage of capacitors uniformly to a considerable value. This technique causes an increase in the discharging voltage level to the load that is many times more than its dc voltage source by charging the capacitors to a greater level. In order to take advantage of the benefits of Marx generator and PFN, this paper suggests a new circuit with the minimum number of switches. It means, to compose BCPFN and Marx, we have tried to design the circuit with fewer switches and instead of it we have achieved our desired performance with changing the operating mode in the states of BC, PFN, BCPFN, and BCPFN Marx. The results are simulated with MATLAB software. At the end, the experimental results of the construction of the above-mentioned system at low-power levels are presented, and the topology’s accuracy is proved by comparing them to the results of simulation. [ABSTRACT FROM AUTHOR]

This paper discusses the control of a modular multilevel converter (MMC) used as a grid interface for the klystron modulators in the compact linear collider (CLIC). The converter has a DC side load which takes short-duration power pulses, causing high DC side power fluctuations that are not tolerable if seen by the AC grid. The DC–AC power decoupling capability of the MMC enables mitigation of the power ripple on the AC side, guaranteeing compliance with power quality requirements. However, the pulse repetition rate of the CLIC modulators is synchronized the 50-Hz AC grid and this induces permanent power imbalance in the arms of the MMC, causing voltage deviation and overmodulation unless appropriate balancing strategies are implemented. Unlike existing arm balancing methods that control 50-Hz circulating currents to balance the arm powers, the method proposed in this paper introduces an augmented modulation strategy where modulation signals are redistributed among arms based on the demand from a balancing controller. The resulting controller has lower complexity and its simple structure enables an easier design of the balancing loop, which guarantees predictable dynamics in operation. The effectiveness of the method has been demonstrated in simulation for the full-scale CLIC converter ratings and experimentally on a 7-kW MMC prototype operating with a 3.3-kA pulsed DC load. [ABSTRACT FROM AUTHOR]

A new modular pulsed-power source with fast rise time and step-wise arbitrary output waveform generation is currently under development to drive the Gepulste Elektronenstrahlanlage device investigated at the Institute for Pulsed Power and Microwave Technology (IHM). Acknowledging the complex design procedures necessary to set up a modular pulsed-power source for voltages of up to 120 kV, this paper focuses on the circuit design for a single stage and its validation prior to the generator assembly. Using a semiconductor-based Marx generator topology, the stages are designed to have an output voltage of 1 kV with a pulse current of up to 600 A. When connected to an ohmic load, the measured current rise times are in the order of 46 ns resulting in the current rise rates of up to 10 kA/ $\mu \text{s}$ using the commercial devices. The step-wise arbitrary output waveform is created by generating the switching commands on the stage using a microprocessor and a fast optical synchronization unit. Effective stage shielding is verified by operating the stage in a 100-kV, 2.5-kA electromagnetic interference test bed. This paper presents the design considerations and the corresponding measurements. [ABSTRACT FROM AUTHOR]

This paper presents theoretical and experimental discussions on low-voltage-ride-through operation of a modular multilevel single-delta bridge-cell (SDBC) inverter intended for utility-scale photovoltaic (PV) systems. Modern grid codes require grid-tied inverters to provide dynamic grid support during grid-fault events by injecting reactive current. This paper discusses decoupled positive- and negative-sequence reactive-current control, focusing on asymmetric voltage sags with imbalanced magnitude and phase relationships. The main objective is to present a feedforward control method based on calculation of the zero-sequence current required for achieving power balance during normal and grid-fault conditions. Moreover, this paper demonstrates a practical method that minimizes overcurrent stress in the three inverter clusters by adjusting active power drawn from PV arrays. Experimental results on a three-phase 12.6-kVA system prove that the SDBC inverter is capable of seamlessly operating through asymmetric voltage sags. [ABSTRACT FROM AUTHOR]

This paper presents a quantitative analysis of the losses of the hybrid cascaded modular multilevel converter (HC-MMC). Regulation of full-bridge (FB) submodule-capacitor voltages in an HC-MMC requires dedicated strategies that affect the voltage harmonics generated by the converter's main power stage and hence its switching patterns and losses. This paper uses an electromagnetic transient simulator (PSCAD/EMTDC) to estimate the semiconductor losses using the switches’ turn-on and turn-off characteristics. The paper examines the losses of a 45-MW HC-MMC for two recently introduced voltage-regulation methods based upon the modified sinusoidal pulse width modulation (PWM) and an existing method based upon the trapezoidal PWM. Losses of a conventional FB-MMC that offers dc-fault blocking capability are also investigated and compared with those of HC-MMC. The loss comparison results indicate that: first, the two voltage-regulation methods for HC-MMC based upon the modified sinusoidal PWM result in markedly lower semiconductor losses than the trapezoidal PWM method; second, compared with the original HC-MMC, a mixed submodule HC-MMC may lower the semiconductor losses at certain operating points with proper addition of mixed submodules; and finally, HC-MMC may have up to 9.0% lower semiconductor losses (relative) than the conventional FB-MMC. [ABSTRACT FROM AUTHOR]

In high-power applications, parallel-operated T-type three-level pulse width modulation (PWM) rectifiers (T3LPRs) are widely employed to improve the power capacity and system reliability. For parallel-operated T3LPRs, there are two important issues need to be properly addressed: 1) the neutral-point potential (NPP) balancing, and 2) the zero sequence circulating current (ZSCC) between the common ac and dc bus. In this paper, the fluctuation of NPP in a T3LPR and the generative mechanism of ZSCC in parallel-operated T3LPRs are first investigated. The zero sequence voltage (ZSV) difference between the parallel-operated T3LPRs is identified as the main excitation source of the ZSCC problem. Meanwhile, the disconnection of the neutral point and the control effect difference of NPP balancing in each T3LPR also affect the ZSCCs within the parallel-operated T3LPRs. To adjust the ZSV of T3LPRs, the dwell time of the positive small voltage vector in each switching period of the converter, which is usually adjusted to balance the NPP, is also required to be controlled to suppress ZSCC. Therefore, in this paper, to avoid the possible conflict, an improved modulation mechanism is designed to guarantee simultaneous ZSCC suppression and NPP balancing. The neutral points of each T3LPR are connected. Then, by adjusting the dwell time of the positive small voltage vector, the charging time of two dc capacitors is adjusted to balance the NPP, and the ZSV differences between different T3LPRs are adjusted to suppress ZSCCs. To avoid the control effect difference of independent NPP balancing in different T3LPRs, all T3LPRs share the same value marking the difference between two dc capacitor voltages. Thus, a communication with a greatly reduced baud rate requirement is needed for NPP balancing to transfer the difference between the two dc capacitor voltages. Moreover, no extra circuit is needed for ZSCC suppression. These approaches make the proposed improved space vector PWM strategy much more practical and easy to employ. The proposed method is verified with experiments on two 3-kW T3LPR prototypes. [ABSTRACT FROM AUTHOR]

This paper proposes a new single-phase single-stage switched-boost inverter with four switches. Like the quasi-Z-source inverter and quasi-switched boost inverter (qSBI), the proposed inverter has the main features as continuous input current, buck/boost voltage with single-stage conversion, and shoot-through immunity. Compared to the qSBI, the proposed inverter uses one more capacitor and one less switch. This paper presents the operating principles, pulse-width modulation control strategy, parameter design guidelines, and simulation results for the proposed inverter. To verify the performance of the proposed inverter, an 800-W prototype was built with an 110 V/50 Hz output voltage in stand-alone and grid-connected modes. The simulation and experimental results matched those of the theoretical analysis. [ABSTRACT FROM AUTHOR]

To reduce stored capacitor energy in modular multilevel converters (MMCs), previous papers propose injection of harmonics in the arm circulating currents and zero-sequence voltages. While this approach is effective, previously utilized combinations of injected harmonics significantly increase converter current ratings. In contrast, the optimization approach developed in this article identifies harmonics that simultaneously achieve capacitor energy optimization and reduced overrating of converter currents. In addition, the proposed approach eliminates the possibility of convergence to local minima, which is a significant improvement on previously proposed nonconvex optimization approaches. Experimental verification of the proposed approach is performed on a low-voltage three-phase modular multilevel converter. [ABSTRACT FROM AUTHOR]