Search

In this paper, a new soft-switching bridgeless single-phase power factor correction (PFC) converter is presented and analyzed. Employing an auxiliary switch, the input current dead angle that is the main drawback of the existing buck-type PFCs is omitted, and thus, the power factor (PF) is improved, which is the main contribution of the paper. Proposed PFC converter operates under discontinuous conduction mode (DCM) and draws sinusoidal input current from power supply inherently. All switches and diodes are turnedonandoffunder soft switching, which leads to low switching losses and elimination of diode reverse recovery problems. Also, minimum numbers of semiconductor devices are in the power flow path that reduce the conduction losses. A 120-W laboratory prototype is implemented and experimental results verify the validity of theoretical analysis and show efficiency of 92.1%. In addition, total harmonic distortion (THD) of 3.3% is achieved and the input current harmonics complies with IEC61000-3-2 Class D requirements. [ABSTRACT FROM AUTHOR]

This paper proposes a three-phase, five-level, non-regenerative pulsewidth modulated rectifier using only two active switches (minimum required) per phase, which drastically reduces gate driver requirement and hardware complexity. It draws sinusoidal input current at close to unity power factor. All the semiconductor devices are rated at only one fourth of the dc-link voltage, and none of them requires any transient voltage balancing snubber. A total of 8 out of the 14 diodes per phase undergo soft switching transition under all operating conditions, which increases its efficiency. No extra hardware circuitry for balancing the flying capacitors (FCs) or the dc-link mid-point voltage are required, which further reduces hardware complexity and increases the conversion efficiency. The proposed topology does not need any sophisticated startup procedure for charging the FCs either, which solves the problem of semiconductor overvoltage during starting. A 3-kW laboratory prototype is built to experimentally verify the proposed topology. The maximum efficiency obtained from the prototype is 98.7%, and it is always more than 96% for the load range from 15% to its rated. [ABSTRACT FROM AUTHOR]

Impedance-source inverters using coupled inductors have been investigated as alternatives for providing high step-up voltages. However, leakage inductances of the coupled inductors have commonly led to lower overall effectiveness, in addition to generating high dc-link voltage spikes. The latter raises voltage stresses of switches, which in turn, may reduce the power levels of the inverters. A high step-up Y-source inverter has therefore been proposed in this paper to provide a high boost with a smooth dc-link voltage ensured by proper recycling of the leakage energy. These features have been verified by comparing simulation and experimental results of an existing Y-source and the proposed inverters. Factors compared are their respective boost ratios, voltage stresses, current stresses, and dc-link voltage spikes. [ABSTRACT FROM AUTHOR]

The ultra-high voltage gain dc–dc converters are extremely required because of the low voltage level of many nonpolluting power resources. This paper proposes an ultra-high voltage gain converter based on an interleave technique and using three-winding coupled inductor and voltage multiplier cell. The interleave technique is useful for reducing the size of the filter components. In the proposed converter, high voltage gain is achieved without extreme duty cycle of solid-state switches. The voltage stress across the semiconductor devices can be reduced by increasing the turn ratio of the secondary of the coupled inductors. In addition, because of the implementation of the interleave structure, peak-to-peak variation of the main input current and switching losses are substantially reduced. The steady-state principles of the proposed converter in continuous conduction mode operation are given. Also, design equations are presented. Validity and performance of the proposed converter are surveyed by simulation and experimental results of a 120 W prototype. [ABSTRACT FROM AUTHOR]

This paper presents a dual output power factor correction (PFC) converter for switched reluctance motor (SRM) drives. Here, a modified single-ended primary inductance converter (SEPIC) is proposed for a wide range of speed control and to achieve PFC at ac mains. The switching frequency of the converter is considered to be 20 kHz. The converter is designed to operate in the discontinuous conduction mode (DCM) of operation, which reduces the size of the output inductor. The DCM mode to obtain PFC also reduces the sensor requirement as compared to the continuous conduction mode (CCM), where two voltage sensors and one current sensor add to the drive cost. The drive is proposed for universal ac mains (90–270 V ac). Simulated and experimental results are demonstrated to validate the performance of the drive during different operating conditions. The input current total harmonic distortion is reduced to comply with an IEC 61000-3-2 standard. [ABSTRACT FROM AUTHOR]

Pollution problems caused by fossil fuels have led to more investigations on renewable energy systems. Photovoltaic cells and fuel cells output low-level voltage than required; therefore, high gain dc–dc converters are used to boost this low voltage. The Z-source converter can be employed as dc–dc converter to boost the photovoltaic panel voltages. It also offers other advantages, such as clamped switched voltage, high voltage gain, isolation of energy source from the load, and positive polarity for output voltage; therefore, this is a good choice for high step-up applications. This paper presents analysis of a novel high step-up Z-source based dc–dc converter that has higher voltage gain than the Z-source converter. Furthermore, high efficiency, low device voltage stress, and wide voltage gain range make it a good candidate for photovoltaic and high voltage step-up applications. The proposed dc–dc converter is evaluated experimentally for converting 24-V dc input to 300-V dc output at 100 W and to validate the simulation results. [ABSTRACT FROM AUTHOR]

This paper presents nonisolated single-switch high step-up converters with low voltage stress. Based on the conventional flyback converter, one single-switch high step-up converter is derived. The voltage stresses on the switch and diodes are limited by using a clamping diode and voltage doubler structure. Also, to further reduce the voltage stresses of them, another single-switch high step-up converter is proposed simply by using one additional capacitor and rearranging the components. Thus, lower voltage-rated switch and diodes can be used, which results in higher efficiency. The operational principle, analysis and design considerations of each converter are presented in this paper. The validity of this study is confirmed by the experimental results from 24 V input and 250 V/125 W output prototype. [ABSTRACT FROM AUTHOR]

In this paper, a compact circuit topology is presented for pulsed power generation with a semiconductor opening switch (SOS). Such circuits require the generation of a fast forward current through the diode, followed by a reverse current that activates the recovery process. In general, magnetic switches are used to switch the diode current from forward to reverse. Therefore, adjustment of the output voltage of an SOS pulser is difficult. This paper introduces a circuit that allows an adjustable output voltage of the pulser. A solution is realized with a premagnetizing circuit on the primary winding of a pulse transformer (PT), so that a third winding is not needed. The primary capacitor voltage can now be varied while maintaining proper saturation of the PT. [ABSTRACT FROM PUBLISHER]

In this paper, a novel transformerless interleaved high step-down conversion ratio dc–dc converter with low switch voltage stress is proposed. In the proposed converter, two input capacitors are series-charged by the input voltage and parallel-discharged by a new two-phase interleaved buck converter for providing a much higher step-down conversion ratio without adopting an extreme short duty cycle. Based on the capacitive voltage division, the main objectives of the new voltage-divider circuit in the converter are for both storing energy in the blocking capacitors for increasing the step-down conversion ratio and reducing voltage stresses of active switches. As a result, the proposed converter topology possesses the low switch voltage stress characteristic. This will allow one to choose lower voltage rating MOSFETs to reduce both switching and conduction losses, and the overall efficiency is consequently improved. Moreover, due to the charge balance of the blocking capacitor, the converter features automatic uniform current sharing characteristic of the interleaved phases without adding extra circuitry or complex control methods. The operation principles and relevant analysis of the proposed converter are presented in this paper. Finally, a 400-V input voltage, 25-V output voltage, and 400-W output power prototype circuit is implemented in the laboratory to verify the performance. [ABSTRACT FROM PUBLISHER]

A novel isolated dc–dc converter is proposed, using the T-Type topology with zero voltage switching and pulse width modulated with a capacitive output filter. It uses four switches, two of which are subjected to the input voltage, and the other two to half the input voltage. All switches commutate under zero voltage over a wide load range. The proposed converter has the following features: (a) symmetrical operation of the isolation transformer, (b) modulation by pulse width with constant frequency, (c) zero voltage switching, and (d) three-level voltage applied to the primary winding of the transformer. Theoretical analysis, design example, and experimental data for a 2 kW, 400 VDC input, 400 VDC output, and 50 kHz switching frequency laboratory prototype, working in two operating points are included in this paper. The measured efficiency was 95% at 950 W. [ABSTRACT FROM AUTHOR]

This paper presents a dc–dc boost converter with high voltage gain based on the three-state switching cell for split-capacitor neutral-point-clamped inverters. The proposed converter is analyzed considering the operation in continuous conduction mode and duty cycle higher than 0.5, which corresponds to overlapping mode. The main characteristics of the topology are operation at high switching frequency, whereas the input inductor is designed for twice such frequency; in order to minimize weight and volume, the voltage stress across the switches is lower than half of the output voltage and naturally clamped by one output capacitor, allowing the use of MOSFET transistors with reduced intrinsic on-resistance; the input current presents small ripple; the output voltage can be further stepped up by increasing the transformer turns ratio without compromising the voltage stress across the switches; and the output voltage is naturally balanced, thus making the converter suitable for supplying split-capacitor inverters. Several topologies where a high voltage step-up is possible are initially investigated in the literature. Then, the principle of operation and experimental results for a 1-kW prototype are presented to validate the theoretical analysis and demonstrate the converter performance. [ABSTRACT FROM PUBLISHER]

Nowadays, use of multilevel inverters in high-power applications clearly can be seen. High quality and lower distortion of the output voltage and low blocking voltage of semiconductor switches are being presented as the major privileges of the multilevel inverter compared to the traditional voltage source inverter. In this paper, a new topology of multilevel inverter is proposed as fundamental block. The proposed topology is generalized using series connection of the fundamental blocks. The proposed multilevel inverter has been analyzed in both symmetric and asymmetric operation modes. A great perfection in voltage levels number with minimum switching devices has been obtained in both symmetric and asymmetric modes. Thereafter, a detailed study of losses and peak inverse voltage (PIV) of the proposed multilevel inverter is given. Also, in continuation, a comparison between the proposed topology and the traditional one and a recently developed topology is carried out. Finally, a computer simulation using MATLAB/Simulink is presented and a laboratory prototype implementation verifies the results. [ABSTRACT FROM AUTHOR]

A novel high step-up dc–dc converter for a distributed generation system is proposed in this paper. The concept is composed of two capacitors, two diodes, and one coupled inductor. Two capacitors are charged in parallel, and are discharged in series by the coupled inductor. Thus, high step-up voltage gain can be achieved with an appropriate duty ratio. The voltage stresses on the main switch and output diode are reduced by a passive clamp circuit. Therefore, low resistance R DS(ON) for the main switch can be adopted to reduce conduction loss. In addition, the reverse-recovery problem of the diode is alleviated, and thus, the efficiency can be further improved. The operating principle and steady-state analyses of the voltage gain are also discussed in detail. Finally, a 24-V input voltage, 400-V output voltage, and 400-W output power prototype circuit of the proposed converter are implemented in the laboratory to verify the performance. [ABSTRACT FROM AUTHOR]

This paper presents a novel topology for the generation of high voltage pulses that uses both slow and fast solid-state power switches. This topology includes diode-capacitor units in parallel with commutation circuits connected to a positive buck-boost converter. This enables the generation of a range of high output voltages with a given number of capacitors. The advantages of this topology are the use of slow switches and a reduced number of diodes in comparison with conventional Marx generator. Simulations performed for single and repetitive pulse generation and experimental tests of a prototype hardware verify the proposed topology. [ABSTRACT FROM AUTHOR]

This paper describes the operation of a solid-state series stacked topology used as a serial and parallel switch in pulsed power applications. The proposed circuit, developed from the Marx generator concept, balances the voltage stress on each series stacked semiconductor, distributing the total voltage evenly. Experimental results from a 10 kV laboratory series stacked switch, using 1200 V semiconductors in a ten stages solid-state series stacked circuit, are reported and discussed, considering resistive, capacitive and inductive type loads for high and low duty factor voltage pulse operation. [ABSTRACT FROM AUTHOR]