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Four-level hybrid-clamped inverter is a newly proposed topology that can operate under a wide voltage range without switches connected in series. However, when it is applied in medium voltage high power conversions, the flying capacitors in each phase will occupy a huge volume and a high switching frequency is required to restrain the voltage ripples. In order to overcome this drawback, a four-level active neutral-point clamped inverter is discussed in this paper, which consists of only six switches and no diodes or flying capacitors are required. In order to balance the neutral-point voltages under the full power factor and modulation index range, a capacitor voltage balance method based on carrier-overlapped pulsewidth modulation is proposed in this paper. The upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection and the central dc-link capacitor voltage is balanced by adjusting the duty cycles of switching signals slightly. Simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n-level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme. [ABSTRACT FROM AUTHOR]

Motors and inverters are increasingly being used in vehicles. As more vehicle components are being adopted, requirement for safety and installation space are increasing. Growing attention is being paid to the use of six-phase permanent magnet synchronous motors (PMSMs) and their parallel control by two inverters, because of their reduced size and enhanced safety. This paper proposes a pulsewidth modulation (PWM) control algorithm for a six-phase PMSM. In low-voltage vehicle components such as electric power steering, the current is usually acquired with resistors placed under the low-side switching devices. In the proposed control algorithm, the neutral voltage of the two inverters is shifted to either a lower or higher voltage within a certain range to allow for the signal conditioning time delay after the switching device turns on or off, and the time taken for the phase current to rise or settle. The paper proposes a novel PWM control algorithm that ensures that the on-time of the low-side switching devices satisfies the restriction on current sensing with resistors and reduces the current in the capacitor at the same time. The work contributes to reducing the current in a practical configuration involving low-voltage vehicle components. [ABSTRACT FROM AUTHOR]

This paper presents two capacitor voltage balancing (CVB) strategies for modular multilevel converter (MMC) applications. Both balancing schemes are based on model predictive control and are designed to efficiently solve a constrained optimal control problem, where the predicted capacitor voltage errors are included in the cost function with the demanded output voltage of a cluster being forced through an equality constraint. The first method proposed in this paper computes specific modulation indexes for each module using the explicit solution of a relaxed version of the original optimization problem. The second approach proposed in this paper reduces the complexity of the original problem by linearizing the objective function and using an optimal sorting network based on a greedy algorithm to solve this approximation. Considering the structures of both solution approaches, they are integrated into modulation schemes based on phase-shifted and level-shifted pulsewidth modulation algorithms, respectively. Experimental results obtained from a nine-cell single-phase MMC prototype demonstrate the good performance achieved with the proposed methodologies, as well as the implementation simplicity offered by the proposed CVB algorithms. [ABSTRACT FROM AUTHOR]

This paper presents a novel fault-tolerant method for active–neutral-point-clamped (ANPC) inverter using a modified carrier-based pulsewidth modulation. At a fault event, the ANPC inverter is divided into subinverters, and the modulating signal is modified to two modulating signals. The modified modulating signals are used to control the subinverters and allow continuous operation of the three-level ANPC inverter during faulty conditions even up to four open-switch faults per phase. This technique provides the fault-tolerant capability of the ANPC inverter without the need to add any additional phase legs or complex control strategies. Furthermore, the proposed technique ensures the voltage balancing of the dc-link capacitors. The performance of the proposed fault-tolerant technique is verified through simulation studies in MATLAB/Simulink under different faulty conditions. The feasibility of the proposed technique is also verified experimentally. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. [ABSTRACT FROM AUTHOR]

The Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. The unique feature of the ZSI is that it can operate either in buck or boost mode with a wide range of obtainable output voltages from a given input voltage. This topology also exhibits better electromagnetic-interference noise immunity when compared to a traditional voltage-source inverter (VSI). However, the LC impedance network of ZSI significantly increases the size and cost of the power converter and can make it unsuitable for low-power applications. This paper proposes a novel topology called switched boost inverter (SBI) which exhibits similar advantages of ZSI with lower number of passive components and more active components compared to ZSI. The steady-state and small-signal analyses of SBI, along with its pulsewidth modulation (PWM) control strategies, have been discussed in this paper. This paper also presents a comparison of SBI and ZSI with the same input and output parameters. The theoretical analysis given in this paper has been validated using a laboratory prototype of SBI, and the experimental results are presented for verification. The experimental harmonic spectrum of the inverter's output voltage with the proposed PWM technique is also plotted and compared with that of a traditional VSI. All the experimental results show good correlation between theory and experiments. [ABSTRACT FROM PUBLISHER]

Applying pulsewidth modulation (PWM) to control the gain in audio codecs for mobile applications leads to several advantages, such as the smooth control of tuning parameters, smaller silicon area, and lower power consumption, as compared with other tuning techniques using programmable gain amplifiers and zero crossing detectors. The PWM has to be embedded into the main signal path, preferably in a closed-loop control scheme, in order to exploit its benefits. However, the insertion of dithering and offset controls in a gain setting loop poses the problem of controlling their effects in all gain conditions. This paper reports a novel technique aimed at solving the associated issues and limitations, and provides the experimental proof of the concept through the implementation of a test-chip design on silicon. In particular, this paper reports the design and experimental results of a delta–sigma analog-to-digital converter featuring a click-free gain control technique, dithering insertion, and idle-tone shifting, which has been implemented in a 40-nm complementary metal–oxide–semiconductor technology for commercial telecom audio codec applications. [ABSTRACT FROM PUBLISHER]

Multimodule converter-based high-voltage dc (HVDC) power transmission incorporates numerous voltage-source converters (VSCs) connected in series/parallel to provide increased voltage/current and, hence, power ratings. When a selective harmonic elimination pulsewidth-modulation (SHE-PWM) technique is employed, the switching losses of the VSC modules are reduced but the voltages of the series-connected dc capacitors are not naturally balanced. In this paper, a voltage-balancing technique is reported. The technique relies on monitoring the voltage of each dc capacitor and when such voltage exceeds its preset band, the realization of the multilevel waveform reallocates the task to another VSC module to ensure that voltage balance between all capacitors is achieved. Three-phase bipolar VSC modules are considered in this paper and each one is modulated by a precalculated multilevel SHE-PWM waveform. The time-domain waveforms and their line-to-line voltage spectra are verified by simulation using PSCAD/EMTDC. The selected results are presented to confirm the viability of the proposed method. [ABSTRACT FROM PUBLISHER]

This paper proposes a new space-vector pulsewidth modulation (SV-PWM) strategy for a three-level neutral point clamped inverter. The presented SV-PWM strategy makes it possible to control the neutral point voltage by optimum choice of switch sequence for any position and length of output voltage vector. The proposed solution takes into consideration the unbalance of the dc-link voltages. It also analyzes the influence of vector sequences on the predicted unbalance of the dc-link voltage. The solution allows selecting optimum vectors and their on-time durations in order to reduce quickly the dc-link voltage unbalance. The calculation of the space vector area proposed in this paper takes into consideration voltage unbalance and its influence on the length and position of vectors. The proposed approach assures properly generating the voltage output vectors, even in the case of the existing large voltage unbalance in the dc-link. The results of the experimental investigation of the proposed modulation strategy are presented in this paper. [ABSTRACT FROM PUBLISHER]

The large number of voltage levels in a modular multilevel converter (MMC) make staircase modulation a feasible alternative, particularly in high-power applications. However, staircase waveforms do not necessarily mean operation of the MMC submodules (SMs) at the fundamental frequency. This paper presents an analysis of SM switching frequencies in staircase-modulated MMCs and their correlation to the modulation index and load phase angle. A carrier-based pulsewidth-modulation (CB-PWM) equivalent technique is also developed. This analysis demonstrates that CB-PWM techniques provide a similar switching frequency with superior harmonic performance and improved voltage balancing characteristics at all modulation indices compared to staircase modulation. The theoretical analysis is verified with extensive simulation results for MMCs with different SMs and experimental results from a laboratory prototype. [ABSTRACT FROM PUBLISHER]

This paper proposes the pulsewidth modulation (PWM) strategy of Z-source inverters (ZSIs) with minimum inductor current ripple. In existing PWM strategy with single-phase shoot-through, the shoot-through time interval is divided into six equal parts, therefore the three phase legs bear the equal shoot-through time interval. In this manner, the allotment and arrangement of the shoot-through state is easy to realize, but the inductor current ripple is not optimized. This causes to use relatively large inductors. In the proposed PWM strategy, the shoot-through time intervals of three phase legs are calculated and rearranged according to the active state and zero state time intervals to achieve the minimum current ripple across the Z-source inductor, while maintaining the same total shoot-through time interval. The principle of the proposed PWM strategy is analyzed in detail, and the comparison of current ripple under the traditional and proposed PWM strategy is given. Simulation and experimental results on the series ZSI are shown to verify the analysis. [ABSTRACT FROM PUBLISHER]

This paper proposes a zero-voltage switching (ZVS) pulsewidth modulation (PWM) dc/dc converter with current double rectifiers to achieve ZVS for all switches under a wide range of load conditions and input voltages. Two three-level PWM circuits sharing the same power switches are adopted in the proposed converter to reduce the voltage stress of each MOSFET at Vin/2 and achieve load current sharing. Thus, the current stress and power rating at the secondary-side components are reduced. The current double rectifiers are used at the secondary side to partially cancel the output ripple current. Thus, the sizes of the magnetic components and output filter capacitance are reduced. Due to the resonant behavior by the resonant inductance and resonant capacitance at the transition interval, all switches are turned on at ZVS. The experimental results based on a 1-kW prototype are provided to verify the operation principle of the proposed converter. [ABSTRACT FROM PUBLISHER]

This paper presents a soft-switching pulsewidth modulation (PWM) nonisolated boost dc–dc converter embedding an edge-resonant switched capacitor (ER-SWC) cell and its interleaved circuit topology. The conceptual boost dc–dc converter treated herein can achieve high-frequency zero-current soft-switching turn-on and zero-voltage soft-switching turn-off operations in the active switches and minimization of a reverse recovering current in the freewheeling diode under discontinuous conduction mode partially including critical conduction mode in the input current. Those advantageous properties enable a wide range of soft-switching operations together with a high-voltage step-up conversion ratio with a reduced current stress. Circuit design guideline based on the soft-switching range is introduced; then, a theoretical analysis is carried out for investigating the step-up voltage conversion ratio. For demonstrating the effectiveness of the ER-SWC soft-switching PWM boost dc–dc converter and its newly developed interleaved topology, laboratory prototypes are evaluated in experiments; then, their performances are discussed from a practical point of view. [ABSTRACT FROM PUBLISHER]

A neutral-point-clamped three-level inverter with small dc-link capacitors is presented in this paper. The inverter requires zero average neutral-point current for stable neutral-point voltage. The small dc-link capacitors may not maintain capacitor voltage balance, even with zero neutral-point current. This may happen due to nonlinearities present in the circuit. This requires a fast control of the neutral-point voltage. A simple carrier-based modulation strategy which allows modeling of the neutral-point voltage dynamics as a continuous function of power drawn from the inverter is proposed. This continuous model shows that the neutral-point current is proportional to the power drawn from the inverter, and it enables the use of a well-established classical control theory for the neutral-point voltage controller design. A simple proportional integral controller is designed for the neutral-point voltage control on the basis of the continuous model. The design method for optimum performance is discussed. The implementation of the proposed modulation strategy and the controller is very simple. The controller is implemented in a 7.5-kW induction machine-based drive with only 14 \mu \F dc-link capacitors. Also, the experimental results show that fast and stable performance of the neutral-point voltage controller are achieved and thus verify the validity of the proposed control approach. [ABSTRACT FROM PUBLISHER]

A modified single-phase quasi-Z-source ac-ac converter is proposed in this paper. The proposed converter has the main features in that the output voltage can be bucked or boosted and be both in-phase and out-of-phase with the input voltage. The input voltage and output voltage share the same ground, the size of a converter is reduced, and it operates in a continuous current mode. A safe-commutation strategy for the modified single-phase quasi-Z-source ac-ac converter is used instead of a snubber circuit. The operating principles and a steady-state analysis are presented. A laboratory prototype, tested using a resistive load, a passive load, and a nonlinear load, was constructed that used an input voltage of 70 Vrms /60 Hz in order to verify the performance of the modified single-phase quasi-Z-source ac-ac converter. The experimental results verified that the converter has a lower input current total harmonic distortion, a higher input power factor, and a higher efficiency in comparison to a conventional single-phase Z-source ac-ac converter. In addition, the experimental results show that the use of the safe-commutation strategy is a significant improvement, as it makes it possible to avoid voltage spikes on the switches. [ABSTRACT FROM AUTHOR]

A five-level flying-capacitor (FC)-based active-neutral-point-clamped (ANPC) converter is an arrangement of a three-level ANPC converter and a two-level cell. In this paper, a control strategy is proposed to regulate the voltage across the FCs at their respective reference voltage levels by swapping the switching patterns of the switches based on the polarity of the output current, the polarity of the FC voltage, and the polarity of the fundamental line-to-neutral voltage under selective harmonic elimination pulsewidth modulation. The voltage across the FCs and the dc-link capacitors are simultaneously controlled at their reference voltage levels. The proposed control strategy is applied using power system computer aided design/electromagnetic transients including dc on a static synchronous compensator operating under a power-factor-correction mode to verify its performance. Experimental results are also presented for low and high number of angles per quarter period using a low-power laboratory prototype. [ABSTRACT FROM AUTHOR]

This paper proposes a zero-voltage-transition (ZVT) pulsewidth-modulated (PWM) synchronous buck converter, which is designed to operate at low voltage and high efficiency typically required for portable systems. A new passive auxiliary circuit that allows the main switch to operate with zero-voltage switching has been incorporated in the conventional PWM synchronous buck converter. The operation principles and detailed steady-state analysis of the ZVT PWM synchronous converter with a passive auxiliary circuit are presented. All of the semiconductor devices aside from the main switch operate under soft-switching conditions. Thus, the auxiliary circuit provides a larger overall efficiency. The feasibility of the auxiliary circuit is confirmed by the simulation and experimental results. [ABSTRACT FROM PUBLISHER]