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In this paper, the pulsewidth modulation switch method was used to investigate the effect of the transformer leakage inductance on the small-signal model in isolated full-bridge converter. A galvanic isolated hard-switching full-bridge converter that operates in constant-current mode is analyzed, confirming that leakage inductance significantly affects the small-signal model, and the influence of leakage inductance can be equivalent to a resistance in series with the converter's output LC filter just as that in phase-shifted full-bridge converter. However, the same leakage inductance in these both converters will lead to different equivalent resistance due to different operating principles. Results of the modified model, simulations, and the experiments are compared to verify the correctness of the model. Moreover, this paper also shows that the Norton equivalent circuit of the charger operates in constant current mode, which can be used to estimate the dynamic behavior of the system. [ABSTRACT FROM AUTHOR]

Dual-comparison one-cycle control for the bidirectional power flow in single-phase grid-connected converters is proposed in this paper. Advantages of dual-comparison one-cycle control when compared to conventional one-cycle control is that it does not give any steady-state dc offset, no light-load instability, and implements unipolar pulsewidth modulation without having to sense the grid voltage. Addition of a fictitious current term, which is generated from the gating signal of one of the active devices, using a bandpass filter, enables the bidirectional power flow. The quality factor of the bandpass filter is shown to impact the total harmonic distortion in current, fundamental displacement angle, and steady-state dc offset. The optimal value of a quality factor, obtained with aid of simulations, gives a superior performance. The current drawn or injected into the grid is seen to lag the grid voltage. The reason for a nonunity displacement power factor is analyzed and a compensation to achieve a unity displacement power factor is also proposed in this paper. Detailed simulation and experimental studies are carried out to validate the proposed control and the high performance that can be obtained. [ABSTRACT FROM AUTHOR]

Multilevel converters with floating capacitors (FCs) are widely applied in recent years in a wide range of industrial applications from high-voltage direct current systems to high power drives. However, some FC topologies lack complete FC voltage balancing capability due to the inherent topology limitation or the insufficient switching state for capacitor balancing. This will result in large ripples on capacitors at low frequency (such as fundamental frequency), limiting their performance and application, particularly, when the fundamental frequency is very low in low-speed drive operations. Typical examples of those multilevel converters are modular multilevel converters (MMC), nested neutral-point-clamped (NNPC) converter, etc. In order to improve the FC balancing for this kind of multilevel converters, this paper proposes a carrier-based pulse-width modulation (PWM) method, named stair edge PWM method. This method can obtain sufficient redundant switching states for FC voltage balancing by producing multiple levels in one PWM period. The FC voltage balancing is thus achieved at switching frequency, which can greatly reduce the capacitor voltage ripple and therefore enable the use of much smaller FCs. Meanwhile, the voltage stress on each device and low $dv/dt$ feature are still the same as the normal multilevel operation, reserving two of the most salient features of multilevel converters. The proposed method also features much simpler and easier implementation compared with space-vector-based approaches, particularly when high-level converters are considered. An application example using a four-level NNPC converter is provided in this paper. The effectiveness and performance of the proposed method are verified by both simulation and experiment. [ABSTRACT FROM AUTHOR]

The neutral-point voltage-balancing control is a critical issue of a neutral-point-clamped converter. The conventional control strategy is to inject the specific zero-sequence voltage to regulate the redundant vector, but it is unacceptable to the three-phase four-wire system. This paper provides a neutral-point voltage-balancing control by the dipolar modulation, and the control freedom of the zero-sequence voltage is flexible. Therefore, the proposed method is suitable for both three-phase three-wire and three-phase four-wire systems. Besides, the proposed method improves the control dynamic in a reactive power system. The proposed neutral-point voltage-balancing control is verified by the mathematical analysis and experimental results. The control dynamic, power loss estimation, and the output current performance are analyzed in this paper. [ABSTRACT FROM PUBLISHER]

The modular multilevel converter (MMC) with nearest level modulation (NLM) is widely used in the high voltage applications for low switching frequency and easy implementation. Existing literature has not provided a complete submodule (SM) fault ride-through scheme for MMC with NLM. In this paper, a strategy including fault detection, localization, redundancy, and recovery is proposed to ensure continuous operation of MMC under IGBT open-circuit faults conditions. It only requires a few hardware and software resources. The features of MMC and SMs with three types of failures are studied, respectively. Based on these, the fault detection method is proposed by using a simple hardware circuit, thus high computation complexity is avoided. Since current fault localization schemes are limited to MMC with carrier phase shifted pulse width modulation, this paper further proposes a strategy for MMC with NLM to locate the faulty SM and identify the fault type. After this, the fault redundancy and the proposed fault recovery method are applied to eliminate the fault and then exit the failure state. Therefore, the ability of SM fault ride-through can be realized. Analysis of failure characteristics are verified in simulation. Experimental results based on a single-phase MMC prototype with 11 SMs per arm are presented to demonstrate the validity of the proposed fault ride-through strategy. [ABSTRACT FROM AUTHOR]

This paper introduces a novel five-level nested neutral point piloted (NNPP) converter and analyzes the operating principle of five-level NNPP converter. This paper presents a novel space vector pulse width modulation (SVPWM) algorithm based on gh coordinate for five-level NNPP converter. First, the common-mode voltage is reduced by choosing the appropriate redundant switching states. After that, the floating-capacitor voltage balance control strategy is presented. The appropriate switch combinations of each phase are determined by the control requirements of floating-capacitor voltages respectively and the hardware mapping method of the switching states is presented. Furthermore, the neutral-point voltage balance control strategy is presented. In order to balance the dc-link capacitor voltages, the seven-segment switching sequence is selected according to the control requirements of dc-link capacitor voltages and the neutral-point voltage regulatory factor is introduced to regulate the durations of the redundant switching states in a switching cycle. Finally, the validity of the novel SVPWM algorithm with decoupling control strategies of floating-capacitor voltages and dc-link capacitor voltages is verified by the experimental results of five-level NNPP converter under steady-state and dynamic conditions. [ABSTRACT FROM AUTHOR]

This paper analyzes three different carrier-based modulation patterns applied to a three-phase high-power-factor-corrected (PFC) five-level buck+boost-type converter acting as an interface between dc distribution systems and an ac grid. The modulation is analyzed employing the space vectors theory so that the achievable performance is demonstrated. The main advantage of the analyzed modulation strategy is its simplicity, which makes it suitable for digital signal controller (DSC) implementations. This seems straightforward for voltage source converters, but is a challenge for current-multilevel converters that typically employ field-programmable gate array devices to achieve better harmonic distortion performance. This is due to modern power electronics DSCs being typically designed for other converter topologies. The power converter is constructed with two phase-shift-modulated six-switch buck-type PFC converters, paralleled by interphase transformers, and an inverting circuit. The system features: bidirectional current carrying capability; relatively low parts count; high utilization of the semiconductors; and low current and voltage ripple at its terminals. The principle of operation, detailed description, analysis of the modulation strategy, and dimensioning equations for three different power circuit realizations are described in this paper assuming the analyzed modulation patterns. The feasibility of the presented converter is demonstrated by means of a constructed hardware prototype. [ABSTRACT FROM AUTHOR]

In this paper, a highly reliable back-to-back (BTB) power converter is proposed for doubly fed induction generator-based wind turbines (DFIG-WTs). When a power switch open-circuit fault is encountered in either the grid-side converter (GSC) or the rotor-side converter (RSC), a four-switch three-phase (FSTP) topology is formed to avoid using redundant bridge arms, which reduces the power circuit complexity and minimizes the conduction and switching losses. A simplified space vector pulsewidth modulation technique is used to eliminate sector identification and complex trigonometric calculations. In addition, the influence of dc-bus capacitor voltage unbalance on the electromagnetic torque is analyzed in detail. The offset current components are calculated, and they are deducted from the reference values in the modified control strategies to suppress the dc-bus voltage deviation. Moreover, the power loss model of a BTB converter is analyzed in detail, and the efficiency study is performed in various post-fault situations. Simulations in MATLAB/Simulink are carried out to verify the performance of a DFIG-WT based on a FSTP BTB converter. Furthermore, the control hardware-in-the-loop setup with RSC and GSC separately simulated in a digital real-time simulator is applied for experimental verification of the proposed control strategy. [ABSTRACT FROM AUTHOR]

Photovoltaic (PV) systems containing a rechargeable battery as an energy buffer require multiple dc–dc converters for PV panel control and battery regulation, and hence, they are prone to be complex and costly. To simplify the system by reducing the number of converters, this paper proposes the nonisolated switched capacitor converter (SCC)-based multiport converter (SC-MPC) for standalone PV systems. The proposed SC-MPC can be derived by integrating a bidirectional pulsewidth modulation (PWM) converter, series-resonant converter (SRC), and an SCC with sharing switches. PWM and pulse frequency modulation (PFM) controls are employed for the PWM converter and SRC, respectively, to regulate either a battery voltage, output voltage, or input power from a PV panel, depending on power balance among the input, battery, and load. The 150-W prototype was built for an experimental verification, and the results demonstrated the output voltage could be regulated independently on the battery voltage or input port of PV panels. [ABSTRACT FROM AUTHOR]

An adaptive control of DPWM implementable in clamped-three-level inverters with two strings of photovoltaic (PV) panels in cascaded connection is proposed in this paper. The proposed modulation is developed based on the so-called circuit-level decoupling concept. It is able to provide balance line voltage even under unbalanced dc links. The unequal dc voltages appeared due to asymmetric maximum point of power trackings (MPPTs) are controlled by proper injection of zero-sequence voltage to the common mode voltage, while the total dc voltage is regulated based on the voltage commands generated by the MPPT of each string. Thus, both PV strings are able to be operated based on their MPPTs while there is almost no low-order harmonic distortion at the inverter output current. Compared with the previous methods, the high capability of the proposed method is evaluated by simulation study and experimental tests. [ABSTRACT FROM AUTHOR]

This paper investigates an ac–dc–ac multilevel power converter. The studied configuration is composed of two single-phase ac–dc–ac three-leg modules and series-connected H-bridges in the shared part of system. Because the proposed converter has shared legs between the input and output, it is employed in applications with same input and output frequency. Uninterrupted power supply and unified power quality conditioner are application examples for this converter. Such multilevel topology has lower dc-link voltage rating, which, consequently, presents low switch blocking voltages when compared to conventional topologies. System model, a space-vector pulsewidth modulation (PWM) strategy to symmetrical and asymmetrical dc-link voltages, and an overall control strategy to adjust the system variables are presented. A power flux analysis shows the operation zone in which the individual dc-link voltage balancing is possible. PWM and control strategies are developed to reduce the semiconductor total losses, harmonic distortion, and switching stress. Two ac–dc–ac multilevel conventional structures are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper investigates a multilevel inverter composed of series/parallel-connected H-bridges. The presented structure can be used for applications in which the use of semiconductor switches with low-voltage and low-current ratings is intended. A comprehensive system model, an overall control strategy to adjust the output voltage with constant magnitude and frequency, and a level-shifted PWM (LS-PWM) strategy based on a voltage vectors unidimensional analysis and a plane analysis are presented. The LS-PWM is capable of mitigating the low-frequency circulating current, thus generating multilevel voltage signals with low harmonic distortion, maximum number of levels, and low dv/dt. In addition, considering a wide range of values of voltages and currents and various power levels, the total converter losses are reduced compared with the conventional multilevel converters. Two multilevel conventional inverters with the same number of semiconductor switches are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

An optimal current control strategy for asymmetrical hybrid multilevel inverters (MLIs) is proposed in this paper enabling their use on motor drives, static synchronous compensators, and photovoltaic and wind generators, where a fast and precise current regulation is required. A key feature of these highly efficient converters is that an ac machine (motor or transformer) operates according to an open-end winding configuration, connected on one side to a main MLI and, on the other side, to an auxiliary two-level inverter (TLI). The first efficiently controls the main power stream operating at a low switching frequency, while the TLI acts as an active power filter, exploiting a conventional high-frequency two-level pulsewidth modulation (PWM) technique. The proposed control scheme optimally exploits the key features of the two inverters by suitably sharing the control task. In fact, a predictive current control is assigned to the MLI, which can be accomplished by low switching frequency operations, while the high switching frequency of the PWM-operated TLI is exploited to accomplish a fast and precise closed-loop current control, processing only a part of the power stream flowing through the system, thus producing low power losses. Simulations and experimental results confirm the consistency of the proposed approach. [ABSTRACT FROM AUTHOR]

This paper illustrates the application of a solving method of linear systems to a multilevel inverter. This study applies a generic pulsewidth modulation (PWM) method to a multilevel topology. This method finally highlights some specific modulation schemes. First, the study describes the mathematical model of the inverter leg. The leg is made of three level T-type structure. The model is extended to the three-phase inverter. The generalized inverse is used to generate the solution set of the conduction rates. Among the modulation strategies possible, three specific modulation schemes are proposed. The modulation schemes are applied to simulate a PWM three-phase inverter. Finally, some experimental results complete the analysis. [ABSTRACT FROM AUTHOR]

In order to prevent the power switching devices (e.g., an insulated-gate bipolar transistor, IGBT) from shoot-through in voltage-source converters during a switching period, the dead time is added either in the hardware driver circuits of the IGBTs or implemented in software in pulse width modulation (PWM) schemes. Both solutions will contribute to a degradation of the injected current quality. As a consequence, the harmonics induced by the dead time (referred to as “dead-time harmonics” hereafter) have to be compensated in order to achieve a satisfactory current quality, as required by standards. In this paper, the emission mechanism of dead-time harmonics in single-phase PWM inverters is, thus, presented considering the modulation schemes in detail. More importantly, a repetitive controller has been adopted to eliminate the dead-time effect in single-phase grid-connected PWM converters. The repetitive controller has been plugged into a proportional-resonant-based fundamental-frequency current controller so as to mitigate the dead-time harmonics and also to maintain the control of the fundamental-frequency grid current in terms of dynamics. Simulations and experiments are provided, which confirm that the repetitive controller can effectively compensate the dead-time harmonics and other low-order distortions, and also, it is a simple method without hardware modifications. [ABSTRACT FROM AUTHOR]

This paper proposes a zero-sequence circulating current (ZSCC) control scheme for the multiparalleled three-level T-type inverters (3LT2Is). Based on the analysis with the proposed generalized model of multiparalleled 3LT2Is, it is seen that the ZSCC is influenced by the circuit parameters, duty cycles, and the circulating currents of the l th and first 3LT2I. To mitigate the circulating currents, a deadbeat control strategy for n-paralleled (n≥3) inverters is proposed, which is realized by adjusting the duty cycle of the small vectors in each PWM sampling period. Compared with the conventional PI control method, the ZSCC spike is mitigated with the proposed scheme, thus improving the quality of the output currents. Also, the reliability of the 3LT2Is system is improved because such a scheme only needs the information about the ZSCC and zero-sequence duty ratio in the l th and the first inverter. The proposed method can also be applied to the neutral-point-clamped converters. Simulation and experimental results verify the effectiveness of the theoretical analysis and the proposed method. [ABSTRACT FROM PUBLISHER]

A conventional asymmetrical half-bridge (AHB) converter is widely used for dc–dc stage in low-to-medium power system. However, since the asymmetric operation of AHB converter causes the low efficiency over entire load condition, the conventional AHB converter is not usually considered for the candidate of server power system. In order to overcome the problems of the conventional AHB converter, a wide zero-voltage-switching (ZVS) range AHB converter with a clamp switch and a clamp diode is proposed in this paper. The proposed AHB converter (PAHBC) replaces a low-side clamp diode with a MOSFET switch and adds an auxiliary winding, which changes the transformer turns-ratio. From these modifications and the pulsewidth-modulation (PWM) control of clamp switch, the PAHBC can be designed optimally at nominal input condition and obtains additional dc gain at hold-up time condition. These advantages achieve the high conversion efficiency over the entire load condition. The operational principle and analysis of the PAHBC are presented in this paper and verified by a 340–400 V input and 50 V/500 W output laboratory prototype. [ABSTRACT FROM PUBLISHER]

Conventional zero-voltage and zero-current-switching (ZVZCS) full-bridge converters are widely used because they can realize zero-voltage switching (ZVS) for the leading leg and zero-current switching (ZCS) for the lagging leg. However, the large turn-off loss of the leading leg is still unacceptable in high-voltage high-power applications where insulated-gate bipolar transistors (IGBTs) with current tailing are employed. Hence, it is preferable to achieve ZCS for all IGBTs of full-bridge converters. This paper analyzes the ZCS conditions for pulsewidth modulated (PWM) full-bridge converters and proposes a general strategy for achieving ZCS for main switches, including the control strategy and design method of the topology. Based on this theory, a novel ZCS PWM full-bridge converter with simple auxiliary circuit is derived and tested. It can achieve ZCS not only for the main switches of full-bridge converter, but for the auxiliary switch as well, and obtain high efficiency. The operation principle of the proposed ZCS PWM full-bridge converter and the design procedure are presented. The experimental results of a 600 V/2.5 kW prototype are also included to verify the theoretical analysis. [ABSTRACT FROM PUBLISHER]

As for ripple-current mode control, it cannot achieve average current tracking, resulting in poor current accuracy and even current waveform distortion. Meanwhile, fast-scale instability may occur in some operating conditions. To solve these problems effectively, a current-ripple compensation (CRC) control technique is proposed in this paper. The error between the average of the controlled current and the reference current is compensated by certain compensation signal, achieving average current tracking while suppressing fast-scale instability. On this basis, the compensator in the outer-voltage loop is further simplified to a proportional part by introducing a rebuilt average reference current. The idea and design procedure of the proposed CRC control technique are discussed in detail. Accordingly, two available implementation schemes for the proposed CRC are presented, including slope compensated and parabolic compensated schemes. Finally, two application cases, respectively, to dc–dc Buck converter and Boost PFC converter, are presented to verify the proposed CRC control technique. [ABSTRACT FROM PUBLISHER]

To prevent partial-shading issues in photovoltaic (PV) systems, various kinds of voltage equalizers that virtually unify characteristics of shaded and unshaded modules have been proposed. Although PV string utilization can be dramatically improved, PV systems tend to be complex and costly because, in addition to the main converter for string control, voltage equalizers are separately necessary. This paper proposes the single-switch single-magnetic pulse width modulation (PWM) converter integrating the voltage equalizer using the series-resonant voltage multiplier (SRVM) for standalone PV systems. By utilizing a square wave voltage generated across a filter inductor in a PWM buck converter for driving the SRVM, the main PWM converter and voltage equalizer can be integrated into a single unit with reducing the total switch and magnetic component counts, achieving not only system-level but also circuit-level simplifications. The experimental test using the prototype for three PV modules connected in series was performed emulating a partial-shading condition. The integrated converter effectively precluded the partial-shading issues and significantly improved the power available at a load, demonstrating its efficacy. [ABSTRACT FROM AUTHOR]

The impedance-source network converter, utilizing a unique LC network and previously forbidden shoot-through states, provides the ability to buck and boost the input voltage in a single stage. However, the inrush shoot-through current (STC) in startup or transient process might cause undesired current stresses on converter devices. This paper focuses on the STC sensing for an effective inrush current limitation by the combined current sensing technique in the quasi-Z-source inverter. STC and phase currents for the inverter control strategy are obtained simultaneously. No extra hardware is needed and the effects of current sensor bandwidth and duty cycle on the sensing accuracy are analyzed mathematically. The voltage spike gets avoided by integrating the stray inductance into the impedance network. Finally, an STC control loop based on proposed method are embedded in the field-oriented control strategy. The inrush STC and the device current stress in the transient process get suppressed. Simulation and experimental results from a quasi-Z-source inverter validate the feasibility of the proposed methods. [ABSTRACT FROM PUBLISHER]

This paper presents a model predictive switching pattern control (MPSPC) for a current-source converter (CSC), which achieves superb low-order harmonics elimination performance in steady state and improved transient responses. Based on a proposed space-vector-based selective harmonic elimination (SHE) method and prediction of load current at the next sampling instant, MPSPC prefers to following a precalculated SHE-pulse width modulation (PWM) pattern in steady state, and governing the CSC through a model predictive control (MPC) approach during transients. In comparison with existing schemes, the advantages of MPSPC are threefold: First, quantization error, introduced by a constant sampling frequency in MPC and degrading steady-state low-order harmonic elimination, is mitigated in the proposed scheme. Second, there is no weighting factor in the cost function, as used in existing schemes. Finally, MPSPC is totally realized based on one-step prediction, which simplifies the structure of the scheme. Both simulation and experimental results verify the steady state and dynamic performance of MPSPC with different SHE-PWM patterns. [ABSTRACT FROM AUTHOR]

The Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. The unique feature of the ZSI is that it can operate either in buck or boost mode with a wide range of obtainable output voltages from a given input voltage. This topology also exhibits better electromagnetic-interference noise immunity when compared to a traditional voltage-source inverter (VSI). However, the LC impedance network of ZSI significantly increases the size and cost of the power converter and can make it unsuitable for low-power applications. This paper proposes a novel topology called switched boost inverter (SBI) which exhibits similar advantages of ZSI with lower number of passive components and more active components compared to ZSI. The steady-state and small-signal analyses of SBI, along with its pulsewidth modulation (PWM) control strategies, have been discussed in this paper. This paper also presents a comparison of SBI and ZSI with the same input and output parameters. The theoretical analysis given in this paper has been validated using a laboratory prototype of SBI, and the experimental results are presented for verification. The experimental harmonic spectrum of the inverter's output voltage with the proposed PWM technique is also plotted and compared with that of a traditional VSI. All the experimental results show good correlation between theory and experiments. [ABSTRACT FROM PUBLISHER]

In recent years, high photovoltaic array voltage up to 1000 V and transformerless grid-tied inverter have been increasingly researched and applied to elevate the inverter and the dc power collection efficiency. With the same reasons, a three-level neutral point clamped (3L-NPC) inverter featuring low power device voltage stress and low leakage current becomes increasingly attractive. In this paper, the operation and the features of a novel grid-tied 3L-NPC are presented. The proposed topology is a derivative of the three-level stacked neutral point clamped (3L-SNPC) structure. However, compared with the conventional 3L-SNPC and its pulse width modulation (PWM) strategy, the new topology with novel PWM strategy features completely inactive intrinsic body diodes. Furthermore, only two outer power devices are working with switching frequency, while the other four Insulated Gate Bipolar Transistors (IGBTs) are actually with the grid frequency. Therefore, the relatively high switching frequency is selected to reduce the inverter output filter inductance. A hybrid CoolMosfet and IGBT power module configuration is also proposed based on the new PWM strategy. The calculation shows that the total power device losses are reduced. The experimental results are illustrated in this paper to confirm the operation of the proposed topology and controller. [ABSTRACT FROM PUBLISHER]

In order to meet the high performance and efficiency requirements, a new space vector-based discontinuous modulation strategy for neutral-point clamped three-level inverter is presented in this paper. Different from the conventional discontinuous PWM (DPWM) strategies, a new clamping state is applied to synthesize the reference voltage under the condition of low modulation index. The rms value of output current ripple for different clamping states are calculated, and then the distribution of the new clamping state and the other two clamping states adopted in conventional DPWMs is optimized based on the calculation results. The switching sequences are redesigned according to the new distribution of the three clamping states. The output voltage and current, switching loss, neutral-point voltage ripple and the common mode voltage of the proposed DPWM strategy and DPWM0–DPWM3 are compared by simulation and experimental results. The results show that by the use of the proposed strategy, the values of total demand distortion of output current (ITDD) and weighted total harmonic distortion of output voltage (\boldsymbolV{\mathbf{WTHD}}) are the lowest. Furthermore, the product of switching loss and ITDD of the proposed strategy maintains the lowest within a large range of modulation index-load angle plane. It can be concluded that the utilization of the new clamping state and optimal distribution of different clamping states could enhance the output performance of the inverter. Moreover, the high-efficiency requirement can also be realized at the same time. [ABSTRACT FROM AUTHOR]

Several pulsewidth modulation (PWM) strategies have been proposed for three-phase multilevel converters. Typically, these PWM methods can be either space-vector or carrier-based implemented, where the carrier-based implementation usually presents a lower computation complexity. In this paper, a novel approach for the carrier-based implementation of different existing PWM methods is proposed for three- (3L) and four-level (4L) dc–ac converters, which can be easily extended to any number of levels. The main features of the proposed approach are its reduced computation complexity and computation time. On the other hand, the proposed approach suggests the derivation of novel PWM strategies which can potentially present improved performance features. As an example, two new discontinuous PWM (DPWM) strategies are proposed for the 4L converter. One of these DPWM strategies presents lower weighted total harmonic distortion than other previously proposed strategies. Simulation and experimental results verify the effectiveness of the proposed approach and novel DPWM strategies. [ABSTRACT FROM AUTHOR]

This paper presents a review of the most popular control and modulation strategies studied for matrix converters (MCs) in the last decade. The purpose of most of these methods is to generate sinusoidal current on the input and output sides. These methods are compared considering theoretical complexity and performance. This paper concludes that the control strategy has a significant impact on the resonance of the MC input filter. [ABSTRACT FROM AUTHOR]

This paper proposes a new space-vector pulsewidth modulation (SV-PWM) strategy for a three-level neutral point clamped inverter. The presented SV-PWM strategy makes it possible to control the neutral point voltage by optimum choice of switch sequence for any position and length of output voltage vector. The proposed solution takes into consideration the unbalance of the dc-link voltages. It also analyzes the influence of vector sequences on the predicted unbalance of the dc-link voltage. The solution allows selecting optimum vectors and their on-time durations in order to reduce quickly the dc-link voltage unbalance. The calculation of the space vector area proposed in this paper takes into consideration voltage unbalance and its influence on the length and position of vectors. The proposed approach assures properly generating the voltage output vectors, even in the case of the existing large voltage unbalance in the dc-link. The results of the experimental investigation of the proposed modulation strategy are presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents a novel topology for a direct ac–ac power converter, called as the “three-to- k” phase matrix converter. The input to the proposed matrix converter configuration is a three-phase fixed voltage and a fixed frequency supply from the grid. The output is a variable voltage and variable frequency ac supply of any number of phases (k phase). However, the discussion is limited here for a k that is equal to odd number of phases. As an example, a “three-to-five” phase matrix converter is utilized for discussion and analysis. This paper also proposes two pulsewidth modulation (PWM) control techniques for the general topology of the “three-to- k” phase matrix converter. This is based on the so-called direct duty ratio PWM (DPWM). In one presented technique, the output voltage is limited to one half of the input voltage. For the other proposed scheme, the output voltage is enhanced to 78.86% of the input voltage. The proposed control algorithm is validated using simulation and an experimental approach. [ABSTRACT FROM AUTHOR]

This paper presents a single-phase power factor corrector based on a tapped-inductor buck–boost converter. This paper suggests simplified models of the power stage under current-mode control and derives small-signal transfer functions of both the current and voltage control loops. Design rules for implementation of the proposed power factor corrector (PFC) are also suggested. The proposed PFC features low dc bus voltage, arbitrary lower than the peak line voltage. The proposed PFC is suitable for applications in computers and communications, where dc isolation can be provided by the downstream dc/dc converters. Simulation and experimental results are also reported and stand in good agreement with theoretical expectations. [ABSTRACT FROM AUTHOR]

Most switched mode power supplies provide a regulated voltage at their output. However, there are applications requiring a controlled current. Among others are battery chargers, test equipment for converters driven by solar cells, and LED drivers. This paper describes a dc–dc power converter realizing such a current source. The converter is based on a boost converter, supplied by a voltage source and acting as a current source. The boost converter can increase the output voltage above the input voltage. The converter provides a high control bandwidth based on a self-oscillating current loop. As additional practical features, soft start and output overvoltage limitation are included and described in this paper. The modulator, the control, and the power stage are described in detail and verified by the experiment. [ABSTRACT FROM AUTHOR]

This paper presents a current soft-commutation pulsewidth modulation (PWM) scheme for three-phase current source converter. With the presented PWM scheme, the incoming switch has a positive collector-to-emitter voltage while the outgoing switch has a negative collector-to-emitter voltage during current commutations. Therefore, natural soft commutations for switching transitions are achieved, while current-commutating durations are also lessened. Moreover, some particular advantages can also be obtained such as reduced switching frequency, high dc current utilization ratio, and in-phase transfer between line currents and their references. For more efficient control, this paper then designs logic equations for mapping out the assignments from references to gating signals, allowing a simple implementation using a digital signal processor or a programmable logic device. The theoretical analysis is verified by experimental results. [ABSTRACT FROM AUTHOR]

This paper describes a modified phase-shifted carrier-based pulsewidth-modulation (PSC-PWM) scheme for modular multilevel converters (MMC). In order to reduce the average device switching frequency, a reduced switching-frequency (RSF) voltage balancing algorithm is developed. This paper also proposes a circulating current suppressing controller (CCSC) to minimize the inner circulating current in an MMC. Based on the double line-frequency, negative-sequence rotational frame, the three-phase alternative circulating currents are decomposed into two dc components and are minimized by a pair of proportional integral controllers. Simulation results based on a detailed PSCAD/EMTDC model prove the effectiveness of the modified PSC-PWM method and the RSF voltage-balancing algorithm. The proposed CCSC not only eliminates the inner circulating current but also improves the quality of the converter ac output voltage. A simple loss evaluation demonstrates that the RSF voltage-balancing algorithm and the CCSC reduce the converter power losses. [ABSTRACT FROM AUTHOR]

Synchronization effects and performance degradation of a distributed inverter built with several phase-leg power electronics building block (PEBB) modules controlled with a space-vector pulsewidth modulation (SVPWM) strategy are presented in this paper. Under the control of the distributed SVPWM strategy, the inverter PEBB modules generate their target output voltage vectors separately, operating simultaneously with the command of the synchronization signal sent by the master module or the upper level controller. When a synchronization error exists, the line-to-line output voltage will contain some noncharacteristic harmonic components. This paper systemically analyzes the impact of synchronization error on the system performance. Conclusions are derived from the double Fourier analysis, MATLAB simulation, and experimental results. [ABSTRACT FROM PUBLISHER]

Due to the higher attenuation of switching frequency current harmonics, the $LCL$ filter has been widely used in grid-connected inverters. To deal with the resonance of the $LCL$ filter, the capacitor current is usually fed back to damp the resonance actively. However, the computation and pulsewidth modulation (PWM) delays in the digital control system have a significant influence on the active damping method, resulting in poor system robustness. Meanwhile, these delays also reduce the control bandwidth greatly and thus impose a severe limitation on the low-frequency gains. In this paper, a real-time computation method with dual sampling mode is proposed to remove the computation delay from the inner active damping loop and the outer grid-current control loop simultaneously; thus, the system robustness and the control performance can be greatly improved. Moreover, the time duration between the sampling instant and the switching transition of the inverter bridge is extended by the proposed method, which effectively prevents the switching noise distorting the sampled signals. Therefore, the noise immunity of the inverter is also improved greatly. Experimental results from a 6-kW $LCL$-type single-phase grid-connected inverter confirm the theoretical expectations and the effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

This paper presents a capacitor voltage balancing control applicable to any multilevel dc–ac converter formed by a single set of series-connected capacitors implementing the dc link and semiconductor devices, such as the diode-clamped topology. The control is defined for any number of dc-link voltage levels and converter legs (for single-phase and multiphase systems), guaranteeing the capacitor voltage control for any modulation index value and load (from idle mode to full power). The associated control loop small-signal transfer function is presented, from which optimum compensator design guidelines are derived. The improvement in control performance is verified through simulation and experiments comparing with a previous balancing control strategy in a four-level three-phase dc–ac conversion system. The satisfactory control performance is also verified through simulation in a four-level five-phase dc–ac conversion system. [ABSTRACT FROM PUBLISHER]

Three-phase multilevel (ML) inverters are used in many medium- and high-power applications such as motor drives and grid-connected systems. Despite the fact that numerous pulsewidth modulation (PWM) techniques for ML inverters have been developed, the impact of these modulation schemes on the peak-to-peak output current ripple amplitude has not been addressed yet. In this paper, analysis and comparison of current ripple for two-level (2L) and three-level (3L) voltage source inverters are given. Reference is made to optimal and popular modulation, so-called centered PWM, easily obtained by both carrier-based modulation (phase disposition, with proper common-mode voltage injection) and space vector modulation (nearest three vectors). It is shown that the peak-to-peak current ripple amplitude in 3L inverters can be determined on the basis of the ripple in 2L inverters, obtaining the same results as by directly analyzing the output voltage waveforms of the 3L inverters. This procedure can be readily extended to higher level numbers. The proposed analytical developments are verified by both numerical simulations and experimental tests. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel modulation technique and a new balancing control strategy for a single-phase five-level flying-capacitor (FC)-based active-neutral-point-clamped (ANPC) converter. The proposed modulator can control the FC voltage to follow the requested reference value and simultaneously generate the required ac output voltage regardless of the values of the dc capacitor voltages of the converter. By implementing this method, smaller values of the dc-link capacitor and FC can be used even in applications that could experience ripple or transient in the capacitor voltage. In a single-phase five-level ANPC converter applications, where the capacitors can experience pulsation power and dc-link balancing issues, such as grid-connected photovoltaic system, the selection of the reference voltage value for the FC can play an important role to balance the average values of the dc-link capacitor voltage. The proposed new control strategy uses a new reference voltage for the FC to be applied by the new modulator to have an average balanced dc-link voltages as well as an ac output voltage with good power quality. Simulation studies and experimental results demonstrate the effectiveness of the proposed modulation technique and control strategy even with relatively small dc capacitors to produce high-quality output voltage and current waveforms while maintaining an average balanced dc-link voltages. [ABSTRACT FROM PUBLISHER]

This paper presents a dual-loop current regulation strategy for coupled-inductor multilevel converters. The basis of the strategy is to recognize that the current in the coupled inductor can be decoupled into independent dc bias and ac load currents, which can be then regulated using separate feedback processes. This allows the system to enforce continuous conduction operation of the inverter phase legs by dynamically varying the dc bias current to track the ac load current. Design principles are presented to account for the different common- and differential-mode load dynamics and to maximize the closed-loop bandwidths of both feedback loops. This ensures that the dc bias current can follow rapid load transient events. Matching simulation and experimental results obtained for a five-level flying-capacitor coupled-inductor inverter are presented to validate the proposed control strategy. [ABSTRACT FROM PUBLISHER]

The propagation delay of a comparator and dead time causes the duty-discontinuity region near the boundary of the step-down and step-up regions in a non-inverting buck–boost (NIBB) converter. The duty-discontinuity region leads to an unstable output voltage and an unpredictable output voltage ripple, which might cause the entire power system to shut down. In this paper, a mode-transition technique called duty-lock control is proposed for a digitally controlled NIBB converter. It locks the duty cycle and eliminates the error between the output voltage and the reference signal by using a proposed fixed reference scheme that ensures the stability of the digital controller and output voltage. The experimental results that were applied to a field-programmable gate array-based platform revealed that the output voltage of the NIBB converter is stable throughout the entire transition region, without any efficiency tradeoffs. The input voltage of the converter that was provided by a Li-ion battery was 2.7–4.2 V, and the output voltage was 1.0–3.6 V, which is suitable for radio-frequency power amplifiers. The switching frequency was 500 kHz, and the maximum load current was 450 mA. [ABSTRACT FROM PUBLISHER]

The term dead time refers to a prime safety factor for most power electronic converter topologies, and it is included either in the control software or in the gate/base driver hardware, depending on the application as well as the control requirements. In this paper, the authors present a comprehensive numerical analysis of dead-time effects on the output voltage of a three-level neutral-point-clamped (NPC) inverter. To incorporate the dead-time effect in the output voltage, 3-D models of three-level carrier pulse width modulation (PWM) methods are modified for two dead-time implementations. Closed-form expressions of inverter phase voltage harmonics for phase opposition disposition (POD) PWM are derived based on the double Fourier series approach and modified contour plots. The harmonic spectra from numerical evaluations, simulations, and experiments for natural sampling (NS), symmetrical regular sampling (SRS), and asymmetrical regular sampling (ARS) are compared to validate the mathematical models. In addition, the fundamental voltage with respect to the dead time and the load phase angle is presented based on analytical results and simulation. [ABSTRACT FROM PUBLISHER]

This paper presents a six-phase current reconstruction scheme for dual traction inverters in hybrid electric vehicles (HEVs) with a single dc-link current sensor. During the phase current reconstruction, one of the inverters is proposed to operate using active vectors, whereas the other inverter operates using nonactive vectors. An advanced phase-shift scheme for all pulsewidth-modulated (PWM) signals based on the sequence of duty cycles is implemented. PWM signals are considered in three types: large, medium, and small duty cycles. Then, the minimum phase-shift scheme is applied to each type of PWM signal to ensure the minimum duration of the active vector for stable current reconstruction. With this proposed phase-shift scheme, the maximum allowable modulation index and dc-link voltage utilization are improved. In addition, the relationship between the minimum required time for stable phase current reconstruction and the maximum allowable modulation index is derived theoretically. The effectiveness of the proposed method is verified by both simulation and experimental results. With this scheme, cost and volume of dual inverters in HEVs are reduced, considering the lower number of current sensors. [ABSTRACT FROM PUBLISHER]

Multilevel flying capacitor (FC) converters provide natural capacitor voltage balance under phase-shifted pulse width modulation (PS-PWM). However, natural balancing may not be robust enough to maintain the voltages at the reference values, especially under certain transient conditions. Furthermore, natural balancing dynamics depend on the load and it may be very slow in some practical applications. Therefore, a more robust balancing mechanism of maintaining the FC voltages at the desired values is required. This paper proposes a new closed-loop voltage-balancing method for the multilevel FC converters using PS-PWM. The proposed method balances the voltages of the FCs by modifying the duty cycle of each switch of the FC converter using a proportional controller. The crossed effect between FC currents and duty cycles is considered and is used for optimal FC voltage balancing. Simulation and experimental results verify that the proposed voltage-balancing method is very robust to different operating conditions, such as load transients, linear/nonlinear and unbalanced loads. [ABSTRACT FROM AUTHOR]

Compared with the widely used constant switching frequency pulse-width-modulation (PWM) method, variable switching frequency PWM can benefit more because of the extra freedom. Based on the analytical expression of current ripple of three-phase converters, variable switching frequency control methods are proposed to satisfy different ripple requirements. Switching cycle Ts is updated in DSP in every interruption period based on the ripple requirement. Two methods are discussed in this paper. The first method is designed to arrange the current ripple peak value within a certain value and can reduce the equivalent switching frequency and electromagnetic interference (EMI) noise; the second method is designed to keep ripple current RMS value constant and reduce the EMI noise. Simulation and experimental results show that variable switching frequency control could improve the performance of EMI and efficiency without impairing the power quality. [ABSTRACT FROM AUTHOR]

This paper presents a zero-voltage-switching (ZVS) full-bridge dc–dc converter combing resonant and pulse-width-modulation (PWM) power conversions for electric vehicle battery chargers. In the proposed converter, a half-bridge LLC resonant circuit shares the lagging leg with a phase-shift full-bridge (PSFB) dc–dc circuit to guarantee ZVS of the lagging-leg switches from zero to full load. A secondary-side hybrid-switching circuit, which is formed by the leakage inductance, output inductor of the PSFB dc–dc circuit, a small additional resonant capacitor, and two additional diodes, is integrated at the secondary side of the PSFB dc–dc circuit. With the clamp path of a hybrid-switching circuit, the voltage overshoots that arise during the turn off of the rectifier diodes are eliminated and the voltage of bridge rectifier is clamped to the minimal achievable value, which is equal to secondary-reflected input voltage of the transformer. The sum of the output voltage of LLC resonant circuit and the resonant capacitor voltage of the hybrid-switching circuit is applied between the bridge rectifier and the output inductor of the PSFB dc–dc circuit during the freewheeling phases. As a result, the primary-side circulating current of the PSFB dc–dc circuit is instantly reset to zero, achieving minimized circulating losses. The effectiveness of the proposed converter was experimentally verified using a 4-kW prototype circuit. The experimental results show 98.6% peak efficiency and high efficiency over wide load and output voltage ranges. [ABSTRACT FROM AUTHOR]

This paper proposes a new zero-voltage switching (ZVS) pulse width modulation (PWM) three-level (TL) full-bridge (FB) dc–dc converter, which is composed of a TL FB converter and a TL half-bridge (HB) converter. It is well suited for high input voltage and high-power applications. The proposed topology has the following attractive features: off-state voltage on all switches in the circuit is only half of the input voltage; full input voltage is utilized on the load for the whole operating range; TL output waveform is achieved, which significantly reduces the requirements for the input and output filters; simple switching scheme can be used to control the output voltage in wide range. The converter can achieve ZVS for all power switches in wide load range and even at light load condition; furthermore, less conduction loss is added to achieve soft switching. The operation and important analysis of the proposed converter are given. Experiments are carried out to validate the proposed converter, and efficiency curves are tested and given. [ABSTRACT FROM AUTHOR]

Cascaded H-bridge multilevel power electronic converters generally require several dc sources. An alternative option is to replace all the separate dc sources feeding the H-bridge cells with capacitors, leaving only one H-bridge cell with a real dc voltage source. This will yield a cost-effective converter. However, the required capacitor voltage balancing is challenging. In this paper, using the phase-shift modulation approach, a new control method for cascaded H-bridge multilevel converters fed with only one independent dc source is presented. The proposed method has a wide voltage regulation range for the replacement capacitors in the H-bridge cells. Experimental and simulation results support the proposed control method. [ABSTRACT FROM PUBLISHER]

This paper presents a new Venturini-based direct matrix converter (DMC) output phase current reconstruction method using a single current sensor. This method is proposed in order to reduce the cost and to improve the reliability of the drive with any control strategy. The proposed technique measures the phase currents using a new single Hall current sensor location in the DMC. To demonstrate the advantages of the proposed system, an experimental bench with a DMC, an induction motor, and a DSP board is carried out to confirm the validity and feasibility of the proposed current reconstruction approach. [ABSTRACT FROM PUBLISHER]

Single-phase three-level neutral point clamped (NPC) converters are widely applied in high-speed railway electrical traction drive systems. A significant problem related to the single-phase three-level NPC converters is the fluctuation of the neutral-point voltage. In this paper, a capacitor voltage balancing technique is proposed that injects an offset voltage into the sinusoidal modulating signals of the conventional carrier-based pulsewidth modulation (CBPWM) method. Furthermore, when the injected offset voltage is maximized, it cannot only balance the dc-link capacitors voltages, but also reduce switching losses. Theoretical analysis has shown that both methods can control the neutral point voltage effectively, but the neutral point voltage controller in the CBPWM with maximum offset voltage injection (CBPWM-MOVI) has a faster dynamic response. It was observed that the high-order harmonics frequencies of the line current are centered around the twice switching frequency in the CBPWM with the offset voltage injection (CBPWM-OVI) but are centered around the switching frequency in the CBPWM-MOVI. And also, the CBPWM-MOVI has switching commutations number at least 25% below that of the CBPWM-OVI in one modulating signal period. The performances of the two strategies were verified by simulation and experimental tests. [ABSTRACT FROM AUTHOR]

This paper presents the ac small-signal modeling of the power stage of pulsewidth-modulated Z-source converter in continuous conduction mode by the circuit-averaging technique. The small-signal models used to derive the open-loop power-stage input voltage-to-capacitor voltage, input voltage-to-inductor current, control-to-capacitor voltage, and control-to-inductor current transfer functions are derived. Open-loop power-stage transfer functions corresponding to the capacitor voltage loop and inductor current loop are derived. The transfer functions derived take into account the equivalent series resistances of the inductors and capacitors. Experimental validation of the derived small-signal models is presented for a laboratory prototype. The theoretical predictions are in good agreement with the experimental results. [ABSTRACT FROM AUTHOR]