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The neutral-point voltage-balancing control is a critical issue of a neutral-point-clamped converter. The conventional control strategy is to inject the specific zero-sequence voltage to regulate the redundant vector, but it is unacceptable to the three-phase four-wire system. This paper provides a neutral-point voltage-balancing control by the dipolar modulation, and the control freedom of the zero-sequence voltage is flexible. Therefore, the proposed method is suitable for both three-phase three-wire and three-phase four-wire systems. Besides, the proposed method improves the control dynamic in a reactive power system. The proposed neutral-point voltage-balancing control is verified by the mathematical analysis and experimental results. The control dynamic, power loss estimation, and the output current performance are analyzed in this paper. [ABSTRACT FROM PUBLISHER]

A gate driving for power devices is a key technology to further improve switching characteristics. With the help of digital gate driver IC, the switching behavior of power devices can be enhanced even under high-speed switching. In this paper, an evaluation platform for determining the optimal switching pattern of an active gate drive control is proposed for an inverter circuit. A high speed optimization system is built up to search for an advantageous switching pattern that reduces total switching loss of two power devices in an inverter circuit and constrains surge voltage simultaneously. The proposed online optimization demonstrates its feasibility for the full-bridge inverter circuit, which is rated at 500 V with digital active gate drive control. Experimental results show that the proposed optimization system is able to obtain optimal switching pattern from $64^{60}$ possible combinations of switching patterns within 15 min, which is 6 times faster than the previous study. Optimizations can also conducted under different load current conditions. Eventually, the obtained optimal pattern yields up to 42% reduction in the total switching loss when it constrains surge voltage to minimum compared with the conventional driving pattern. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) features many optimal properties for future memory applications that make RRAM a strong candidate for storage-class memory and embedded nonvolatile memory. This paper addresses the cycling-induced degradation of RRAM devices based on a HfO2 switching layer. We show that the cycling degradation results in the decrease of several RRAM parameters, such as the resistance of the low-resistance state, the set voltage V\mathrm{ set} , the reset voltage V\mathrm{ reset} , and others. The degradation with cycling is further attributed to enhanced ion mobility due to defect generation within the active filament area in the RRAM device. A distributed-energy model is developed to simulate the degradation kinetics and support our physical interpretation. This paper provides an efficient methodology to predict device degradation after any arbitrary number of cycles and allows for wear leveling in memory array. [ABSTRACT FROM AUTHOR]

Magnetically coupled impedance-source (MCIS) networks are recently introduced impedance networks intended for various high-boost applications. It employs coupled magnetic in the circuit to achieve higher voltage gain. Various MCIS networks have been proposed in the literature for myriad applications; however, due to effective role of system modeling in the closed-loop controller design, this paper is allocated to small-signal modeling and analysis of MCIS converters. The modeling is performed by means of the circuit averaging and averaged switch technique. A generalized small-signal derivation is demonstrated for pulse width modulation (PWM) MCIS converters and it is shown that the derived transfer functions can simply be applied to Y-source, Γ-source, and T-source impedance networks. Various transfer functions for capacitor voltage, output voltage, magnetizing current, input and output impedance are derived and have been validated through frequency and dynamic responses of computer simulation results. In addition, a comprehensive analysis has been done for all mentioned PWM MCIS converters regarding their circuit parameters. Furthermore, the effect of considering the equivalent series resistances of capacitor and inductor on the stability margin of MCIS converters is revealed in this paper. Finally, in order to validate the derived transfer functions and to consolidate the perfumed analysis, experimental results are presented for all mentioned MCIS converters. [ABSTRACT FROM PUBLISHER]

Many research works have been conducted on increasing the efficiency of interleaved boost converters (IBCs) applied for power factor correction (PFC) by using high-performance power electronic devices and soft switching circuits, which are not helpful in reducing the hardware cost and systematic complexity. In this paper, three intrinsic parameters affecting the efficiency of IBC PFC are found and analyzed, including the switching frequency value, boost inductor value, and output voltage value. Based on the findings, considering the limitations of current ripples, power factor, maximum magnetic flux density, and volume of a boost inductor, an optimization design method for high-efficiency IBC PFC is proposed. A 3.3-kW IBC PFC prototype is developed based on Si devices. The experimental result verifies that the proposed method can improve the efficiency of IBC PFC with low-cost low-performance devices in the full-load range. [ABSTRACT FROM AUTHOR]

The multigap gas switch has been widely used in liner transformer drivers (LTDs), but there is still room for improvement on its self-breakdown and triggering characteristics. In this paper, based on the circuit model of the six-gap gas switch, the gap voltage distribution during the charging and triggering process is analyzed, and the optimization on self-breakdown and triggering characteristics by mounting resistors and capacitors in parallel with switch gaps are theoretically and experimentally investigated. The results indicate that compared with the original switch, when the self-breakdown voltage is about ±90 kV, the standard deviation is reduced from 7.5 to less than 3 kV; for a charging voltage of ±80 kV and by operating at 60% working coefficient, when the negative trigger voltage is 75 kV, the jitter of the switch is reduced from 6.1 to 1.4 ns. [ABSTRACT FROM AUTHOR]

A simple buck–boost LED driver suitable for battery operated applications with limited input voltage level is presented in this paper. Soft switching performance is provided for the main switch via a resonant circuit to improve the converter efficiency. The incorporated auxiliary switch also performs under zero voltage switching condition. Both power switches can be driven with a simple gate drive circuit, so, the additional switch does not add any driving complexity. In addition, only one magnetic element is utilized in the proposed LED driver which contributes to circuit simplicity and lower weight and size. Also, all diodes turn off at zero current switching which eliminates the reverse recovery losses and improves efficiency. A laboratory prototype converting 12 V input voltage to 32 V output operating at 26 W output power is implemented and tested to verify the effectiveness of the proposed LED driver. [ABSTRACT FROM AUTHOR]

A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM), a new emerging nonvolatile memory technology based on changes in electrical resistivity of a dielectric film, offers promising advantages such as scalability, fast switching, and low operation voltage. However, for ReRAM to become a successful technology, it is necessary to accurately control the stochastic nature of the conductive nanoscale filaments (CNFs) that governs the resistive switching (RS) behavior of the device and limits its long-term stability and reliability. In this paper, we developed a highly scalable nanostructured/textured electrode that is composed of an array of Al nanotips based on an anodic aluminum oxide template. The nanotips improve the RS characteristics by intensifying the electric field at the apex of each nanotip which is demonstrated using numerical simulations. The localized electric field induces the repetitive nucleation/ formation/rupture of the CNFs in a more controlled fashion compared to a flat Al electrode. As a result, the nanotip sample exhibits uniform and reduced forming/reset voltages as low as 4.70 ± 0.98V/1.00 ± 0.19 V, stable endurance, and long-term retention. As a result, we were able to achieve ultralow-power and error-free operation of 100 cells covering a large area, significantly demonstrating improved uniformity and reliability compared to devices made using flat Al electrodes. This universal bottom-up strategy of self-organized nanostructured-electrodes provides a pathway toward large-scale, highly reliable, and RS memory devices. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) is known as a major cause of premature motor failures. The form and amplitude of the CMV generated by any converter depends on both the circuit topology and modulation technique. Among single stage ac–ac converters employed in drive applications, the Z-source ultra sparse matrix converter (ZSUSMC) is a desirable choice due to reduced number of switches in its structure and voltage boosting capability. Based on these considerations, this paper aims to: 1) theoretically determine and compare the CMV of the ZSUSMC with four well-known impedance networks, namely, cascaded, switched-inductor, quasi, and series, in its structure and 2) propose modulation techniques for CMV reduction in the ZSUSMCs. To this end, first, it is shown that the ZSUSMC, depending on the impedance network used in its structure, provides more freedom to choose from redundant switching states compared to the ultra sparse matrix converter. Then, by taking advantage of this feature, novel modulation strategies that attenuate the CMV without affecting the boosting capability are developed. The proposed modulation schemes are based on avoiding the switching states most contributing to the CMV during a switching period. Through hardware-in-the-loop studies, the effectiveness of the proposed modulation strategies in reducing the CMV of the ZSUSMCs is verified. [ABSTRACT FROM AUTHOR]

Although high-frequency circulating current exists in parallel-operated inverters, it has not attracted as much attention as low-frequency circulating current, and thus has not been analyzed in detail previously. In this paper, a mathematical model and analysis are presented, which reveal the spectrum components and their changing trends of the circulating currents caused by carrier phase differences. The impact of carrier phase difference on high-frequency circulating current is also analyzed and verified. A closed-loop control scheme is proposed to suppress the switching frequency circulating current caused by carrier phase difference. In addition, the deadbeat and closed-loop control are combined to suppress the low- and high-frequency circulating currents simultaneously, to improve the overall performance of circulating current suppression. The effectiveness of the proposed scheme is verified by the simulation and experimental results acquired from a laboratory platform. [ABSTRACT FROM AUTHOR]

The neutral-point potential fluctuation in single-phase three-level rectifiers leads to coupling between the line current regulation and dc-link capacitor voltage balancing, deteriorating waveform quality of the line current. For addressing this issue, this paper proposes a low-complexity model predictive current control (MPCC) with constant switching frequency, which achieves a decoupling control of the line current and the neutral-point potential under the unbalanced load condition. The switching frequency is fixed by combining the MPCC scheme with predefined switching sequences. The boundary of the durations for voltage vectors in switching sequences is presented to balance the capacitor voltage without worsening the line current quality. The optimal switching sequence and the corresponding optimal durations of voltage vectors in the switching sequence are readily derived without the assessment of the cost function, which dramatically simplifies the complexity of the MPCC scheme. Finally, simulations and experimental results are conducted to verify the effectiveness of the proposed MPCC scheme. [ABSTRACT FROM AUTHOR]

Flyback/forward derived power converters offer operational simplicity, but require active clamping circuits to reduce switch voltage stress and improve the converter efficiency. This paper presents an active clamping circuit technique, which additionally ensures enhancement in the converter voltage gain. This is enabled by the proposed auxiliary circuit, which introduces a charged capacitor in series with the primary source during the energizing interval. Two circuits are designed on this principle, and design and operation of both are presented for discontinuous conduction modes. It is shown that the voltage gain of these circuits increases with increase in the leakage inductance, which is an improvement over existing converters. Also, in one circuit primary (secondary) winding, rms current is similar to (lower than) that in a typical ideal flyback converter, leading to improvement in power density. Operation and analyses of this variant are experimentally verified with a 400-V laboratory prototype. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate the linear conductance-change characteristics of a conductive-bridging RAM (CBRAM) to be employed as an artificial synapse device in neuromorphic systems. The CBRAM with a bilayer electrolyte structure (${\mathrm {Cu/Cu}}_{{2}-{x}}\text{S}$ / $\mathrm {WO}_{{3}-{x}}$ /W) exhibits analog switching behavior during the depression process due to the well-controlled dissolution of the conductive filament. To analyze the origin of this motion, we investigate the effective voltage applied to $\mathrm {Cu}_{{2}-{x}}\text{S}$ and $\mathrm {WO}_{{3}-{x}}$. Our findings reveal that $\mathrm {Cu}_{{2}-{x}}\text{S}$ , acting as a voltage divider, helps in suppressing the large voltage drop in $\mathrm {WO}_{{3}-{x}}$ , where the formation/dissolution of filament occurs. Furthermore, due to the diode-like characteristics of $\mathrm {Cu}_{{2}-{x}}\text{S}$ and the division of voltage drop between $\mathrm {WO}_{{3}-{x}}$ and $\mathrm {Cu}_{{2}-{x}}\text{S}$ , an optimum programming energy is applied to $\mathrm {WO}_{{3}-{x}}$ during the depression process. This leads to linear conductance-change characteristics under identical pulses. However, abrupt conductance-change characteristics are observed during the potentiation process. Thus, we use only the device characteristics of the depression part for the neuromorphic system. An excellent classification accuracy is achieved due to the linear conductance-change characteristics and optimized pulse conditions. [ABSTRACT FROM AUTHOR]

In this paper, a novel platform for the single phase switched-capacitor multilevel inverters (SCMLIs) is presented. It has several advantages over the classical topologies, such as an appropriate boosting property, higher efficiency, lower number of required dc voltage sources, and other accompanying components with less complexity and lower cost. The basic structure of the proposed converter is capable of making nine-level of the output voltage under different kinds of loading conditions. Hereby, by using the same two capacitors paralleled to a single dc source, a switched-capacitor (SC) cell is made that contributes to boosting the value of the input voltage. In this case, the balanced voltage of the capacitors can be precisely provided on the basis of the series–parallel technique and the redundant switching states. Afterward, to reach the higher number of output voltage levels, two suggested SC cells are connected to each other with a new extended configuration. Therefore, by the use of a reasonable number of required power electronic devices, and also by utilizing only two isolated dc voltage sources, which their magnitudes can be designed based on either symmetric or asymmetric types, a 17- and 49-level of the output voltage are obtained. Based on the proposed extended configuration, a new generalized version of SCMLIs is also derived. To confirm the precise performance of the proposed topologies, apart from the theoretical analysis and a complete comparison, several simulation and experimental results are also given. [ABSTRACT FROM AUTHOR]

A comprehensive study on the dielectric modulated (DM) drift region for power devices is presented in this paper. The performance of this drift region structure is theoretically analyzed and compared with other two structures: conventional and superjunction. In this paper, a study is focused on switching performance. The C – V relationships during switching are analytically derived, and the depletion widths predicted by the proposed analytical model agree well with simulation in a wide reverse bias region. The switching energy loss is evaluated based on the analytical model and its accuracy is verified by 2-D simulations. An effective depletion charge QD is defined as E\mathrm {loss} / breakdown voltage (BV), from which a figure of merit (FOM) of R\mathrm{\scriptscriptstyle ON,\mathrm {sp}}{}^\ast QD is proposed to compare the performances of these different drift region structures, considering both the conduction and switching losses. The discussions in part I on Si and silicon carbide device structures are extended in part II to include FOMs. It is found that the DM drift region structures show better R\mathrm{\scriptscriptstyle ON,\mathrm {sp}} -BV tradeoffs compared with the conventional structures, but slighter inferior FOMs. However, DM structures are still attractive for applications, where switching loss is less critical than the conduction loss, such as low frequency or soft switching. [ABSTRACT FROM PUBLISHER]

This paper presents a merged-two-stage circuit topology suitable for either wide-range dc input voltage or ac line voltage at low-to-moderate power levels (e.g., up to 30 W). This two-stage topology is based on a soft-charged switched-capacitor preregulator/transformation stage and a high-frequency magnetic regulator stage. Soft charging of the switched capacitor circuit, zero voltage switching of the high-frequency regulator circuit, and time-based indirect current control are used to maintain high efficiency, high power density, and high power factor. The proposed architecture is applied to an LED driver circuit, and two implementations are demonstrated: a wide input voltage range dc-dc converter and a line interfaced ac-dc converter. The dc-dc converter shows 88%-96% efficiency at 30-W power across 25-200-V input voltage range, and the ac-dc converter achieves 88% efficiency with 0.93 power factor at 8.4-W average power. Contributions of this paper include: 1) demonstrating the value of a merged two-stage architecture to provide substantial design benefits in high-input voltage, low-power step down conversion applications, including both wide-range-input dc-dc and line-input ac-dc systems; 2) introduction of a multimode soft-charged SC stage for the merged architecture that enables compression of an 8:1 input voltage range into a 2:1 intermediate range, along with its implementation, loss considerations, and driving methods; and 3) merging of this topology with an resonant transition discontinuous-mode inverted buck stage and pseudocurrent control to enable step-down power conversion (e.g., for LED lighting) operating at greatly increased frequencies and reduced magnetics size than with more conventional approaches. [ABSTRACT FROM AUTHOR]

This paper presents a generalized multilevel direct power control (ML-DPC) scheme for grid-connected multilevel power converters. The proposed method extends the original DPC operating principle by considering only the closest subset of two-level voltage vectors to the present switching state. The implementation of this principle requires the power derivatives for feedback, which can present numerical problems when applied experimentally, mainly due to high measurement noise sensitivity. Therefore, a derivative estimator is proposed based on the converter-grid model in the synchronous reference frame. In addition, a virtual flux observer is developed to achieve synchronization and improve robustness in the presence of grid voltage harmonics. The proposed method is applicable to any multilevel converter topology of any number of levels. In this paper, simulations and experimental results are presented for a seven-level cascaded H-bridge converter. [ABSTRACT FROM AUTHOR]

This paper presents a fast and generalized space vector pulse width modulation (SVPWM) scheme for any multilevel inverter. The SVPWM scheme generates all the available switching states and switching sequences based on two simple and general mappings, and calculates the duty cycles simply as if for a two-level SVPWM, thus independent of the level number of the inverter. Because the switching states, duty cycles, and switching sequences are all obtained by simple calculation in the proposed SVPWM scheme, no lookup table is needed and the scheme is computationally fast. The generalized method of generating the switching states (first mapping), calculating the duty cycles, and determining the switching sequence (second mapping) is described in this paper. The scheme is suitable for any reference vector with any modulation index, and can be conveniently extended to meet specific requirements, such as symmetric switching sequences. Compared with prior methods, the SVPWM scheme proposed in this paper provides two more degrees of freedom, i.e., the adjustable switching sequences and duty cycles, thus offering significant flexibility for optimizing the performance of multilevel inverters. The influence of redundant switching sequences in the output phase voltage of inverters is demonstrated for a nine-level inverter. This paper also thoroughly compares the proposed SVPWM scheme with prior methods. Both simulation and experimental results are given. [ABSTRACT FROM AUTHOR]

The parameters of electrical energy such as voltage amplitude are very important, particularly from the viewpoint of the final consumer and sensitive loads connected to the grid. The dynamic states in the power grid—deep voltage sags and swells—might cause faults and defects in sensitive loads. This paper deals with a three-phase hybrid transformer (HT) without dc energy storage to compensate voltage sags and swells and to protect sensitive loads against the rapid and extensive changes in supply voltage amplitude. The analyzed HT contains two main units: the first one is the conventional electromagnetic transformer, realizing an electromagnetic coupling, and the second one is the buck–boost matrix-reactance chopper, realizing an electrical coupling in the HT unit. In the presented solution, output voltage is transformed in two ways—electromagnetically and electrically. This paper presents an operational description, the theoretical analysis, and the experimental test results from a 2-kVA laboratory model. On the basis of the authors' research, it can be stated that the HT makes it possible to compensate deep voltage sags (deeper than 50% of nominal source voltage) and overvoltages (up to 140% of nominal source voltage) while maintaining good dynamic properties. The main advantages of the proposed solution, in comparison to other conventional solutions, are the ability to control the output voltage in the range of 0.66–3.5 US, good dynamics (transient state during source voltage uS amplitude change is shorter than 10 ms), and galvanic separation between source and load (such as in the case of the conventional electromagnetic transformer). [ABSTRACT FROM PUBLISHER]

A constant switching frequency hysteresis controller based on current error space vector (CESV) for two-level voltage source inverter fed induction motor (IM) drive is proposed in this paper. Here the stator voltages along the α- and β-axes are estimated using current error information and steady-state model of IM. Estimated stator voltages, switching dwell times, and instantaneous voltage error vectors are used in the online hysteresis boundary computations. The steady-state CESV boundaries and the phase voltage normalized harmonic spectrum of the proposed hysteresis controller at different speeds resembles that of a constant switching frequency voltage-controlled bus clamping pulse-width modulation-based drive. The proposed controller exhibits adjacent voltage vector switching, fast dynamic response under transient conditions, and has a simple controller implementation. The superior performance of the proposed controller is simulated using MATLAB/Simulink platform and experimentally verified on a three-phase 2.2 kW IM drive. [ABSTRACT FROM AUTHOR]

A modified scheme for reactive power compensation using static VAr compensators (SVCs) has been proposed in this paper for unbalanced four-wire system. The conventional SVC-based scheme requires both delta ( $\Delta $ $)$ - and star (Y)-connected SVCs for the same purpose. The proposed scheme uses a single-equivalent delta-connected thyristor controlled reactor (TCR) along with a combination of Y- and $\Delta $- connected thyristor switched capacitors for this purpose. The single-equivalent $\Delta $ -TCR in the present scheme is the result of a virtual Y-TCR and the conventional $\Delta $-TCR. This can reduces effective number of switching devices, cost, complexity, and space requirement compared to the conventional SVC-based schemes. Moreover, the proposed scheme can have various advantageous features compared to newly used DSTATCOM. The proposed scheme can also prevent injection of triplen harmonics in to the line, which is injected by Y-TCR in the conventional scheme. An optimized switching function is adopted in the proposed scheme for reduction of additional injected harmonics by TCR. The optimized switching angles are computed offline using gravitational search algorithm and stored in the processor memory for online application. The viability of the proposed scheme is simulated using MATLAB/Simulink and verified by suitable experimental results on a practical system. [ABSTRACT FROM AUTHOR]

This paper presents the concept of three-phase module-integrated converters (MICs) incorporated in grid-tied large-scale photovoltaic (PV) systems. The current-source converter with dc voltage boost capability, namely the single-stage power conversion system, is proposed for the three-phase PV MIC system. A model predictive scheme with low switching frequency is designed to control the proposed topology in such a way that provides a certain amount of active and reactive power in steady-state operation and also provides a proper ratio of reactive power under transient conditions to meet the low-voltage ride through regulations. To predict the future behavior of current control values and switching states, a discrete-time model of the MIC is developed in the synchronous reference frame. It is demonstrated that the injected active and reactive power can be controlled by minimizing the cost function introduced in the predictive switching algorithm. The proposed structure is simulated in MATLAB/SIMULINK software. An experimental verification is provided to justify the performance of the proposed control method through a 300-VA laboratory prototype. The results verify the desired performance of the proposed control scheme for exchanging both active and reactive powers between the PV MIC and the grid within different operating conditions. [ABSTRACT FROM AUTHOR]

The effect of inverter dead time on the inverter output voltage is well studied in the literature. This paper studies the effect of the dead time on the inverter input current. An expression for the switching-cycle-averaged inverter input current including the dead time effect is derived, which shows the dead time effect to primarily result in a reduction in the average value of the inverter dc input current. The effect of dead time on the input current is incorporated into the dc-link dynamic model of a diode-bridge-rectifier (DBR) fed voltage source inverter (VSI). A switching-cycle-average model of a DBR-VSI-fed induction motor is proposed, which considers the effect of dead time on both the ac output voltage and dc input current of the VSI. The proposed average model is used to study the light-load instability phenomenon in a 100-kW open-loop motor drive. The proposed model is shown to predict the region of oscillatory behavior (i.e., region exhibiting light-load instability) with better accuracy than existing average models. The proposed model also accurately predicts the dc-link voltage swing at such oscillatory operating points. While being comparable in accuracy in predicting the system dynamics, the proposed model is much more computationally efficient than the state-of-the-art switching model. The validity of the proposed average model is also confirmed by experimental measurements on a 100-kW induction motor drive. [ABSTRACT FROM AUTHOR]

This paper presents a variable switching point predictive current control (VSP $^2$CC) for the quasi-Z-source inverter (qZSI). The proposed VSP $^2$CC aims to remove the output current error on the ac side, as well as the inductor current and capacitor voltage errors of the quasi-Z-source network on the dc side of the converter. Unlike the previously presented direct model predictive control (MPC) strategies for the qZSI, the proposed control scheme can directly apply the switching signals not only at the discrete time instants, but at any time instant within the sampling interval. Consequently, the shoot-through state can be applied for a shorter time than the sampling interval, resulting in lower output and inductor currents ripples. Experimental results based on field programmable gate array are provided to verify the effectiveness of the introduced control method. As it is shown, the proposed method leads to lower inductor current ripples and less output current total harmonic distortion when compared with the conventional direct MPC. [ABSTRACT FROM AUTHOR]

This paper proposes an isolated single-ended primary-inductor converter (SEPIC) dc–dc converter with ripple-free input current and lossless snubber. The proposed converter is based on a conventional isolated SEPIC converter to enable electrical isolation and high voltage gain using a coupled inductor. The input current ripple is significantly reduced by utilizing an auxiliary circuit that also functions as a lossless snubber circuit with an additional diode. Moreover, the maximum switch voltage stress is clamped to a low voltage by the snubber circuit. Therefore, a low voltage rating mosfet that has low $R_{{\rm{DS(on)}}}$ can be utilized as a main switch device. Hence, the total power efficiency is improved. Experimental results from a 100 W prototype, which are presented to verify the theoretic analysis and performance of the proposed converter. [ABSTRACT FROM PUBLISHER]

In this paper, a class of single-phase Z-source (ZS) ac–ac converters is proposed with high-frequency transformer (HFT) isolation. The proposed HFT isolated (HFTI) ZS ac–ac converters possess all the features of their nonisolated counterparts, such as providing wide range of buck-boost output voltage with reversing or maintaining the phase angle, suppressing the in-rush and harmonic currents, and improved reliability. In addition, the proposed converters incorporate HFT for electrical isolation and safety, and therefore can save an external bulky line frequency transformer, for applications such as dynamic voltage restorers, etc. The proposed HFTI ZS converters are obtained from conventional (nonisolated) ZS ac–ac converters by adding only one extra bidirectional switch, and replacing two inductors with an HFT, thus saving one magnetic core. The switching signals for buck and boost modes are presented with safe-commutation strategy to remove the switch voltage spikes. A quasi-ZS-based HFTI ac–ac is used to discuss the operation principle and circuit analysis of the proposed class of HFTI ZS ac–ac converters. Various ZS-based HFTI proposed ac–ac converters are also presented thereafter. Moreover, a laboratory prototype of the proposed converter is constructed and experiments are conducted to produce output voltage of 110 Vrms / 60 Hz, which verify the operation of the proposed converters. [ABSTRACT FROM AUTHOR]

This paper presents a novel fully integrated step-up dc/dc converter containing circuits to improve electromagnetic emissions. This design utilizes current sources to limit the impulsive current flow into the integrated flying capacitors. This reduces the discontinuous pulse currents normally associated with capacitive converters causing electromagnetic interference (EMI). A variable reference current enables the converter to operate with the lowest possible emissions through the entire operating range and is used to regulate the output voltage. The inclusion of low EMI techniques enables fully integrated power converters to be implemented in systems where noise produced by converters currently restricts or prohibits their use. The proposed 3.2 mW voltage doubler was fabricated in a 0.18 $\mu$m CMOS process. With an input voltage range of 1–1.8 V, the converter produces a 1.6–3.3 V output. Experimental results verify the reduction of emissions to meet IEC 61967-4 Class L using current control with a reduction of noise voltage when compared with the circuit without the proposed techniques. [ABSTRACT FROM AUTHOR]

Dynamic voltage restorer (DVR) technology has become a mature power quality product. In high-power applications, DVR using a multilevel converter is commonly used. However, DVR using a multilevel direct pulse width modulation (PWM) ac–ac converter has not been well studied. This paper presents a new DVR topology using a cascaded multilevel direct PWM ac–ac converter. In the proposed scheme, the unit cell of the multilevel converter consists of a single-phase PWM ac-ac converter using switching cell structure with coupled inductors. Therefore, the multilevel converter can be short- and open-circuited without damaging the switching devices. Neither lossy RC snubber nor a dedicated soft commutation strategy is required in the proposed DVR. This improves the reliability of the DVR system. The output voltage levels of the multilevel converter increase with the number of cascaded unit cells, and a high ac output voltage is obtained by using low-voltage-rating switching devices. Furthermore, a phase-shifted PWM technique is applied to significantly reduce the size of the output filter inductor. A 1-kW prototype of single-phase DVR is developed, and its performance is experimentally verified. Finally, the simulation results are shown for a three-phase DVR system. [ABSTRACT FROM AUTHOR]

In this paper, a new type of matrix converter (MC) also called a single-phase high-frequency transformer isolated (HFTI) buck MC is proposed. The proposed converter can provide step-down operation of the input voltage with various types of output voltages such as in-phase and out-of-phase output voltages, rectified (or positive) output voltage, and output voltage with step-changed frequency. By incorporating HFT isolation, the proposed MC saves an extra bulky line frequency transformer, which is required for the conventional MCs to provide electrical isolation and safety, when used in application such as dynamic voltage restorers, etc. Two different circuit variations of the proposed HFTI MC are presented with and without continuous output currents, with the latter having less passive components. The safe-commutation strategy is also employed for the proposed HFTI MC to provide current path for the inductor during dead-time, which avoids switch voltage spikes without adding any snubber circuits. The operation principle and circuit analysis of the proposed MC are presented, and switching strategies are also developed to obtain various output voltages. Moreover, a prototype of the proposed MC is fabricated, and experiments are performed to produce in-phase/out-of-phase and rectified output voltages, and output voltage with step-changed frequency. [ABSTRACT FROM PUBLISHER]

The paper presents a new bridgeless power factor correction (PFC) topology, using a recently proposed controllable LCL filter, namely active virtual ground to achieve efficient power conversion, and high-frequency common mode voltage (CM) reduction. The proposed PFC circuit consists of high-frequency semiconductors for shaping inductor current and low-frequency semiconductors to form two different LCL structures for different conditions. This reduces grid differential mode current ripple or inductance. Besides, the PFC CM voltage, a main problem of bridgeless PFCs, is significantly reduced, since the capacitor in the LCL filter clamps the voltage between the grid and the converter ground. The performance of the proposed PFC is experimentally verified. The results show that the proposed PFC guarantees sinusoidal input current, low high-frequency common-mode voltage noise, and has a good agreement with the theoretical findings. [ABSTRACT FROM AUTHOR]

This paper proposes a zero-ripple input-current high-step-up boost–single ended primary inductor converter (SEPIC) dc–dc converter with reduced switch-voltage stress to overcome some drawbacks of the conventional cascaded boost–SEPIC dc–dc converter. In the proposed converter, the input current ripple is significantly removed by the auxiliary circuit at the boost stage and the voltage gain is more increased by using turn ratio of a coupled inductor at the SEPIC stage. Additional, the switch-voltage stress is reduced due to the clamping circuit, and the reverse-recovery problem of the output diode is alleviated by the leakage inductor. Hence, the low-voltage-rating MOSFET, which has low $R_{{{\rm ds(on)}}}$, can be utilized as a main switch device. Therefore, the total power efficiency is improved. The theoretical analysis of the proposed converter is verified on an output 200-V to 200-W prototype. [ABSTRACT FROM AUTHOR]

Distributed energy resources (DERs) are expected to provide ancillary functions including reactive power generation and harmonics compensation. Meanwhile, multilevel inverters and two-level converters with optimal pulsewidth modulation (OPWM) will be commonly used for DERs at high power levels. The challenge is to realize harmonic compensation with limited switching angles. This paper presents an online solution to realize the selective harmonics compensation (SHC), and power generation with DERs. For harmonics compensation, the selective harmonic components in the load current are detected. Then, the harmonic voltages are provided with DERs to cancel out these detected components. Since the power converter is requested to realize both harmonics filtering and power generation, limitations on harmonics compensation at the given power are discussed. Power hardware-in-the-loop-based online verifications are shown at the end of the paper. [ABSTRACT FROM AUTHOR]

In this paper, a design method is proposed for finding the equivalent inductance and capacitance of the single-ended primary-inductor converter (SEPIC). The relations of the output voltage ripple (OVR) of the SEPIC converter are obtained in complete inductor supply mode–continuous conduction mode (CISM-CCM), incomplete inductor supply mode-CCM (IISM-CCM), and IISM-discontinuous conduction mode (IISM-DCM). The maximum of OVR (MOVR) is investigated for a specified range of the input voltage and load resistance. This value of the MOVR is obtained for the minimum values of input voltage and load resistance. In this paper, the minimum values of the equivalent inductance and capacitance are calculated in obtaining the minimum value of the MOVR. One of the other performed studies in this paper is calculation of the switch peak current in CCM and DCM. In addition, the converter is designed based on the minimum values of the MOVR and stress of the switching current. Experimental and simulation results are used to prove the validity of the presented theoretical subjects. [ABSTRACT FROM PUBLISHER]

The five-level active neutral-point-clamped (5L-ANPC) converter has been widely studied for its excellent performance in high-power medium-voltage applications. This paper analyzes the space vector pulse width modulation (SVPWM) strategy of the 5L-ANPC converter in the virtual coordinate, and presents an optimized control strategy which can balance the neutral point (NP) voltage and avoid the dead-time effects for the first time. In this strategy, on one hand, the 125 space vectors are combined by 96 triangles in the seven-segment vector synthesis method, then the triangles are divided into seven categories which have different characteristics of balancing the NP voltage, and every category has its own principles to choose the vector sequence and compute the vector durations. On the other hand, the dead-time effects of the 5L-ANPC converter are studied in detail and the transitions between different switching states are constrained in the optimized control strategy to avoid the dead-time effects that cannot be compensated by traditional pulse-based dead-time compensation methods. Finally, the optimized SVPWM strategy is experimentally verified in this paper. [ABSTRACT FROM AUTHOR]

This paper explores the feasibility of active clamping techniques in isolated time-sharing (TS) multiple-input converters (MICs). Additional losses caused by energy transfer from the leakage inductance in the isolating coupled-inductor into the input switches are addressed with a common active clamping leg for all input legs. An active clamping technique is applied to isolated TS-MIC to minimize the additional switching losses and voltage stresses on input legs. This paper also conducts an operational analysis of an isolated time-sharing dual-input single-ended primary-inductor converter (I-TS-DI-SEPIC) with the discussed active clamping technique. Zero-voltage switching can be achieved on the first-turned-on input leg and the active clamping leg with a proper driving strategy and well-chosen circuit parameter settings. Discussions on the effect of the active clamping technique to an MIC and the components stresses of the I-TS-DI-SEPIC with the active clamping technique have also been made to assist in the design of TS-MICs. Prototypes of the I-TS-DI-SEPIC with the active clamping technique have been built to demonstrate the performance in the application of split-phase dc distribution systems. Converter efficiency and voltage stresses are experimentally verified, showing that the active clamping technique achieves noticeable efficiency gains and component stress reduction. [ABSTRACT FROM AUTHOR]

The meat grinder is a basic circuit for inductive pulsed-power supply (IPPS). Based on meat grinder, the Institute of Advanced Technology proposed a circuit called the slow transfer of energy through capacitive hybrid (STRETCH) meat grinder, in which an Integrated Gate Commutated Thyristors (IGCT) is selected as the main switch. Tsinghua University proposed the STRETCH meat grinder with inverse current commutation with semiconductor devices (ICCOS) in which the main switch is replaced by a thyristor and the ICCOS subcircuit is introduced to turn off the main switch. To reduce the opening switch voltage and increase the current turning-off capacity for IPPS, this paper presents a novel circuit topology named the meat grinder with self-charged capacitor and thyristors (SECTs). The key idea of the SECT topology is to turn off the primary current by the energy transfer capacitor, which is precharged. The meat grinder with SECT has larger capacity than the STRETCH meat grinder because it replaces the IGCT with a thyristor and is simpler than the STRETCH meat grinder with ICCOS because it only needs one capacitor. The suggested circuit is more suitable for IPPS module with high energy density. Simulation and experiment have been carried out to validate the circuit. [ABSTRACT FROM PUBLISHER]

A novel isolated dc–dc converter is proposed, using the T-Type topology with zero voltage switching and pulse width modulated with a capacitive output filter. It uses four switches, two of which are subjected to the input voltage, and the other two to half the input voltage. All switches commutate under zero voltage over a wide load range. The proposed converter has the following features: (a) symmetrical operation of the isolation transformer, (b) modulation by pulse width with constant frequency, (c) zero voltage switching, and (d) three-level voltage applied to the primary winding of the transformer. Theoretical analysis, design example, and experimental data for a 2 kW, 400 VDC input, 400 VDC output, and 50 kHz switching frequency laboratory prototype, working in two operating points are included in this paper. The measured efficiency was 95% at 950 W. [ABSTRACT FROM AUTHOR]

To regulate an output ac voltage in inverter systems having wide input dc voltage variation, a buck–boost power conditioning system is preferred. This paper proposes a novel high-efficiency quasi single-stage single-phase buck–boost inverter. The proposed inverter can solve current shoot-through problem and eliminate PWM dead time, which leads to greatly enhanced system reliability. It allows bidirectional power flow and can use MOSFET as switching device without body diode conducting. The reverse recovery issues and related loss of the MOSFET body diode can be eliminated. The use of MOSFET contributes to the reduction of switching and conduction losses. Also, the proposed inverter can be operated with simple pulse width modulation (PWM) control and can be designed at higher switching frequency to reduce the volume of passive components. The detailed experimental results are provided to show the advantages of the proposed inverter. Efficiency measurement shows that using simple PWM control the proposed inverter can obtain peak efficiency of 97.8% for 1.1-kW output power at 30-kHz switching frequency. [ABSTRACT FROM AUTHOR]

This paper presents a new advanced bus-clamped space vector pulsewidth modulation (SVPWM) technique to reduce line current harmonic distortion as well as switching loss. The proposed sequence introduces multiple division of active vector time (MDAVT) in a subcycle. An analysis of optimal subdivision of active vector dwell time is presented. Existing bus-clamping pulsewidth modulation techniques use double-switching clamping sequences, which use only one zero state and apply an active vector twice in a subcycle. The proposed MDAVT-based SVPWM technique presents a hybrid SVPWM technique. The additional switching is added when the fundamental voltage crosses zero. The switching patterns for the other two phases are not changed. The harmonic performance and switching loss characteristics of the proposed hybrid SVPWM techniques over the existing SVPWM is verified with experimental results on a 415-V, 2.2-kW induction motor drive. [ABSTRACT FROM AUTHOR]

A series of switched-capacitor (SC) cell balancing circuits is proposed for rechargeable energy storage devices like battery and supercapacitor strings in this paper. Taking a basic SC-based cell balancing unit as an equivalent resistor, the behavioral models of the proposed cell balancing circuits are developed to evaluate their balancing performance. Comparing with existing SC-based cell balancing circuits, the main advantage of the proposed circuits is that their balancing speed is independent of both of the number of battery cells and initial mismatch distribution of cell voltages. In order to improve the operation performance of SC-based cell balancing circuits in the respect of minimizing the equivalent resistance, optimizing methodologies of circuit parameters are introduced by referring the concepts of slow switching limit and fast switching limit as well as inductive switching limit of SC power converters. Simulation and experimental results are provided to verify the feasibility of the proposed cell balancing circuits. [ABSTRACT FROM AUTHOR]

In this paper, a novel space-vector pulse-width modulation (PWM) scheme for reducing the common-mode voltage (CMV) in the three-phase five-level active neutral-point clamped (5L-ANPC) inverter is proposed, where only the 55 selected voltage vectors among the entire 125 that produce low values of the CMV are utilized. This PWM scheme can significantly reduce the CMV without the increase of switching losses and total harmonic distortion of the output voltages. With the 55 selected voltage vectors, the inverter can still operate up to the maximum modulation index. In addition, the capacitor voltages are controlled by redundant switches of the 5L-ANPC inverters. It has been shown that the peak value of the CMV is decreased to one-twelfth of the dc-link voltage from the simulation and experimental results. [ABSTRACT FROM PUBLISHER]

Diode-assisted buck–boost voltage-source inverter achieves high voltage gain by introducing a switch-capacitor based high step-up dc–dc circuit between the dc source and inverter bridge. As for the unique structure, various pulse width modulation (PWM) strategies are developed with regard to the chopped intermediate dc-link voltage. In order to maximize voltage gain and increase efficiency, this paper proposes a novel PWM strategy. It regulates the average value of intermediate dc-link voltage in one switching time period ( Ts) the same as the instantaneous maximum value of three-phase line voltage by controlling the front boost circuit. Then, the equivalent switching frequency of power devices in the inverter bridge can be reduced to 1/3fs (fs = 1/Ts). The operating principle and closed-loop controller design are analyzed and verified by simulations and experiments. Compared with existing PWM strategies, the new control strategy demonstrates less power device requirement and higher efficiency in high voltage gain applications. It is a more competitive topology for wide range dc/ac voltage regulation in renewable energy applications. Furthermore, with new control strategy, the dc-side inductor current and capacitor voltage contains six-time line-frequency ripples. To overcome the undesired influence of low frequency ripples, it is also suitable for 400–800 Hz medium frequency aircraft and vessel power supply system. [ABSTRACT FROM PUBLISHER]

This paper proposes a new method of generating higher number of levels in the voltage waveform by stacking multilevel converters with lower voltage space vector structures. An important feature of this stacked structure is the use of low voltage devices while attaining higher number of levels. This will find extensive applications in electric vehicles since direct battery drive is possible. The voltages of all the capacitors in the structure can be controlled within a switching cycle using the switching state redundancies (pole voltage redundancies). This helps in reducing the capacitor size. Also, the capacitor voltages can be balanced irrespective of modulation index and load power factor. To verify the concept experimentally, a nine-level inverter is developed by stacking two five-level inverters and an induction motor is run using V/f control scheme. Both steady state and transient results are presented. [ABSTRACT FROM AUTHOR]

This paper proposes a novel high step-up nonisolated single switch dc–dc converter suitable for regulating dc bus in various microsources especially for photovoltaic (PV) sources. Quadratic boost and switched-capacitor technique are used as primary and secondary circuits, respectively. A coupled inductor is applied to make a connection between them, so a high dc voltage gain is achieved. High efficiency is yield where voltage stress on active switch is alleviated by clamped capacitor; consequently, smaller \rmR\rm{DS(ON)} for power switch is required. On the other hand, input current of the proposed converter is continued, hence stress on the input source is reduced. The operating principles and steady-state analyses are discussed in detail for both continuous and discontinuous conduction modes. Also, the boundary condition is computed. To verify the performance of the proposed converter and theoretical calculations, a 250-W prototype converter is implemented with an input voltage of 24 V and an output voltage of 400 V designed especially for PV sources in continuous conduction mode operation. Finally, simulation results are confirmed by experimental results; maximum efficiency is occurred at 150 W and full-load efficiency is 92.96%. [ABSTRACT FROM AUTHOR]

The series configuration of fast semiconductor switches seems to be the key component in the high-voltage and fast rising time pulse generation. In this approach, two important issues must be considered. The first is to provide a safe operating condition for the switches in transient intervals. The second is to design a gate drive system with the capability of driving a large number of discrete devices simultaneously. The aim of this paper is to obviate these two requirements. First, different factors affecting the unbalanced voltage sharing between the series switches are discussed. In this investigation, the switch-to-ground parasitic capacitance effect has been recognized as the major effect on the unbalanced voltage sharing in the transient interval. Two schemes for abating this effect are proposed. To solve the unbalanced voltage distribution, the structure with a snubber circuit in the clamp mode operation is suggested. This scheme can be used for any number of switches without destructively affecting their behavior. In addition, the output pulse with a fast rising time could be obtained by the proposed gate drive system. In order to evaluate the operation of the proposed structure, a stacked switch with the voltage capability of 36 kV is tested experimentally. The characteristics of the obtained pulse are the fast rising time (69.5 ns) with the dV/dt of 460 kv/ \mu \texts and the wide range of the pulsewidth adjusting to 0.5–15 \mu \texts . In addition, the voltage variance of the switches level in the series structure is about 10%. [ABSTRACT FROM AUTHOR]