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The neutral-point voltage-balancing control is a critical issue of a neutral-point-clamped converter. The conventional control strategy is to inject the specific zero-sequence voltage to regulate the redundant vector, but it is unacceptable to the three-phase four-wire system. This paper provides a neutral-point voltage-balancing control by the dipolar modulation, and the control freedom of the zero-sequence voltage is flexible. Therefore, the proposed method is suitable for both three-phase three-wire and three-phase four-wire systems. Besides, the proposed method improves the control dynamic in a reactive power system. The proposed neutral-point voltage-balancing control is verified by the mathematical analysis and experimental results. The control dynamic, power loss estimation, and the output current performance are analyzed in this paper. [ABSTRACT FROM PUBLISHER]

A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]

The neutral-point potential fluctuation in single-phase three-level rectifiers leads to coupling between the line current regulation and dc-link capacitor voltage balancing, deteriorating waveform quality of the line current. For addressing this issue, this paper proposes a low-complexity model predictive current control (MPCC) with constant switching frequency, which achieves a decoupling control of the line current and the neutral-point potential under the unbalanced load condition. The switching frequency is fixed by combining the MPCC scheme with predefined switching sequences. The boundary of the durations for voltage vectors in switching sequences is presented to balance the capacitor voltage without worsening the line current quality. The optimal switching sequence and the corresponding optimal durations of voltage vectors in the switching sequence are readily derived without the assessment of the cost function, which dramatically simplifies the complexity of the MPCC scheme. Finally, simulations and experimental results are conducted to verify the effectiveness of the proposed MPCC scheme. [ABSTRACT FROM AUTHOR]

This paper presents a merged-two-stage circuit topology suitable for either wide-range dc input voltage or ac line voltage at low-to-moderate power levels (e.g., up to 30 W). This two-stage topology is based on a soft-charged switched-capacitor preregulator/transformation stage and a high-frequency magnetic regulator stage. Soft charging of the switched capacitor circuit, zero voltage switching of the high-frequency regulator circuit, and time-based indirect current control are used to maintain high efficiency, high power density, and high power factor. The proposed architecture is applied to an LED driver circuit, and two implementations are demonstrated: a wide input voltage range dc-dc converter and a line interfaced ac-dc converter. The dc-dc converter shows 88%-96% efficiency at 30-W power across 25-200-V input voltage range, and the ac-dc converter achieves 88% efficiency with 0.93 power factor at 8.4-W average power. Contributions of this paper include: 1) demonstrating the value of a merged two-stage architecture to provide substantial design benefits in high-input voltage, low-power step down conversion applications, including both wide-range-input dc-dc and line-input ac-dc systems; 2) introduction of a multimode soft-charged SC stage for the merged architecture that enables compression of an 8:1 input voltage range into a 2:1 intermediate range, along with its implementation, loss considerations, and driving methods; and 3) merging of this topology with an resonant transition discontinuous-mode inverted buck stage and pseudocurrent control to enable step-down power conversion (e.g., for LED lighting) operating at greatly increased frequencies and reduced magnetics size than with more conventional approaches. [ABSTRACT FROM AUTHOR]

The parameters of electrical energy such as voltage amplitude are very important, particularly from the viewpoint of the final consumer and sensitive loads connected to the grid. The dynamic states in the power grid—deep voltage sags and swells—might cause faults and defects in sensitive loads. This paper deals with a three-phase hybrid transformer (HT) without dc energy storage to compensate voltage sags and swells and to protect sensitive loads against the rapid and extensive changes in supply voltage amplitude. The analyzed HT contains two main units: the first one is the conventional electromagnetic transformer, realizing an electromagnetic coupling, and the second one is the buck–boost matrix-reactance chopper, realizing an electrical coupling in the HT unit. In the presented solution, output voltage is transformed in two ways—electromagnetically and electrically. This paper presents an operational description, the theoretical analysis, and the experimental test results from a 2-kVA laboratory model. On the basis of the authors' research, it can be stated that the HT makes it possible to compensate deep voltage sags (deeper than 50% of nominal source voltage) and overvoltages (up to 140% of nominal source voltage) while maintaining good dynamic properties. The main advantages of the proposed solution, in comparison to other conventional solutions, are the ability to control the output voltage in the range of 0.66–3.5 US, good dynamics (transient state during source voltage uS amplitude change is shorter than 10 ms), and galvanic separation between source and load (such as in the case of the conventional electromagnetic transformer). [ABSTRACT FROM PUBLISHER]

This paper presents a variable switching point predictive current control (VSP $^2$CC) for the quasi-Z-source inverter (qZSI). The proposed VSP $^2$CC aims to remove the output current error on the ac side, as well as the inductor current and capacitor voltage errors of the quasi-Z-source network on the dc side of the converter. Unlike the previously presented direct model predictive control (MPC) strategies for the qZSI, the proposed control scheme can directly apply the switching signals not only at the discrete time instants, but at any time instant within the sampling interval. Consequently, the shoot-through state can be applied for a shorter time than the sampling interval, resulting in lower output and inductor currents ripples. Experimental results based on field programmable gate array are provided to verify the effectiveness of the introduced control method. As it is shown, the proposed method leads to lower inductor current ripples and less output current total harmonic distortion when compared with the conventional direct MPC. [ABSTRACT FROM AUTHOR]

This paper presents a novel fully integrated step-up dc/dc converter containing circuits to improve electromagnetic emissions. This design utilizes current sources to limit the impulsive current flow into the integrated flying capacitors. This reduces the discontinuous pulse currents normally associated with capacitive converters causing electromagnetic interference (EMI). A variable reference current enables the converter to operate with the lowest possible emissions through the entire operating range and is used to regulate the output voltage. The inclusion of low EMI techniques enables fully integrated power converters to be implemented in systems where noise produced by converters currently restricts or prohibits their use. The proposed 3.2 mW voltage doubler was fabricated in a 0.18 $\mu$m CMOS process. With an input voltage range of 1–1.8 V, the converter produces a 1.6–3.3 V output. Experimental results verify the reduction of emissions to meet IEC 61967-4 Class L using current control with a reduction of noise voltage when compared with the circuit without the proposed techniques. [ABSTRACT FROM AUTHOR]

Dynamic voltage restorer (DVR) technology has become a mature power quality product. In high-power applications, DVR using a multilevel converter is commonly used. However, DVR using a multilevel direct pulse width modulation (PWM) ac–ac converter has not been well studied. This paper presents a new DVR topology using a cascaded multilevel direct PWM ac–ac converter. In the proposed scheme, the unit cell of the multilevel converter consists of a single-phase PWM ac-ac converter using switching cell structure with coupled inductors. Therefore, the multilevel converter can be short- and open-circuited without damaging the switching devices. Neither lossy RC snubber nor a dedicated soft commutation strategy is required in the proposed DVR. This improves the reliability of the DVR system. The output voltage levels of the multilevel converter increase with the number of cascaded unit cells, and a high ac output voltage is obtained by using low-voltage-rating switching devices. Furthermore, a phase-shifted PWM technique is applied to significantly reduce the size of the output filter inductor. A 1-kW prototype of single-phase DVR is developed, and its performance is experimentally verified. Finally, the simulation results are shown for a three-phase DVR system. [ABSTRACT FROM AUTHOR]

In this paper, a new type of matrix converter (MC) also called a single-phase high-frequency transformer isolated (HFTI) buck MC is proposed. The proposed converter can provide step-down operation of the input voltage with various types of output voltages such as in-phase and out-of-phase output voltages, rectified (or positive) output voltage, and output voltage with step-changed frequency. By incorporating HFT isolation, the proposed MC saves an extra bulky line frequency transformer, which is required for the conventional MCs to provide electrical isolation and safety, when used in application such as dynamic voltage restorers, etc. Two different circuit variations of the proposed HFTI MC are presented with and without continuous output currents, with the latter having less passive components. The safe-commutation strategy is also employed for the proposed HFTI MC to provide current path for the inductor during dead-time, which avoids switch voltage spikes without adding any snubber circuits. The operation principle and circuit analysis of the proposed MC are presented, and switching strategies are also developed to obtain various output voltages. Moreover, a prototype of the proposed MC is fabricated, and experiments are performed to produce in-phase/out-of-phase and rectified output voltages, and output voltage with step-changed frequency. [ABSTRACT FROM PUBLISHER]

The paper presents a new bridgeless power factor correction (PFC) topology, using a recently proposed controllable LCL filter, namely active virtual ground to achieve efficient power conversion, and high-frequency common mode voltage (CM) reduction. The proposed PFC circuit consists of high-frequency semiconductors for shaping inductor current and low-frequency semiconductors to form two different LCL structures for different conditions. This reduces grid differential mode current ripple or inductance. Besides, the PFC CM voltage, a main problem of bridgeless PFCs, is significantly reduced, since the capacitor in the LCL filter clamps the voltage between the grid and the converter ground. The performance of the proposed PFC is experimentally verified. The results show that the proposed PFC guarantees sinusoidal input current, low high-frequency common-mode voltage noise, and has a good agreement with the theoretical findings. [ABSTRACT FROM AUTHOR]

The five-level active neutral-point-clamped (5L-ANPC) converter has been widely studied for its excellent performance in high-power medium-voltage applications. This paper analyzes the space vector pulse width modulation (SVPWM) strategy of the 5L-ANPC converter in the virtual coordinate, and presents an optimized control strategy which can balance the neutral point (NP) voltage and avoid the dead-time effects for the first time. In this strategy, on one hand, the 125 space vectors are combined by 96 triangles in the seven-segment vector synthesis method, then the triangles are divided into seven categories which have different characteristics of balancing the NP voltage, and every category has its own principles to choose the vector sequence and compute the vector durations. On the other hand, the dead-time effects of the 5L-ANPC converter are studied in detail and the transitions between different switching states are constrained in the optimized control strategy to avoid the dead-time effects that cannot be compensated by traditional pulse-based dead-time compensation methods. Finally, the optimized SVPWM strategy is experimentally verified in this paper. [ABSTRACT FROM AUTHOR]

In this paper, a novel space-vector pulse-width modulation (PWM) scheme for reducing the common-mode voltage (CMV) in the three-phase five-level active neutral-point clamped (5L-ANPC) inverter is proposed, where only the 55 selected voltage vectors among the entire 125 that produce low values of the CMV are utilized. This PWM scheme can significantly reduce the CMV without the increase of switching losses and total harmonic distortion of the output voltages. With the 55 selected voltage vectors, the inverter can still operate up to the maximum modulation index. In addition, the capacitor voltages are controlled by redundant switches of the 5L-ANPC inverters. It has been shown that the peak value of the CMV is decreased to one-twelfth of the dc-link voltage from the simulation and experimental results. [ABSTRACT FROM PUBLISHER]

Diode-assisted buck–boost voltage-source inverter achieves high voltage gain by introducing a switch-capacitor based high step-up dc–dc circuit between the dc source and inverter bridge. As for the unique structure, various pulse width modulation (PWM) strategies are developed with regard to the chopped intermediate dc-link voltage. In order to maximize voltage gain and increase efficiency, this paper proposes a novel PWM strategy. It regulates the average value of intermediate dc-link voltage in one switching time period ( Ts) the same as the instantaneous maximum value of three-phase line voltage by controlling the front boost circuit. Then, the equivalent switching frequency of power devices in the inverter bridge can be reduced to 1/3fs (fs = 1/Ts). The operating principle and closed-loop controller design are analyzed and verified by simulations and experiments. Compared with existing PWM strategies, the new control strategy demonstrates less power device requirement and higher efficiency in high voltage gain applications. It is a more competitive topology for wide range dc/ac voltage regulation in renewable energy applications. Furthermore, with new control strategy, the dc-side inductor current and capacitor voltage contains six-time line-frequency ripples. To overcome the undesired influence of low frequency ripples, it is also suitable for 400–800 Hz medium frequency aircraft and vessel power supply system. [ABSTRACT FROM PUBLISHER]

A novel high step-up dc–dc converter with a quasi-active switched-inductor structure for a renewable energy system is presented in this paper. The proposed converter is composed of two coupled inductors which can be integrated into one magnetic core, two capacitors, two active switches, and three diodes. The primary sides of coupled inductors are charged in parallel by the input source, and the secondary sides of coupled inductors are discharged in series with the input source and two capacitors to achieve high step-up voltage gain with an appropriate duty ratio. The two sets of diode–capacitor circuits not only help to lift the voltage conversion gain but also alleviate voltage spike affected by the leakage inductance to limit the voltage stress across the power switch effectively. Therefore, the two low on-state resistance switches can be adopted to reduce conduction loss. Furthermore, the two diodes have no reverse-recovery problem due to turn off naturally, the reverse-recovery problem of the output diode is also alleviated by the leakage inductor and lower part count is needed; therefore, the power conversion efficiency can be further improved. The operating principles and steady-state analyses are discussed in detail; then, the performance of the proposed converter is compared with existing converters. Finally, a prototype is established in the laboratory, and the experimental results are given to verify the correctness of the analysis. [ABSTRACT FROM AUTHOR]

The flying capacitor multilevel inverter (FCMLI) is one of the well-known structures of multilevel inverters having attracted considerable attention because of its merits. In spite of its many advantages, it has some limitations such as high volume and complicated control method because of its bulky capacitors and their voltage balancing requirement. Moreover, the high number of power semiconductors required makes this structure susceptible to failure. To increase the ratio of the number of levels to the number of components, an uneven distribution of capacitor voltages has been suggested in previous reports; however, this approach complicates the control method. Up to now, almost all presented methods suffer from high computational load and/or structure-dependent algorithm. In this paper, a simple state-based and structure-independent method is proposed for capacitor voltage regulation. The proposed method is straightforward and can perform online computation of switching sequences in a computationally efficient manner without any need for stored information or look-up tables. The method is conveniently extendible to any number of cells and levels in an FCMLI structure with arbitrary dc link voltage distribution schemes. Simulation and experimental results show the effectiveness and simplicity of this method. [ABSTRACT FROM PUBLISHER]

A capacitor voltage-balancing method for a nested neutral point clamped (NNPC) inverter is proposed in this paper. The NNPC inverter is a newly developed four-level voltage-source inverter for medium-voltage applications with properties such as operating over a wide range of voltages (2.4–7.2 kV) without the need for connecting power semiconductor in series and high-quality output voltage. The NNPC topology has two flying capacitors in each leg. In order to ensure that the inverter can operate normally and all switching devices share identical voltage stress, the voltage across each capacitor should be controlled and maintained at one-third of dc bus voltage. The proposed capacitor voltage-balancing method takes advantage of redundancy in phase switching states to control and balance flying capacitor voltages. Simple and effective logic tables are developed for the balancing control. The proposed method is easy to implement and needs very few computations. Moreover, the method is suitable for and easy to integrate with different pulse width modulation schemes. The effectiveness and feasibility of the proposed method is verified by simulation and experiment. [ABSTRACT FROM PUBLISHER]

This paper presents a new hysteresis current regulation strategy for the neutral point clamped and flying capacitor (FC) three-level inverters. The strategy uses the measured average of the switched phase leg output voltage to adjust the controller hysteresis band as the load back EMF varies to maintain a near constant phase leg switching frequency. The phase leg switchings are then fine tuned to a fixed frequency clock to further improve frequency regulation. Next, the zero-crossings of the measured phase leg average voltages are used to select between positive and negative switched output voltage levels, so that only one hysteresis current regulator is required for the full inverter switched output voltage range. For the FC inverter, a state machine is then added to select between redundant switching states to maintain balanced capacitor voltages. Finally, the controller is extended to a three-phase system by subtracting the common mode interacting current from the total phase leg current error before making any switching decision. The resulting controller achieves a line-to-line harmonic performance that is very close to open-loop phase disposition pulse width modulation, while retaining all of the dynamic benefits of hysteresis current regulation. [ABSTRACT FROM AUTHOR]

This paper presents a buck-boost dc-dc converter for LED drivers capable of delivering an output current ranging from 0.1 to 2 A and a variable output voltage ranging between 2 and 5 V, starting from an input voltage spanning from 2.7 to 5.5 V. The dc-dc converter, realized in a 0.18-μm CMOS technology with 5-V option, occupies an area of 4 mm2 including pads. The circuit features automatic mode switching and dynamic sizing of the power transistors to achieve a peak efficiency of 91%. With a switching frequency of 2.5 MHz, the achieved line regulation is lower than 0.1% V-1 and the output voltage ripple is less than 10 mV. The obtained turn-on and load transient settling time are lower than 40 μs, thus allowing pulsed operation of the LEDs, as well as switching among LEDs of different colors. [ABSTRACT FROM AUTHOR]

This paper discusses about the voltage output ripple reduction and error minimization for the direct-drive, linear switched reluctance generator (LSRG)-based wave power generation system. First, the concept of the LSRG-based wave power generation system is studied. According to the characteristics of the LSRG, the suitable drive circuit dedicated to proper current excitation and generation is established. Second, the reasons that cause voltage output ripples are investigated. To reduce the remarkable ripples from phase current commutations, a current distribution function (CDF) is proposed based on the minimized copper loss principle. Third, the dual-loop control strategy with current and voltage as the inner and outer loop is constructed, implemented with the proposed CDF. Theoretical bases of the control strategy are derived. The simulation results prove that the proposed control algorithm is capable of voltage ripple suppression and error reduction within the range of ±0.5 V over the entire operation speed for wave energy extraction, validated by experimental verification. [ABSTRACT FROM AUTHOR]

In this paper, a predictive direct power control (DPC) method without sector information and voltage vector selection is proposed for three-phase grid-connected converters. Different from conventional predictive direct power controllers, the proposed strategy always adopts fixed voltage vectors, instead of selecting voltage vectors according to the angular information of the grid-voltage vector or the virtual-flux vector. The converter switching time is obtained by minimizing the squared errors of the instantaneous active and reactive power. Switch duty cycles are then calculated and equivalently reconstructed. The proposed strategy not only presents rapid dynamic response due to the use of the predictive controller, but also possesses excellent steady-state performance as a result of duty cycle reconstruction. The main advantage of the proposed control scheme, compared with the classical DPC strategies, is that it is unnecessary to use sector information of the grid-voltage vector, and selection of active voltage vectors is also not required here. Therefore, incorrect selection of voltage vectors and the resulting performance deterioration are surely avoided, without the need of any additional compensation measures. An in-depth comparison and experimental assessment are given to validate the effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

This paper presents a new gate drive circuit for driving a series string of insulated-gate bipolar transistors (IGBTs). The proposed quasi-active gate control (QAGC) circuit is simple to implement as it consists of only a few passive components in addition to a standard gate driver. No separate isolation power supply is required for the upper devices in the stack. The proposed QAGC circuit provides an effective way to drive the power devices and control static and dynamic voltage sharing to the devices at the same time. The theoretical switching operation and the oscillation stability analysis allow criteria for component selection to be established. Limitations of the QAGC circuit are also identified. The modification of the circuit to support more power devices in the series stack is discussed with the aid of the simulation results. The switching operation of the circuit is validated from the experimental results using two IGBTs connected in series. The circuit shows an excellent switching operation with well-controlled dynamic and static voltage sharing and comparable gate voltage between the coupled devices. [ABSTRACT FROM AUTHOR]

In this paper, a soft-switching dc/dc converter with secondary-side phase-shift control strategy is proposed to improve the conversion efficiency and minimize the primary switch voltage stress in the high input voltage applications. Zero-voltage-switching performance is achieved for both the primary- and secondary-side power devices in a wide load range to reduce the switching losses due to the secondary-side phase-shift control scheme. Furthermore, compared with the conventional phase-shift control mechanism, the circulating current at the freewheeling stage is effectively suppressed as well to minimize the conduction losses. Moreover, the voltage stress of the primary switches is only half of the input voltage by employing the improved three-level structure, which makes the low-voltage rated power devices available to improve the circuit performance. In addition, the converter can work in the buck, balance, and boost modes to achieve a relatively wide input voltage range, which is an expected advantage for the communication power system to minimize the electrolytic capacitors with an acceptable hold-up time. The operation principle is analyzed and experimental results of a 1-kW 100-kHz prototype are provided to verify the effectiveness and the advantages of the proposed converter. [ABSTRACT FROM AUTHOR]

This paper provides a perspective on progress toward realization of efficient, fully integrated dc–dc conversion and regulation functionality in CMOS platforms. In providing a comparative assessment between the inductor-based and switched-capacitor approaches, the presentation reviews the salient features in effectiveness in utilization of switch technology and in use and implementation of passives. The analytical conclusions point toward the strong advantages of the switched-capacitor (SC) approach with respect to both switch utilization and much higher energy densities of capacitors versus inductors. The analysis is substantiated with a review of recently developed and published integrated dc–dc converters of both the inductor-based and SC types. [ABSTRACT FROM AUTHOR]

An auxiliary capacitor-based balancing approach is adopted in this paper to equalize the dc-link capacitor voltages of a diode-clamped multilevel converter (DCMC). Four balancing circuits, including the generalized, one-level-capacitor, one-capacitor, and simplified one-capacitor-based configurations are discussed for a five-level DCMC system. These configurations are different in connection of the auxiliary circuits and numbers of the capacitors and switches, but they work on the same principle called ping-pong operation by utilizing the auxiliary capacitor as an equalizer between the capacitors of different voltages. The unbalance phenomenon, ping-pong principle, circuit configurations, and their switching schemes are analyzed, respectively. The superiorities of the proposed approach include balancing operation regardless of load power factor and modulation index, control simplicity, and independence from main circuits when compared to the traditional approaches. Simulations and experimental results verified the performances using the proposed balancing circuits and control strategies. [ABSTRACT FROM AUTHOR]

Single-phase three-level neutral point clamped (NPC) converters are widely applied in high-speed railway electrical traction drive systems. A significant problem related to the single-phase three-level NPC converters is the fluctuation of the neutral-point voltage. In this paper, a capacitor voltage balancing technique is proposed that injects an offset voltage into the sinusoidal modulating signals of the conventional carrier-based pulsewidth modulation (CBPWM) method. Furthermore, when the injected offset voltage is maximized, it cannot only balance the dc-link capacitors voltages, but also reduce switching losses. Theoretical analysis has shown that both methods can control the neutral point voltage effectively, but the neutral point voltage controller in the CBPWM with maximum offset voltage injection (CBPWM-MOVI) has a faster dynamic response. It was observed that the high-order harmonics frequencies of the line current are centered around the twice switching frequency in the CBPWM with the offset voltage injection (CBPWM-OVI) but are centered around the switching frequency in the CBPWM-MOVI. And also, the CBPWM-MOVI has switching commutations number at least 25% below that of the CBPWM-OVI in one modulating signal period. The performances of the two strategies were verified by simulation and experimental tests. [ABSTRACT FROM AUTHOR]

Due to the increasing chip temperature and the strong dependency of leakage power on temperature, thermal aware power management has received a considerable amount of attention recently in energy efficient system design. In this paper, we propose a temperature-aware intra-task scheduling algorithm to minimize leakage energy in real-time systems. The basic idea of our algorithm is to run tasks at full speed when the chip temperature is low or the work urgency is high, and switch the processor to a low-power state when the chip temperature is high or the workload is light. Our offline algorithm can achieve the optimal leakage reduction for a given task with the worst-case execution time, while the online algorithm has a very low runtime complexity. The simulation results show that the online algorithm is able to reduce 34% of total leakage energy on average in both real-world and artificial benchmarks. Finally, we demonstrate how to combine our algorithm with existing dynamic voltage scaling technique to optimize the overall energy consumption. [ABSTRACT FROM AUTHOR]

The design and characterization in high-voltage (HV)-CMOS technology of an innovative intelligent power switch (IPS) for harsh automotive applications is proposed in this paper. To safely handle the ordinary and extraordinary automotive electrical and environmental conditions, a systematic design flow is followed: several design solutions are presented at the architectural and circuital level, integrating on-chip self-diagnostic capabilities and full protection against the high voltage and reverse polarity, the effects of wiring parasitics, and the over-current and over-temperature phenomena. Moreover, the current slope and soft start integrated techniques ensure a low electromagnetic interference, and the IPS is also configurable to efficiently drive different interchangeable loads. The innovative IPS has been implemented in a 0.35-\mu\m HV-CMOS technology and has been embedded in mechatronic third generation brush-holder regulator system-on-chip for an automotive alternator. The electrical simulations and experimental characterization and the testing at component and on-board system levels prove that the proposed design allows a compact and smart power switch realization facing the harshest automotive conditions. [ABSTRACT FROM AUTHOR]

When small currents are interrupted by a vacuum switch, it is well known that the chopping current and the associated overvoltage are observed. Many investigations on the current-chopping phenomena in alternating-current (ac) circuits have been carried out, but there are no data available on inverter circuits in spite of their recent wide application to synchronous motor systems. In this paper, chopping-current levels and the overvoltages in an inverter circuit under a simple three-level pulsewidth-modulated control are investigated. As a result, the mean chopping-current level is three to four times higher than that in an ac circuit. In particular, high chopping currents occur only when the timing of the current interruption by the vacuum switch synchronizes with that of the inverter's switching, which we call “double chopping.” High chopping current due to double chopping might be harmful since the high overvoltage proportional to the chopping-current level could damage the insulation of electric equipment. However, we experimentally confirmed that a typical surge suppressor could reduce overvoltage. [ABSTRACT FROM AUTHOR]