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This paper proposes a novel polygonal voltage space vector structure (SVS) having 30 sides, for a star-connected induction motor drive. The SVS eliminates the presence of harmonics up to 25th order from motor phase voltage throughout the entire modulation range, providing a torque profile devoid of lower order pulsations. Linear modulation is extended till 99.63% of base speed without exceeding the motor phase voltage rating. Topology consists of a dc-link fed primary inverter and two equal low voltage modular capacitor fed secondary inverters. Here the harmonics generated by the primary inverter is canceled by the secondary inverter which acts as a switched capacitive filter. Detailed description of the SVS generation and timing calculations are provided in this paper. Effectiveness of the proposed scheme is validated using experimental results, inverter loss calculations, and harmonic analysis. [ABSTRACT FROM AUTHOR]

This paper presents an optimization method for selective harmonic elimination in a cascaded multilevel inverter using teaching–learning-based optimization (TLBO). The main objective in selective harmonic elimination (SHE) strategy is to eliminate low-order harmonics by solving nonlinear equations and reaching optimal solution, while the fundamental component is satisfied. In this paper, in one side, the influence of optimal dc sources is investigated to reach the SHE goal, and in another side, comparing optimization methods is considered. In this paper, the TLBO as a recently emerged nature-inspired algorithm is presented to provide better results for the SHE in comparison with genetic algorithm, artificial bee colony, imperialistic competitive algorithm, harmony search, ant colony optimization, particle swarm optimization, and differential evolution. For better comparison of those methods and influence of optimal dc sources, 5-, 9-, and 15-level inverters are chosen and MATLAB software is used for optimization. Simulation results show the superiority of TLBO, higher precision and probability of convergence than other mentioned algorithms. Finally, to validate the influence of optimal dc sources and the accuracy of TLBO results, the experimental setup is conducted for a 5-level cascaded H-bridge inverter with optimal dc sources. [ABSTRACT FROM AUTHOR]

First harmonic analysis (FHA) is arguably the most widely used analytical technique for wireless power transfer (WPT) circuits due to its simplicity. Although FHA can provide closed-form solutions, the existence of rectifier diode forward voltage drop and higher order harmonics, especially the second and third harmonics at variable duty cycle operation, can significantly deteriorate its accuracy. This paper presents an accurate and efficient method called enhanced multiple harmonic analysis (eMHA) for the optimal design and optimal control of WPT systems. The eMHA method considers the nature of nonlinear rectification networks under nonsinusoidal current and reexamines the concept of the equivalent load. As a result, the rectified WPT system is transformed into a series of linear systems with complex load impedances. The steady-state electric quantities can be then explicitly calculated. This enables eMHA to seamlessly work with numerical optimization algorithms to facilitate the automated design and optimization of WPT systems. An example of optimal design and optimal control of a 10 W WPT system is demonstrated. The results obtained by eMHA and FHA are also compared. A prototype of the designed circuit was constructed. The accuracy and effectiveness of eMHA are verified by experimental measurements. This paper is accompanied by a MATLAB-based analytical tool with a graphical user interface demonstrating the effects of circuit variables on electrical quantities and waveforms. [ABSTRACT FROM AUTHOR]

The supply-side current of an inverter-fed induction motor (IM) is easily accessible and less affected by noises than the motor stator current. This paper proposes a novel sensorless speed estimation method for an IM using the spectrum of the supply-side current. However, due to the influence of fundamental supply frequency, it is difficult to carry out the speed detection straight from the supply-side current signal. In this paper, an analytic model for characterizing the supply-side current of an inverter-fed IM using the modulation theory and the switching function concept is developed. Then, the Hilbert transform is applied to extract the speed harmonic component from the supply-side current. Finally, an interpolated Goertzel algorithm is put forward to enhance the estimation precision of IM speed. The performance of the proposed sensorless speed estimation method is proved by the speed estimation results obtained from hardware experiments of an IM fed by an inverter under different load conditions. [ABSTRACT FROM AUTHOR]

This paper proposes a novel discontinuous pulse-width modulation (DPWM) method to reduce the current harmonics and improve the system efficiency for a single-phase three-level neutral-point clamped inverter. In single-phase inverters, the unipolar pulse-width modulation (UP-PWM) method is commonly used. However, this method has the disadvantage of power losses due to numerous switching operations. Conventional DPWM methods reduce the power losses and improve efficiency but increase the current total harmonic distortion (THD). To overcome these weaknesses, this paper proposes a hybrid DPWM switching method combining two PWM methods: the UP-PWM method and the conventional DPWM method called one-pole clamped PWM method. Since the proposed DPWM method offers all the advantages of both PWM methods, the optimal performance—with regard to the power losses and current THD—is obtained. The combination of two PWM methods is investigated by analyzing the power losses and current THD. Based on the analysis, the process determining the optimal operating condition is introduced. The effectiveness of the proposed DPWM method is demonstrated through simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper proposes generation of a 15-level (14 concentric) dodecagonal voltage space vector structure (DVSVS) for a star connected induction motor drive. The proposed multilevel DVSVS is obtained by cascading two inverters, namely a primary and secondary inverter. The primary inverter is a five-level (5L) structure formed by stacking two three-level flying capacitors with individual reduced dc sources and the secondary inverter is also a 5L structure formed by cascading two capacitor-fed cascaded H-bridges (CHB). The active power is supplied by the primary inverter, while the secondary inverter acts as switched capacitor harmonics filter, and capacitors in the secondary inverter are balanced naturally irrespective of load power factor for entire modulation index. The high-voltage dc supply fed primary inverter is operated in quasi-square wave mode, while the high frequency switching is applied to low voltage CHBs, thus, reducing the overall switching loss. The proposed scheme gives the advantages of both DVSVS and multilevel structure, thus, making it one of the solutions for battery or stacked dc-fed applications. The paper also presents the experimental results as well as comparison study with the existing topologies to support the advantages of proposed scheme. [ABSTRACT FROM AUTHOR]

Neutral-point-clamped (NPC) multilevel inverter fed high power drives operating at low switching frequency are prone to low-order torque pulsations. For a case of N switching angles per quarter, apart from maintaining the fundamental component, (N-1) voltage harmonics can be eliminated. Consequently, \fracN-12 or lower number of torque harmonics could be eliminated. This paper proposes an optimal pulse-width modulation (PWM), which minimizes the combined root mean square (RMS) value (\tau RMS ) of torque harmonics of order lower than $6N$ at any modulation index (M$) for an induction motor drive fed from an NPC three-level inverter. This paper considers cases of two, three, and four switching angles per quarter cycle of the pole voltage. Compared with synchronized sine-triangle PWM and selective harmonic elimination (SHE) PWM, the proposed PWM reduces the first (N-1$ ) torque harmonics (i.e., \tau _6 ) over a wide speed range. Simulation and experimental results are presented on a 3.7-kW open-loop constant volts-per-Hertz induction motor drive. [ABSTRACT FROM PUBLISHER]

This paper presents a simplified implementation technique for direct torque control (DTC) of asymmetric six-phase induction motor drive. Current harmonics of fifth and seventh order are observed in the phase currents if conventional DTC scheme is extended for the asymmetric six-phase machine. These harmonic components are not responsible for torque production, thus causing losses in the motor winding. Synthetic vectors are generally used for reduction of current harmonics. Average voltage in $xy$ subspace is maintained to zero by synthetic vectors leading to reduction of currents in $xy$ subspace. A simplified method of implementation of synthetic vectors is proposed in this paper, which eliminates the need for designing of switching sequence and requirement of field-programmable gate array. Also, the number of synthetic vectors that can be possibly produced is increased compared with the ones developed by techniques available in the literature. The experimentation is carried out on a laboratory-developed prototype and the experimental results are presented in this paper to verify the proposed scheme. [ABSTRACT FROM PUBLISHER]

This paper proposes an active switching harmonic current reduction method within the dc-link capacitor of two-level, three-phase, back-to-back converters. This method is based on the derived analytical solution for switching harmonic currents in the dc-link. It is shown that by controlling the pulse width modulation carrier waveform's phase angles, the harmonics in the second carrier band of the rectifier and the inverter can be synchronized such that cancellation occurs in the dc-link capacitor. This synchronization is provided by harmonic phase feedback control. The feasibility of the proposed approach has been verified experimentally and results are presented in this paper. [ABSTRACT FROM PUBLISHER]

Switching harmonic attenuation has always been challenging for inverters used in high-power conversion applications, where ratio of switching to fundamental frequency is low. Addition of multiple LC-trap filters is no doubt a feasible cost-effective method, which has increasingly been used, but generally susceptible to filter parameter variations and harmonic resonances. This paper hence presents an alternative active trap filter (ATF), based on a series-LC-filtered inverter, for attenuating switching harmonics in a flexible, while yet not cost burdensome, approach. A direct impedance synthesis method has also been proposed for the ATF to better enforce its active switching harmonic bypassing ability. Compared with conventional schemes for controlling active power filters, the proposed method is more readily implemented, since it requires neither current reference generation nor high-bandwidth current control loop. Moreover, the use of a series LC filter at its ac side helps the ATF to reduce its inverter voltage and power ratings. Compensated frequency range of the ATF can hence be enlarged by using a comparably higher switching frequency and a proper step-by-step design procedure to be presented in this paper. Simulation and experimental results have confirmed the design procedures, and hence expected performance of the ATF. [ABSTRACT FROM PUBLISHER]

This paper presents an improved direct torque control (DTC) method for an asymmetrical six-phase induction motor using a two-level six-phase inverter. As is well known, a simple extension of three-phase DTC technique to an asymmetrical six-phase motor, using large vectors only, introduces significant current harmonics of the order 6 n±1 (n = 1, 3, 5,…), which are mapped into the nonflux/torque producing (xy) plane. These harmonics cause only losses in the motor winding as they do not take part in torque production. Hence, a number of different improved DTC techniques have been developed in the past for multiphase motor drives. The paper takes one such DTC method as the starting point and improves it further by using the concept of virtual voltage vectors. Developed vector selection algorithm, based on two virtual voltage vectors, requires the information on position of the flux in the auxiliary (xy) subspace and provides stator current quality commensurate with the currently available best DTC algorithm for six-phase drives. However, use of two virtual voltage vectors enables a substantial reduction of the torque ripple, which is achieved by means of a five-level torque comparator. Extensive experimentation is performed and it is shown that the reduction of the current harmonics is in essence almost the same as in another recently developed DTC scheme, based on the use of a single virtual voltage vector. However, the achieved torque ripple reduction, which is verified experimentally, makes the scheme superior when compared to the existing approaches. At the same time, developed scheme retains qualities of conventional DTC schemes, such as simple structure and fast response. Its additional beneficial feature is the easiness of implementation. [ABSTRACT FROM PUBLISHER]

A multilevel dodecagonal voltage space vector generation scheme for variable-speed drive applications with single-dc-link operation requires a large value of capacitance for cascaded H-bridge (CHB) filters, when operated at lower speeds. In existing schemes, the multilevel dodecagonal structure is obtained by cascading a flying capacitor inverter with a CHB. In this paper, a new scheme has been proposed to minimize the capacitance requirement for full speed operation by creating vector redundancies using modular and equal voltage CHBs. Also, an algorithm has been developed to optimize the selection of vector redundancies among the CHBs in order to minimize the voltage ripple of the floating capacitors. The proposed algorithm considers instantaneous capacitor voltages and phase currents for optimal selection of vector redundancies. A mathematical model for capacitor voltage deviation is presented, and the effectiveness of the proposed algorithm is verified in both the simulation and the experiment. [ABSTRACT FROM AUTHOR]

This paper presents the circuit design and magnetic integration of push–pull class-E inverters for wireless power transfer (WPT) up to megahertz. The design criterion for achieving zero-voltage switching (ZVS) of a class-E inverter with coupled windings is derived mathematically. The approaches of magnetic integration for push–pull class-E inverters are analyzed and compared. Then, a new magnetic structure with hybrid magnetic materials is proposed to build the integrated inductors with either coupled windings or uncoupled windings. A 3-MHz WPT system is built to verify the analysis. The detailed comparison of the class-E inverters with magnetic integration is presented in terms of switch voltage, efficiency, harmonic currents, and thermal distribution. In the optimized design example, the switches keep ZVS over the entire load range without using any closed-loop control. The system efficiency reaches 87.1% at 350-W output power. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to derive a pulsewidth modulation (PWM) technique for the generalized multi-phase drive. This novel approach is called a phase traversing principle. The given phase traversing principle is applied to the proposed PWM technique for five-phase open-end winding induction motor drive fed from a single dc source. The proposed PWM technique has the benefits of phase clamping, symmetrical operation of inverters, and common-mode current (CMC) elimination. Thus, it reduces the switching losses and also minimizes the issue of the CMC. The symmetrical operation of dual inverters further helps in the even distribution of losses. Also, the proposed PWM technique gives a good harmonic performance. The performance of the proposed PWM technique is analyzed using the switching loss function and harmonic flux trajectory methods. The first analysis gives justification of the reduced switching losses. While the second analysis gives the deviations in the motor flux with respect to variation in. modulation indices The proposed PWM technique is verified with both simulation and hardware results. [ABSTRACT FROM AUTHOR]

This paper proposes a new pulse amplitude width modulation (PAWM) procedure for cascaded H-bridge multilevel inverters fed by dc voltage sources with unequal amplitudes. With proposed procedure, the generated output voltage is obtained modulating a sinusoidal reference signal at the desired fundamental frequency with equally spaced switching angles. It has been analytically demonstrated that, under these assumptions, all harmonics except those of order $n=2kl\pm 1$ , $k=1,2,\ldots$ are deleted from the output voltage waveform. After a detailed description of the method and a comparative analysis with others existing in the literature, its harmonics elimination capability has been experimentally verified with 5-, 7-, 9-, and 11-level cascaded H-bridge inverters, moreover, it has been mathematically demonstrated that it reduces total harmonic distortion below 5% with a 17-level inverter and it is capable of eliminating the first 49 harmonics considered by standards with a 27-level inverter. [ABSTRACT FROM AUTHOR]

In this paper, the zero sequence circulating current in open winding permanent magnet synchronous machine (OW-PMSM) drives with common dc bus is systematically analyzed for the first time. It is revealed that the zero sequence circulating current is affected by zero sequence back-electromotive force, cross coupling voltages in zero sequence from the machine side, pulse-width modulation induced zero sequence voltage, and inverter nonlinearity from the inverter side. Particularly, the influences from the cross coupling voltages in zero sequence and parasitic effect of inverter nonlinearity are investigated for the first time in this paper. Then, the synthetic model of the equivalent zero sequence circuit is proposed as well. Each cause is studied independently via analytical modeling, finite element analysis, and experiments. Meanwhile, to tackle this issue, the relevant suppression strategy using frequency adaptive proportional resonant controller is presented and tested on the 3 kW OW-PMSM platform. [ABSTRACT FROM AUTHOR]

In this paper, a new space vector pulse width modulation method to extend the linear modulation range of a cascaded five level inverter topology with a single dc supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0.577 to 0.637 V\text{dc} without increasing the dc bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0–50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The five-level topology presented in this paper is realized by cascading a two-level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady-state and dynamic operating conditions are presented in this paper. [ABSTRACT FROM AUTHOR]

The degradation in power quality causes adverse economical impact on the utilities and customers. Harmonics in current and voltage are one of the most commonly known power quality issues and are solved by the use of a hybrid series active power filter (HSAPF). In this paper, a new controller design using sliding-mode controller-2 is proposed to make the HSAPF more robust and stable. An accurate averaged model of a three-phase HSAPF is also derived in this paper. The design concept of the robust HSAPF has been verified through simulation and experimental studies, and the results obtained are discussed. [ABSTRACT FROM AUTHOR]

This paper presents a method for generating a multilevel dodecagonal voltage space vector structure using a single dc source for induction motor drives. Multilevel dodecagonal structure combines the advantages of both multilevel and dodecagonal structures, and hence, generates low dv/dt phase voltage along with the elimination of fifth- and seventh-order harmonics over the entire modulation range. This eliminates low-order harmonic currents and prevents the generation of sixth-order torque ripple in the motor. The topology used requires only one dc source making four-quadrant operation of the drive system simpler compared to previously proposed multilevel topologies generating dodecagonal space vector structures. The topology used consists of a three-level flying capacitor (FC) inverter cascaded with a capacitor fed H-bridge. The FC inverter operates at a lower switching frequency and the low-order harmonics are eliminated by the switching action of the cascaded H-bridge inverter. The capacitors in the cascaded H-bridge modules are maintained at a substantially smaller voltage compared to the dc-link voltage and are inherently balanced during the pulsewidth modulation operation. This results in low switching loss, in the FC inverter as well as in the cascaded H-bridge inverter. Experimental results are included to validate the operation of the topology and modulation scheme presented in this paper. [ABSTRACT FROM AUTHOR]

In this paper, the near-state pulsewidth modulation (NSPWM), adapted to be implemented in dual-voltage-source inverter (VSI) fed open-end motor, is proposed with the aim of mitigating low-order harmonics (which lead to current total harmonic distortion (THD) minimization). The following two proposed methods are studied in detail: 1) fixing phase angle displacement (PAD) between two VSIs to 120° while adjusting the modulation index (MI); and 2) fixing MI to the predetermined value (wherein low-order harmonics are highly mitigated) while adjusting PAD. Furthermore, the proposed approaches enhance efficiency by limiting the number of commutations within the switching interval. The paper also presents the mathematical approaches to accurately determine low-order harmonic components and switching losses for dual-VSI structure. The experimental setup, including dual-VSI and open-end induction motor, is assembled in the laboratory to evaluate performance of the proposed method. Finally, the simulation results, carried out in the MATLAB/Simulink environment, are found to be in close agreement with experimental data. [ABSTRACT FROM AUTHOR]

The paper proposes a method of active switching harmonics current reduction in the dc-link capacitor of a two-level, three-phase, back-to-back converter. Based on the derived analytical solution for switching harmonic currents in the dc-link, it is shown that by specific control over the pulsewidth-modulated (PWM) carriers’ phase angles, the targeted harmonics of the rectifier and the inverter can be synchronized in phase such that their cancellation occurs in the dc-link capacitor. This synchronization is provided by harmonic phase feedback control. A three-step procedure to implement the method is detailed in the paper. The effectiveness of the proposed approach is verified experimentally. [ABSTRACT FROM AUTHOR]

This paper proposes a new topological configuration for a unified power quality conditioner (UPQC). Generally, the power structure of the three-phase three-wire UPQC consists of two back-to-back connected six-switch inverters. For this configuration, out of 12 switches, six of the series inverter switches will be underutilized most of the time. To improve the semiconductor utilization and consequently to reduce the total switch count, this paper proposes a new reduced switch topology for the UPQC. The proposed topology is realized using only ten switches and retains all the performance merits of the 12-switch UPQC while minimizing its underutilization without increasing the switch VA rating. The paper provides a detailed analytical study and evaluation by comparing the proposed topology with the twelve- and nine-switch-based UPQC system configurations. The feasibility of the proposed topology is validated through experimental investigation. [ABSTRACT FROM AUTHOR]

Due to the pulsating power at the inverter output terminals, the passive storage elements of the boost stage of the current-fed switched inverter (CFSI) contain a power frequency harmonic component (100 Hz), apart from dc and switching frequency components. In prior designs, the second harmonic component is suppressed by increasing the size of the input filter inductor and capacitor or by using additional circuits. This paper presents a complete characterization of a control-based approach to suppress the power frequency harmonic component in the input inductor current of a CFSI. It also presents a comprehensive characterization of the harmonic power redistribution. Using the proposed approach, it is demonstrated that the inductor value of a CFSI is reduced by 61% for the same peak-to-peak ripple. This leads to an improvement in the conversion ratio, efficiency, and power density of the overall converter. A SiC MOSFET-based CFSI with 75-kHz switching frequency is used to verify the proposed design philosophy. [ABSTRACT FROM AUTHOR]

The leakage current originated from the fluctuations of the common-mode voltage (CMV) is an issue in a transformerless grid-connected photovoltaic system. In this paper, a modified space vector modulation based on the Fourier transform analysis is proposed to reduce the leakage current in a three-phase quasi-Z-source inverter (qZSI). The CMV harmonic content in a qZSI contains low- and high-frequency harmonics that cause safety and electromagnetic interference problems, respectively. By implementing the proposed modulation in a three-phase qZSI, the low-frequency harmonics of the CMV are mainly reduced. The distribution of the high-frequency harmonics is also modified in a way they can be simply filtered. Passive filtering in a qZSI using other modulation techniques is less effective than using this method. Applying the proposed modulation in the presence of a high-frequency inductive-capacitive filter results in the strong suppression of both high- and low-frequency harmonics (more than 90% in the investigated case). A reduced-voltage prototype is designed to evaluate the modulation method. The experimental results from this prototype verify the accuracy of the proposed technique. [ABSTRACT FROM AUTHOR]

This paper proposes a high-frequency dc–dc converter with a synchronous rectifier (SR), which is suitable for the low-voltage output application. The proposed topology consisting of a Class Φ2 inverter and a synchronous Class E current-driven rectifier features low switch voltage stress, fast transient response, and high efficiency. First, the analysis and design method of the converter are presented. Concerning the coupling of amplitude and phase of the fundamental voltage and current in the rectifier stage, the duty cycle of the switch is considered in the proposed design method. For the design of the inverter stage, the impedance of the resonant tank across the main mosfet is utilized in the design process. Second, a self-oscillating resonant driver with dc bias voltage is proposed for the SR switch and features low component count and low driving power loss. A prototype with 12 V input and 5 V/10 W output was built to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

Conventional two-level as well as multilevel voltage-source-inverter topologies with a hexagonal voltage-space vector structure generate low-order harmonics in the machine terminal voltages when operated beyond the linear modulation range in variable speed drive application. Progressing from hexagonal to a higher sided polygonal voltage-space-vector structure (VSVS) suppresses significant low-order harmonics throughout the modulation range. In addition, the linear modulation range will also be enhanced very near to the base speed. In this paper, for the first time, the generation of a multilevel 24-sided VSVS using a single dc source for induction-motor drives is proposed. A cascaded topology with a dc-source-fed flying-capacitor inverter and two low-voltage capacitor-fed H-bridge cells forms the power circuit. The features and advantages of the proposed scheme are validated through experimental results and discussions. [ABSTRACT FROM AUTHOR]

Most photovoltaic (PV) systems are composed of series and parallel inverters. The electromagnetic interference (EMI) mainly comes from the off–on of inverter switches with pulsewidth modulation (PWM). The output EMI peaks of PV systems would increase markedly due to the interference superposition effect caused by parallel inverters, whose carrier initial phases are in phase or close to each other. In this paper, an auto-screening carrier phase-shift scheme is proposed to weaken the superposition effect of EMI peaks and to get the result of reverse offset at its best. In a PV system, through voltage detections and spectrum estimations of each inverter with a series of phase-shift carriers, a best carrier phase of each inverter is obtained automatically to minimize EMI peaks of the PV system. In order to avoid the conflict that the screening processes of two or more inverters are underway at the same time, a specific frequency signal is output temporarily as an occupancy mark in one of the inverters. The feasibility and effectiveness of the proposed scheme are verified by experimental results in a PV system composed of four parallel single-phase inverters. [ABSTRACT FROM AUTHOR]

In this paper, performances on two kinds of aggregated flyback microinverters are compared in aspect of harmonic resonances, which are controlled by current feedback control and peak current control. Based on the Norton models of flyback microinverters obtained by a small-signal modeling approach, potential harmonic resonances with the grid are analyzed. Following that, an impedance-based stability criterion is proposed, where the resonance frequency can be calculated and predicted based on the derived Norton models and the system admittance matrix of aggregated microinverters. After comprehensive analysis and comparisons, it is found that the peak-current-control-based flyback microinverters has better performance on damping the harmonic resonances than the current feedback controlled one. Simulations and experiments are carried out for verifying the effectiveness of the presented models and the correctness of the analysis results. [ABSTRACT FROM AUTHOR]

The three-phase four-wire inverter with split dc-link capacitors can supply unbalanced loads. For the purpose of reducing the filter inductors, a neutral inductor could be introduced into the neutral line. This paper analyzes the operation principle of the three-phase four-wire inverter with split dc-link capacitors when a neutral inductor is introduced. It is illustrated that the neutral inductor can reduce the zero-sequence switching harmonics in the voltages between the phase-leg midpoints and the output neutral point, thus the filter inductors can be reduced. The optimized design of the neutral inductor and filter inductors is proposed with the considerations of the inductor current ripple, the ability of supplying unbalanced loads, and the total energy stored in the inductors. The equivalent circuits of the three-phase four-wire inverter with split dc-link capacitors and neutral inductor is derived in the α–β–0 frame, and the zero-axis voltage regulator is modified to suppress the third-order harmonic in the zero-sequence current caused by the deadtime of the drive signals for the power switches. Finally, the experimental results from a 9-kW prototype are provided to prove the effectiveness of the proposed optimized design of the neutral inductor and filter inductors and the control strategy of the inverter. [ABSTRACT FROM AUTHOR]

In this paper, a modified selective harmonic mitigation pulse amplitude modulation (SHM-PAM) is presented to be capable of canceling all triplen harmonic orders and suitable for single-phase application of five-level type of voltage source inverters. To this end, a new constraint is established for the two switching angles (α1, α2) to derive the new formula for the harmonics’ amplitude, which results in self-elimination of all triplen harmonics (e.g., 3rd, 9th, 15th, …). The fifth and seventh harmonic orders are mitigated through normal operation of the proposed SHM-PAM technique. It is also shown that the proposed technique is extendable to other multilevel voltage waveforms and a flowchart of self-elimination of all triplen harmonics has been presented. Mathematical analysis supported by experimental investigations show the desired performance of the proposed SHM-PAM algorithm on a two-cell single-phase cascaded H-bridge inverter as a typical five-level configuration in dealing with linear and nonlinear loads. Then, it is demonstrated that the maximum number of harmonic orders would be controlled with the minimum number of available angles in a low switching frequency voltage waveform. [ABSTRACT FROM AUTHOR]

In this paper, a novel space vector modulation (SVM) strategy is proposed and designed for dual three-phase three-level motor drives based on vector space decomposition (VSD), which could be applied for high-power and high-reliability applications. The key of the proposed method is to design two decoupled groups of voltage vector candidates for synthesis on α − β subspace and x − y subspace, respectively. The two decoupled groups of voltage vectors will synthesize respective voltage references on α − β subspace and x − y subspace, while having no impact on each other. The redundant small voltage vectors and zero-sequence voltage vectors are utilized to mitigate voltage oscillation in midpoint of dc link and suppress zero-sequence current component for dual three-phase windings with a common neutral. For comparison, another VSD-SVM strategy is designed based on traditional solution, which cannot offer closed-loop control on x − y subspace. Both simulation and experiments have been given to verify that the proposed decoupled VSD-SVM can suppress harmonic components on x − y subspace besides tracking torque components on α − β subspace. Furthermore, the harmonic performance of the proposed decoupled VSD-SVM has been compared with the traditional VSD-SVM strategy and the carrier disposition based pulsewidth modulation. [ABSTRACT FROM AUTHOR]

This paper presents a new least-mean-square (LMS) algorithm based deadtime compensation method to suppress the current distortion in permanent-magnet synchronous motor (PMSM) field-oriented control (FOC) drives. Compared to conventional average value compensations, the proposed method is robust to switching device parameter variations thanks to the online adaptation capability of the LMS algorithm. Similarly, the disturbance observer compensators are also immune to switching device parameter variations; however, varying motor parameters degrade their compensation performance. Without prior knowledge of switching device or motor parameters, the proposed method can directly reduce the deadtime current harmonics by generating compensation voltage references. In addition, the proposed method is easy to implement since it does not require voltage errors estimation or current harmonics extraction, which are necessary for disturbance observer and adaptive filter based methods. The proposed method is tested on a 2.5-kW voltage-source inverter PMSM drive controlled by an FOC algorithm. Its effectiveness is validated by both experimental results and spectrum analysis. [ABSTRACT FROM AUTHOR]

This paper proposes new angles constraint for selective harmonic elimination-pulsewidth modulation (SHE)-PWM utilized in single-phase inverter applications. The proposed angles constraint naturally eliminates all triplen harmonics, whereas they conventionally appeared in all single-phase output voltages. The harmonic amplitude formula is developed based on the obtained angles constraint, and then modified single-phase SHE equations are defined to eliminate only specified low nontriplen harmonics. Therefore, more harmonics would be eliminated with the same switching frequency in modified SHE-PWM. Five-level voltage waveform has been opted to implement the introduced method, but it can be applied on all multilevel voltage waveforms such as seven-level with even number of angles. Unlike the conventional SHE technique, THD is analyzable in modified SHE to find optimum values for switching angles in order to control noneliminated harmonic amplitudes and minimize THD. Moreover, the cancellation of triplen harmonics empowers a single-phase inverter to supply nonlinear loads beside linear ones. Some experimental tests are accomplished using a single-phase five-level modified packed U-cell (MPUC) inverter. Results are discussed to prove the excellent performance of a single-phase MPUC inverter under both normal and harmonic loads and accurate elimination of determined triplen and nontriplen harmonics by applying the presented angles constraint. [ABSTRACT FROM AUTHOR]

In order to prevent the power switching devices (e.g., an insulated-gate bipolar transistor, IGBT) from shoot-through in voltage-source converters during a switching period, the dead time is added either in the hardware driver circuits of the IGBTs or implemented in software in pulse width modulation (PWM) schemes. Both solutions will contribute to a degradation of the injected current quality. As a consequence, the harmonics induced by the dead time (referred to as “dead-time harmonics” hereafter) have to be compensated in order to achieve a satisfactory current quality, as required by standards. In this paper, the emission mechanism of dead-time harmonics in single-phase PWM inverters is, thus, presented considering the modulation schemes in detail. More importantly, a repetitive controller has been adopted to eliminate the dead-time effect in single-phase grid-connected PWM converters. The repetitive controller has been plugged into a proportional-resonant-based fundamental-frequency current controller so as to mitigate the dead-time harmonics and also to maintain the control of the fundamental-frequency grid current in terms of dynamics. Simulations and experiments are provided, which confirm that the repetitive controller can effectively compensate the dead-time harmonics and other low-order distortions, and also, it is a simple method without hardware modifications. [ABSTRACT FROM AUTHOR]

High-step-up dc/dc converters are widely required in grid-connected applications with renewable energy sources. An extremely high-ratio step-up nonisolated dc/dc converter, in the form of a harmonics-boosted resonant converter, is proposed in this paper. This proposed converter consists of a high-frequency dc/ac inverter stage that is followed by a passive ac/dc rectifier stage connected in cascade. Conventionally, such a dc/ac inverter is designed to output a pure sinusoidal ac voltage with an amplitude several times the amplitude of the input voltage. However, for the proposed converter, the harmonics-boosted inverter stage is designed to contain selected voltage harmonics that significantly boost the amplitude of its output voltage. This greatly increases the overall gain of the converter. The adopted ac/dc stage is a diode-capacitor rectifier, which is of high efficiency and easily extendable to increase the voltage gain. Importantly, the proposed converter involves only one active switch. With only one active switch, the driver's loss is minimized and the converter's control is simplified. Zero-voltage switching is applied to reduce the switching loss, which also allows the converter to operate efficiently at high frequency, and thus can be designed for high power density. The optimal design of the two converter stages and their combined voltage gain is investigated and reported. Besides, a design guideline of the proposed converter is provided. A prototype of a 57-time harmonics-boosted resonant converter with 3.3 V input voltage, 500 kHz switching frequency, and 21 W output power, is built. The experimental result shows that the achieved converter's efficiency is as high as 88.6%. [ABSTRACT FROM AUTHOR]

Microinverters operating into the single-phase grid from new energy source with low-voltage output face the challenges of efficiency bottleneck and twice-line-frequency variation. This paper proposed a multilevel inverter based on bridge modular switched-capacitor (BMSC) circuits with its superiority in conversion efficiency and power density. The topology is composed of dc–dc and dc–ac stages with independent control for each stage, aiming to improve system stability and simplify the control method. The BMSC dc–dc stage, which can be expanded to synthesize more levels, not only features multilevel voltage gain but also partially replaces the original bulk input capacitor and functions as an active energy buffer to enhance power-decoupling ability between dc and ac sides. In dc–ac stage, the control strategy of optimized unipolar frequency doubling sine-wave pulse width modulation is proposed to improve the quality of output waveform. Meanwhile, the multilevel voltage phase has been optimized to further reduce the power loss. Finally, a prototype has been built and tested. Associated with the simulation, the experimental results validate the practicability of these analyses. [ABSTRACT FROM PUBLISHER]

This paper introduces a new analysis approach to modeling resonant converters that can be used to determine closed-form expressions for the exact resonant network waveforms. This approach, based on superposition of step responses to inverter and rectifier imposed steps, can easily be applied to resonant converters with high-order resonant networks, multiple inverters, and/or rectifiers. The usefulness of the proposed analysis approach is demonstrated first by applying it to a series-resonant converter, wherein it is used to determine accurate closed-form expressions for its tank current in different operating modes. These expressions are utilized to draw insights that help identify the converter's operating mode, and determine associated expressions for its output voltage and the switching frequency required to achieve a desired output power. The proposed approach is also applied to the multi-inverter multi-element impedance control network (ICN) resonant converter, wherein it is used to derive closed-form expressions for the converter's currents. These expressions are utilized to evaluate the behavior and optimize the design of an ICN resonant converter. A prototype 200-W 500-kHz ICN resonant converter optimized using the proposed approach is used to validate the modeling results. It is shown that there is an excellent agreement between the experimental and modeled waveforms during steady-state operation as well as during startup transients. [ABSTRACT FROM AUTHOR]

This paper proposes a new fault-tolerant strategy to revamp performance of three-phase multilevel converters with a single faulty switch. The proposed fault-tolerant strategy is based on the application of a modified selective harmonic elimination (SHE) technique in conjunction with the fundamental phase-shift compensation method. The proposed fault-tolerant strategy makes the most use of the converter capacity in the faulty condition, generates balanced line voltages, and eliminates a wide range of lower order harmonics to limit the total harmonic distribution of the converter voltages in the faulty condition. In this paper, first, a brief background about cascaded H-bridge multilevel converters and SHE technique is provided. Then, the proposed fault-tolerant strategy and the modified SHE technique are presented. Finally, several experimental results are provided to validate the operation of the proposed strategy. [ABSTRACT FROM PUBLISHER]

A virtual space vector modulation technique reducing both magnitude and third-order harmonic component of the common-mode voltage (CMV) in a two-level voltage-source inverter (VSI) is proposed in this paper. The presented method employs a set of virtual space vectors constructed from original stationary space vectors to conduct modulation. Since the created virtual vectors have the lowest instantaneous and zero average CMVs, both the magnitude and third-order harmonic component of the generated CMV are reduced, contributing to better overall CMV performance and common-mode filter design in VSI applications. Three variants of the proposed modulation method using different virtual space vector combinations are presented. The concept of the virtual space vector modulation technique demonstrated with two-level inverter in this paper can also be extended to multilevel inverters. Simulation and experimental results, as well as comparisons with existing methods are provided to verify the proposed technique. [ABSTRACT FROM AUTHOR]

A merit of the interleaving reducing the switching harmonics allows for the reduction of the filter inductance. However, in the case of direct parallel voltage source inverters (VSIs), a severe circulating current occurs. To suppress the high frequency circulating current, coupled inductors (CIs) for the high impedance is inserted. However, the employed CIs induce a positive- or negative-sequence circulating current (i.e., a cross current) besides the zero-sequence circulating current already mentioned in the other papers. Due to different impedances developed by the current characteristics and the cross current in the CIs, VSIs becomes unstable when the resonant controllers are applied for the harmonic compensation such as 5, and 7th harmonics. In this paper, the cross currents and the impedances of CIs varying with the current characteristics are mathematically analyzed, and a novel current controller is proposed to solve this stability problem. The experimental results validate the proposed control scheme. [ABSTRACT FROM PUBLISHER]

This paper presents a new multilevel selective harmonic elimination pulse-width modulation (MSHE-PWM) technique for transformerless static synchronous compensator (STATCOM) system employing cascaded H-bridge inverter (CHI) configuration. The proposed MSHE-PWM method optimizes both the dc-voltage levels and the switching angles, enabling more harmonics to be eliminated without affecting the structure of the inverter circuit. The method provides constant switching angles and linear pattern of dc-voltage levels over the modulation index range. This in turns eliminates the tedious steps required for manipulating the offline calculated switching angles and therefore, easing the implementation of the MSHE-PWM for dynamic systems. Although the method relies on the availability of the variable dc-voltage levels which can be obtained by various topologies, however, the rapid growth and development in the field of power semiconductor devices led to produce high-efficiency dc-dc converters with a relatively high-voltage capacity and for simplicity, a buck dc-dc converter is considered in this paper. Current and voltage closed loop controllers are implemented for both the STATCOM and the buck converter to meet the reactive power demand at different loading conditions. The technique is further compared with an equivalent conventional carrier-based pulse-width modulation to illustrate its enhanced characteristics. The effectiveness and the theoretical analysis of the proposed approach are verified through both simulation and experimental studies. [ABSTRACT FROM AUTHOR]

This paper proposes an analytical procedure for computation of all pairs of valid switching angles used in pattern generation in five-level H-bridge cascaded inverters. The proposed procedure eliminates harmonic components from inverter output voltage and, for each harmonic, returns the exact boundaries of all valid modulation index intervals. Due to its simple mathematical formulation, it can be easily implemented in real time using a digital signal processor or a field-programmable gate array. In this paper, after a detailed description of the method, simulation and experimental results demonstrate the high quality of achievable results. [ABSTRACT FROM PUBLISHER]

In this paper, a real-time implementation of selective harmonic elimination pulsewidth modulation (SHEPWM) using generalized Hopfield neural network (GHNN) as applied to the single-phase inverter is designed and discussed. Finding the location of the switching instants in the case of SHEPWM involves the solution of a set of nonlinear algebraic transcendental equations. The problem is redrafted as an optimization problem, and it is solved by using GHNN. Though, in principle, the $n$ number of harmonics can be eliminated using the presented methodology, this paper tries for the case of the elimination of the 5th-, 7th-, 11th-, and 13th-order harmonics while retaining the desired fundamental. An energy function is formulated for this problem and the set of ordinary differential equations (ODEs) describing the behavior of GHNN is obtained. A program in KEIL C was developed to solve these systems of ODEs by the Runge–Kutta fourth-order method to give the switching instants for continuously varying modulation indexes $(M)$. A MATLAB simulation was carried out, and an experimental setup was also constructed in order to validate the simulated results. The fast Fourier transform analysis of the simulated output voltage waveform and the experimental output voltage waveform confirms the effectiveness of the proposed method. Hence, the proposed method proves that it is much applicable in the industrial applications by virtue of its suitability in real-time applications. [ABSTRACT FROM PUBLISHER]

Three optimized pulse-width modulated (PWM) techniques for the overmodulation region of two-level inverter-fed ac drives are introduced and investigated from the harmonic loss minimization point of view. The optimization is elaborated for the lowest loss-factor, which is proportional to the square of the root mean square value of current harmonics. The loss-factors are computed for different switching numbers as the function of the motor fundamental voltage. It is shown that, with respect to the motor heating and torque ripples, the acceptable drive condition can be guaranteed by a relatively low value of an inverter switching frequency up to 96%–97% of maximal possible motor voltage. Furthermore, it is shown that the so-called three-vector methods have considerably better performance in the lower part of the overmodulation region than the so-called two-vector method for the same number of switching. The performance of the techniques is compared with other existing PWM techniques. This paper discusses the implementation details of the proposed optimal PWM techniques. The theoretical results are verified by experimental and simulation tests. [ABSTRACT FROM AUTHOR]

An observer-based control (OBC) strategy for dual-active-bridge converters is proposed in this paper. The target is not only to handle the active power transferring between two terminals, but also to regulate the phase difference between the primary voltage and current around specific minimum value. The value is chosen to reduce the conduction loss in the system. A reduced-order observer is developed to estimate the direct and quadrature components of the transmission current for use in a decoupled current control system. Since the dc terminal current is the only input of the observer, a low sampling frequency is enough to ensure an acceptable precision. Experiment results show that the proposed OBC strategy can help improve the dynamic performance compared with that when using a single loop voltage mode system. Furthermore, at the high power range, the efficiency obtained when employing the OBC method is improved by up to 7.2%. [ABSTRACT FROM AUTHOR]

Impedance network inverters are the best alternatives for voltage-source and current-source inverters. The boosting capability and the shoot-through solution of such converters make them excellent solutions for various applications. Nevertheless, hard switching forces the converter to operate in low switching frequency, which results in a bulky impedance network. Moreover, the coupling between the shoot-through duty cycle and the inverter modulation index makes a tradeoff between the voltage gain and the modulation index (output voltage harmonics). This paper presents a novel dual switching frequency modulation to mitigate the switching losses of the converter, which results in a more compact impedance network. The proposed method combines a high-frequency pulse width modulation with a low-frequency sinusoidal pulse width modulation (SPWM). Therefore, the switching losses decrease considerably with respect to the conventional simple boost modulation. In addition, the impedance network design frequency remains high, and the network size decreases obviously. The proposed approach removes the interdependence between the shoot-through duty cycle and the inverter modulation index. A comparison between the proposed method and the conventional simple boost method is performed to show its advantages over the conventional method. Finally, experimental results are presented to validate the performance of the proposed method. [ABSTRACT FROM PUBLISHER]

Shunt active power filter (SAPF) is the preeminent solution against nonlinear loads, current harmonics, and power quality problems. APF topologies for harmonic compensation use numerous high-power rating components and are therefore disadvantageous. Hybrid topologies combining low-power rating APF with passive filters are used to reduce the power rating of voltage source inverter (VSI). Hybrid APF topologies for high-power rating systems use a transformer with large numbers of passive components. In this paper, a novel four-switch two-leg VSI topology for a three-phase SAPF is proposed for reducing the system cost and size. The proposed topology comprises a two-arm bridge structure, four switches, coupling inductors, and sets of LC PFs. The third leg of the three-phase VSI is removed by eliminating the set of power switching devices, thereby directly connecting the phase with the negative terminals of the dc-link capacitor. The proposed topology enhances the harmonic compensation capability and provides complete reactive power compensation compared with conventional APF topologies. The new experimental prototype is tested in the laboratory to verify the results in terms of total harmonic distortion, balanced supply current, and harmonic compensation, following the IEEE-519 standard. [ABSTRACT FROM AUTHOR]

This paper discusses the use of a cascaded multilevel converter for flexible power conditioning in smart-grid applications. The main feature of the proposed scheme is the use of independent dc links with reduced voltages, which makes such a topology an ideal candidate for medium- and high-power applications with increased reliability. The developed control strategy regulates independent dc-link voltages in each H-bridge cell, and allows the selective and flexible compensation of disturbing currents under a variety of voltage conditions without requiring any reference frame transformation. The selective control strategies are based on the decompositions proposed in the conservative power theory, which result in several current-related terms associated with specific load characteristics. These current components are independent of each other and may be used to define different compensation strategies, which can be selective in minimizing particular effects of disturbing loads. Experimental results are provided to validate the possibilities and performance of the proposed control strategies, considering ideal and deteriorated voltage conditions. [ABSTRACT FROM PUBLISHER]

In this paper, a dc-link voltage protection (DCVP) control method is proposed to address the dc-link overvoltage issue due to power backfeeding in a parallel uninterruptible power supply (UPS) system. The proposed control method is able to protect the inverter against the excessive dc-link voltage, which increases the system reliability and robustness. Moreover, a current sharing control strategy is proposed by online regulating the virtual resistance of each UPS module. The proposed current sharing control strategy is able to address the circulating fundamental and harmonic currents caused by the line impedance mismatching or power backfeeding issue in the UPS system. In addition, an improved consensus-based distributed controller is proposed to alleviate the overshoot issue during the transient process in voltage amplitude and frequency restoration. Finally, the feasibility of the proposed methods is verified by experimental results from the parallel UPS prototypes. [ABSTRACT FROM PUBLISHER]