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Microinverters for grid-connected photovoltaic (PV) power conversion systems often require voltage boost due to the low dc voltage of the PV panels. A high-frequency (HF) transformer-isolated differential-mode Ćuk inverter (DMCI) is an attractive topology due to its inherent voltage boost capability and high power density. One of the significant operational issue of the DMCI addressed in this paper is the presence of lower order harmonic distortion in the injected grid current. It is shown that lower order odd and even harmonic voltages are generated with this topology. This problem is accentuated due to the low damping offered by the grid to harmonic voltages. A systematic low-complexity control design is proposed to address this issue. It is shown experimentally that the DMCI operates stably with effective attenuation of the lower order harmonics using the proposed design. Practical operational issues of the DMCI with fast switching GaN field-effect transistor (FET) devices are analyzed and solutions are proposed. It is shown that there can be significant HF noise generation in the DMCI with a frequency range higher than the switching frequency. Practical solutions for resolving HF issues using a combination of circuit layout design and additional passive components are proposed and validated. All of the experimental results are demonstrated on a 500-W GaN-FET-based microinverter prototype. [ABSTRACT FROM PUBLISHER]

Traditional model predictive control cost functions, when utilizing long prediction horizons ( $N\geq 10$) in power inverter applications, have demonstrated harmonic performances approaching that of schemes based on offline-generated optimal pulse patterns. However, long prediction horizons often prohibitively increase computational load. A different approach to maximizing harmonic performance is taken in this paper. It is shown that shaping the output voltage spectra using a simple feedback mechanism can significantly reduce the length of the required prediction horizon, facilitating a feasible computational load. When a short-horizon cost function is augmented by the feedback mechanism an excellent tradeoff between harmonic performance and switching loss is achieved, even with a prediction horizon of one. It is also shown that the feedback mechanism can be used to improve input reference tracking. Experimental verification of the proposed modulator is performed on a two-level three-phase inverter. [ABSTRACT FROM AUTHOR]

In voltage-source inverters, it is necessary to add the dead time between gating signals of the upper and lower switches to prevent short circuit in a phase leg. But in current-source inverters (CSI), due to the large series inductor in dc link, it is necessary to add the overlap time in gating signals of switches during the commutation process for avoiding voltage spikes generated by the intermittent dc current. However, the overlap time will cause negative influence in the output current waveform. In this paper, the current commutation process of CSI within a carrier period is investigated, which shows that the overlap time can cause output-current-vector errors. The output-current-vector errors are then analyzed, which are equivalent to a superposition and introducing additional low-order harmonics in the output current waveform. The relationship between harmonic distortion and the overlap time is derived. An overlap-time compensation method is then proposed, which compensates the dwell time of vectors according to the relations of voltages at the ac side of the inverter. The proposed overlap-time compensation method can effectively decrease the current harmonics introduced by the overlap time and improve the output current of the inverter. Simulation and experimental results are finally provided to verify the feasibility and validity of the proposed method. [ABSTRACT FROM PUBLISHER]

As is well known, the additional low-order harmonic currents and the huge computation amount of the cost function value with all available control sets are the two special issues of finite-control-set model predictive current control (FCS-MPCC) for multiphase inverters. Thus, this paper proposes a FCS-MPCC scheme with duty-ratio optimization for five-phase inverters. First, a group of the reconstructed virtual voltage vectors (V3) with low-order harmonic elimination is defined and employed as the control sets in FCS-MPCC scheme. Thus, it leads to no requirement for harmonic items and weighting factors existing in the cost function. Then, a combination of zero vectors and the selected V3 during each control horizon is adopted to rearrange the pulse sequence, which can realize constant switching frequency. In addition, the durations of the selected V3 and zero vectors during each control horizon are also estimated to minimize the steady-state current ripples in different subspaces based on the cost function optimization. Finally, a comparison of the proposed V3-FCS-MPCC scheme and the other FCS-MPCCs are presented in simulation and experimental test. Simulation and experimental results verify that the proposed V3-FCS-MPCC scheme can remain the simplified structure, fast dynamic performance, constant switching frequency, and achieve minimum current ripples in different subspaces. [ABSTRACT FROM PUBLISHER]

Conventional voltage-source inverters used for induction motor drives generate a hexagonal space vector structure. In the overmodulation range, the hexagonal space vector structure generates low-order harmonics in the phase voltage resulting in low-order torque ripple in the motor. Inverter topologies with an octadecagonal (18 sided) space vector structure eliminate fifth-, seventh-, eleventh-, and thirteenth-order harmonics from the phase voltage, and hence, the dominant sixth- and twelfth-order torque ripple generation is eliminated. Octadecagonal space vector structures proposed in the past require multiple dc sources, which makes four-quadrant operation of the drive system difficult and costly. In this paper, the formation of a multilevel nine-concentric octadecagonal space vector structure using a single dc source is proposed. Detailed experimental results, using open-loop $V/f$ control and rotor field-oriented control, are presented to validate the effectiveness of the proposed drive scheme. [ABSTRACT FROM PUBLISHER]

In this paper, a fault-tolerant multiphase multilevel inverter (MPMLI) configuration is proposed based on the dual inverter concept. This configuration helps to improve the performance of pole–phase modulated multiphase induction motor (PPMMIM) drive in both normal and switch failure conditions. Comparing to the existing multilevel inverter topologies for multiphase induction motor (MIM) drives, the proposed MPMLI configuration requires less number of dc sources and power electronic devices. The proposed MPMLI configuration is able to sustain under various faulty conditions, which can improve the reliability of the system. In addition, dc-link utilization (DLU) in low-pole mode is improved by using space vector pulsewidth modulation (SVPWM). In high-pole mode, carrier-phase-shifted 3-Φ SVPWM is used for reducing the torque ripple. This MPMLI configuration produces a multilevel voltage profile across the effective phase in 3-phase 12-pole mode. By maintaining the V/f ratio constant, the proposed MPMLI-fed MIM drive facilitates a wide range of load torque with half of the rated speed in faulty condition. This advantage makes it suitable for traction and electric vehicle applications where reliability and wide range of torque–speed are the major concerns. The performance of proposed MPMLI-fed 5 hp, 9-φ PPMMIM drive is simulated by finite-element method (FEM) in ANSYS Maxwell 2-D and experimentally verified by laboratory prototype under normal and faulty conditions. [ABSTRACT FROM PUBLISHER]

In this paper, a new carrier-based pulse width modulation (PWM) strategy providing common-mode voltage (CMV) elimination and reduced current ripple in a three-level neutral-point-clamped inverter is introduced. The employed switching sequences are made up of the three zero CMV (ZCMV) vectors, and one among the three vec-tors is applied at two ends of a half-carrier cycle. The output current ripple characteristics pertaining to those switching sequences are investigated. In a carrier cycle, the root-mean-square current ripple minimization is analyzed and an optimal sequence is derived accordingly. The presented PWM scheme results in a considerably reduced current harmonic distortion in a wide modulation region as compared to the two existing ZCMV schemes on the same average switching frequency. Also, an implementation of sawtooth-carrier-based PWM patterns is proposed for further improvement of the harmonic performance. The algorithm requires small computational burden and is straightforward for an online implementation. Simulation and experimental results are both provided to validate the good performance of the proposed PWM method. [ABSTRACT FROM PUBLISHER]

This paper studies and proposes the vector space decomposition-based direct torque control (DTC) scheme for the T-type neutral-point-clamping (T-NPC) three-level inverters-fed double-stator-winding permanent magnet synchronous machine (PMSM) drive, which provides an effective solution for high-power high-reliability applications. The key is to propose a simple but effective space vector modulation (SVM) for DTC of T-NPC double-stator-winding drives-based two-step voltage vector synthesis, in such a way that good dynamic response and harmonic performance are obtained. The closed-loop controllers on harmonic subspace are incorporated to suppress the possible harmonics induced from back electromotive force and unbalanced parameters in phase windings of electrical machine. Furthermore, a hybrid current control is proposed for fault-tolerant operation of the T-NPC double-stator-winding PMSM drives under one-phase open-circuit conditions. In the hybrid current controller, the healthy winding still uses the SVM-DTC control while the faulty winding uses the closed-loop current controller to track the optimized current references. Both simulation and experimental results are presented to verify the performance of the proposed switching strategies and control schemes. [ABSTRACT FROM AUTHOR]

The injected grid current of the voltage-controlled grid-connected inverter has serious distortion due to the low frequency harmonic components in the output voltage, which is resulted by the dead time of the drive signals of the power switches, and the distortion cannot be eliminated even when an output voltage closed loop is incorporated. This paper introduces a virtual series impedance to increase the output impedance of the grid-connected inverter only at the dominated lower harmonic frequencies; thus, the injected grid current quality can be improved and the dynamic performance of the grid-connected inverter is not deteriorated. Experimental results from a 6-kW single-phase grid-connected inverter confirm the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

The six-step operation of surface-mounted permanent magnet machine drives in a flux weakening region has many advantages compared to the pulse width modulation mode, such as the reduced switching loss and fully utilized inverter output voltage. However, if the ratio of the sampling frequency to the fundamental frequency is low in fixed sampling system, the low-frequency oscillation in the current can be incurred in the six-step operation. The low-frequency current causes a system stability problem and reduces system efficiency due to an excessive heat and high power loss. Therefore, this paper proposes the variable time step controller for six-step operation. By updating an output voltage, sampling phase currents, and executing the digital controller synchronized with the variable sampling time, the turn on and off switch signals for six-step operation can be generated at the exact moment. As a result, the low-frequency oscillation in the phase current can be eliminated. In addition, the system transfer function of the proposed control method is discussed for the system stability and system dynamic analysis. The effectiveness of the proposed method is verified by the comparative simulation and experimental results. [ABSTRACT FROM AUTHOR]

DC-link voltage fluctuation, originated from the single-phase power supply, has a significant impact on the railway traction drive system. Instead of employing a large LC filter to suppress the fluctuation, software solutions are of more interests, since they do not add additional components to the system. A state-of-the-art feedforward strategy predicts the dc-link voltage pattern based on its repetitive nature and directly modifies the duty cycle fed to the inverter to eliminate the impact of the fluctuation. Yet this strategy requires a symmetrical and consistent pulse pattern. In this paper, a compensation approach for synchronous space vector modulation with multiple pulse patterns is proposed. It utilizes the prediction of the dc-link voltage pattern and, based on the volt–second balancing principle, modifies the switching instants corresponding to different pulse patterns. Simulation and experimental results show that the proposed method can significantly eliminate the impact of the fluctuation. [ABSTRACT FROM PUBLISHER]

Over recent years, the output power of micro-inverters [module-incorporated inverter (MIC)] is progressively pushed to higher levels, following the current photovoltaic (PV) modules market trends. The interleaved Flyback inverter—under discontinuous conduction mode of operation (DCM)—is an appealing solution for PV applications which are based on MIC technology. This topology provides increased power level for distributed PV generation exploitation with simple control configuration, high efficiency, and reduced filter size. In this paper, the harmonic injection capability is incorporated into the interleaved Flyback inverter for the implementation of an active anti-islanding scheme. A suitable technical solution is proposed that bypasses the unfolding H-bridge, without affecting the active power generation of the inverter and without requiring any hardware modification. In addition, a mathematical model based on the instantaneous power balance theory is presented, being a powerful analysis tool for inverters operating under complete magnetic discharge such as the Flyback inverter (either conventional or interleaved) under DCM or boundary conduction mode of operation. The proposed model predicts accurately the steady-state operational behavior of the Flyback inverter under current harmonic injection, either in grid-tied or islanding operation. The proposed technical implementation method and mathematical model are verified through simulation and experimental results. Finally, an anti-islanding set-up based on the proposed harmonic injection technique is presented and implemented into the Flyback micro-inverter. The proposed set-up is verified through experimental results on various quality factor values, as well as for weak grid conditions. [ABSTRACT FROM AUTHOR]

When employed as a modulator in power inverters, model predictive control has an equivalence to a recently proposed modulation technique known as feedback quantizer modulation (FBQM). Both schemes produce a random-like switching pattern that can facilitate explicit control over the shape of frequency spectra associated with inverter output voltages and currents. This is useful to satisfy electromagnetic interference and acoustic noise requirements, and to avoid excitation of external system resonances. However, it will be shown in this paper that inverter deadtime introduces a disturbance into FBQM that significantly degrades the ability to shape the frequency spectra. Several compensation techniques, designed to model the effect of deadtime inside the formulation of FBQM, are proposed and experimentally verified on a two-level three-phase inverter. [ABSTRACT FROM PUBLISHER]

This paper presents the mathematical and harmonic analyses of output phase voltages of three-phase voltage source inverters which employ a hybrid two-dimensional–threedimensional (2-D–3-D) space vector modulation (SVM) voltage control algorithm. The explicit time-domain representation of the harmonic components in addition to the total harmonic distortion (THD) of the output phase voltages is given in terms of system and control parameters. This paper also investigates the harmonic characteristics and THD performance against the linearity of the modulation region which helps in the harmonic performance and design studies of such inverters employing the hybrid 2-D–3-D SVM. The fundamental component of the output voltages follows the reference with lower THD in the linear modulation region rather than the overmodulation region. Experimental results are used to validate these analyses as well as the effectiveness of the hybrid 2-D–3-D SVM algorithm for generating balanced and low THD phase voltages. [ABSTRACT FROM PUBLISHER]

A new zero-sequence circulating current (ZSCC) reduction method for multimodule voltage source inverters (MVSIs) consisting of P three-phase inverters that are connected in parallel is proposed in this paper. Four-switch inverter modules are used instead of the conventional six-switch modules to reduce the cost. In this paper, the effectiveness of the proposed ZSCC reduction method is studied using selective harmonic elimination pulse width modulation. The proposed ZSCC reduction method can remove about P times the number of harmonics using the same switching frequency as compared to more conventional methods, as explained later in this paper. The concepts discussed in the paper are confirmed with results obtained from an MVSI experimental prototype. [ABSTRACT FROM AUTHOR]

Distributed energy resources (DERs) are expected to provide ancillary functions including reactive power generation and harmonics compensation. Meanwhile, multilevel inverters and two-level converters with optimal pulsewidth modulation (OPWM) will be commonly used for DERs at high power levels. The challenge is to realize harmonic compensation with limited switching angles. This paper presents an online solution to realize the selective harmonics compensation (SHC), and power generation with DERs. For harmonics compensation, the selective harmonic components in the load current are detected. Then, the harmonic voltages are provided with DERs to cancel out these detected components. Since the power converter is requested to realize both harmonics filtering and power generation, limitations on harmonics compensation at the given power are discussed. Power hardware-in-the-loop-based online verifications are shown at the end of the paper. [ABSTRACT FROM AUTHOR]

This paper presents the design and implementation of a simple neutral point potential (NPP) regulator for a three-level diode-clamped inverter employing a sine-triangle regulator in conjunction with a closed-loop controller with reduced switching losses. The regulator principle is based on adding a continuous variable offset voltage which regulates the midpoint potential of the dc bus. The novelty of the proposed NPP regulator is in the determination of the magnitude of variable offset voltage based upon the average value, peak-to-peak amplitude, total harmonic distortions, and third harmonic content in NPP. Aside from maintaining dc-bus voltage balance, the proposed regulator leads to a significant reduction in the voltage distortion at the NP, resulting in the reduction of the required dc-bus capacitance. It also reduces the switching losses of the inverter by inserting the “no-switching” zone within each half cycle of the fundamental voltage wave. Analytical, computer simulation, and experimental results verifying the approach are presented in this paper for various load power factor angles. [ABSTRACT FROM AUTHOR]

The Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. The unique feature of the ZSI is that it can operate either in buck or boost mode with a wide range of obtainable output voltages from a given input voltage. This topology also exhibits better electromagnetic-interference noise immunity when compared to a traditional voltage-source inverter (VSI). However, the LC impedance network of ZSI significantly increases the size and cost of the power converter and can make it unsuitable for low-power applications. This paper proposes a novel topology called switched boost inverter (SBI) which exhibits similar advantages of ZSI with lower number of passive components and more active components compared to ZSI. The steady-state and small-signal analyses of SBI, along with its pulsewidth modulation (PWM) control strategies, have been discussed in this paper. This paper also presents a comparison of SBI and ZSI with the same input and output parameters. The theoretical analysis given in this paper has been validated using a laboratory prototype of SBI, and the experimental results are presented for verification. The experimental harmonic spectrum of the inverter's output voltage with the proposed PWM technique is also plotted and compared with that of a traditional VSI. All the experimental results show good correlation between theory and experiments. [ABSTRACT FROM PUBLISHER]

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

This paper investigates the suitability of selective harmonic elimination (SHE) for low-loss multimegawatt grid-connected photovoltaic (PV) inverters. The proposed system is able to meet utilities regulations, IEEE and IEC standards. In an attempt to substantiate the potential superiority of SHE over carrier-based or space-vector pulsewidth modulation (PWM), this paper demonstrates that SHE may allow grid-connected PV inverters to be controlled using a switching frequency of less than 1 kHz, while the inverter is still able to provide necessary operation features such as independent control of active and reactive powers and operation control simplicity. For system validation, experimental results with SHE are compared to the case when the inverter is controlled using third-harmonic injection PWM, with a 2-kHz switching frequency. Furthermore, the paper proposes a new implementation technique for SHE that utilizes the third harmonics to spread the switching angles over 90° instead of being located in a narrow range as generated when using conventional techniques, along with increases in modulation index. The advantages of the proposed technique include simplicity in implementation and flexibility in PWM waveforms. Simulation and experimentation demonstrate agreement, which validates the practicability of the proposed system. [ABSTRACT FROM AUTHOR]

A new approach for modulation of an 11-level cascade multilevel inverter using selective harmonic elimination is presented in this paper. The dc sources feeding the multilevel inverter are considered to be varying in time, and the switching angles are adapted to the dc source variation. This method uses genetic algorithms to obtain switching angles offline for different dc source values. Then, artificial neural networks are used to determine the switching angles that correspond to the real-time values of the dc sources for each phase. This implies that each one of the dc sources of this topology can have different values at any time, but the output fundamental voltage will stay constant and the harmonic content will still meet the specifications. The modulating switching angles are updated at each cycle of the output fundamental voltage. This paper gives details on the method in addition to simulation and experimental results. [ABSTRACT FROM PUBLISHER]

This paper addresses the inverter nonlinearity of a three-level T-type inverter. The main causes of the nonlinearity are pulse shaping, pulse skipping due to narrow pulses for the dead time, and voltage drop of the switching devices. Although the same causes have existed in two-level inverters, the pulse skipping phenomenon and results are quite different in the case of the three-level T-type inverter. The effects of pulse shaping and skipping have been investigated and discussed. In addition, the voltage drop of the switching devices has been considered in conjunction with the conduction path of the T-type inverter. Compensation methods based on the pulse width modulation (PWM) of T-type inverter to alleviate the inverter nonlinearity have been proposed from research results. The proposed methods could be easily implemented by adding appropriate offset voltages to the voltage references of the inverter in PWM. Furthermore, a neutral voltage balancing method of a three-level T-type inverter has been proposed in conjunction with the proposed PWM methods using offset voltage. Through extensive experimental tests, the fifth- and seventh-harmonic components of the current are conspicuously reduced along with the even harmonics. The neutral voltage of the inverter can be balanced effectively with the proposed offset voltage adjustments as well. [ABSTRACT FROM AUTHOR]

Large-scale photovoltaic (LSPV) energy conversion systems have been installed at many places across the world. The essential component of the LSPV system is the dc–ac conversion stage. The usage of multilevel converters is one of the recent advances in the dc–ac conversion stage of the LSPV system to enable transformer-less inversion. Current-fed multilevel inverter has been chosen in this paper as it provides high power inversion with inherent voltage boosting, and thus, avoids the usage of transformer. High power conversion necessitates low device switching frequency operation in order to satisfy thermal constraint of semiconductor devices and also to improve efficiency. However, low device switching frequency operation leads to higher harmonic distortion of inverter output currents. Synchronous optimal pulsewidth modulation (SOP) technique is an emerging low device switching frequency modulation technique that has been successfully implemented for voltage-source multilevel inverters. However, the state-of-the-art SOP technique cannot be directly applied to modulate current-source multilevel inverter topologies due to additional constraints on the switching commutations. Therefore, the purpose of our study was to propose a modified SOP technique to achieve: low device switching frequency and minimal harmonic distortion of inverter output currents. The topology of current-fed five-level inverter was used for demonstrating the performance of proposed technique. A generalized conversion method was introduced in the modified SOP technique for including switching constraints of the current-fed inverter. In addition, a state-sequencing machine was developed by utilizing redundant inverter states to produce equal switching commutation among all semiconductor devices at minimal switching frequency of 350 Hz. The experimental results obtained from the five-level current-source inverter of 1.2 kW demonstrated the effectiveness of the proposed SOP technique. [ABSTRACT FROM AUTHOR]

This paper investigates a control method to significantly reduce the low-frequency current oscillation for six-step operation of a three-phase inverter. The six-step operation of an ac electric machine drive system under high speeds has a few advantages compared with pulse width modulation (PWM) operation including reduced switching losses, a better utilization of the dc bus voltage, and an enhanced speed capability. In digital implementation of the six-step control, power electronics may not be able to switch on and off exactly at the zero crossing points of reference voltages, which will result in a dc offset in phase voltages and cause a low-frequency oscillation in phase currents. The low-frequency oscillation will create issues such as higher power losses, lower efficiency, and excessive heat that may demagnetize magnets on the rotor for a permanent magnet synchronous machine. This research presents a control algorithm using asymmetric PWM to ensure that power electronics switch on and off exactly at the reference voltage zero crossing points. Both simulation and experimental results demonstrate the algorithm can reduce the low-frequency oscillation in phase currents by more than 90%. [ABSTRACT FROM AUTHOR]

This paper presents a new high-frequency modulation method for multilevel converters. The proposed method provides a broad linear operating range and can be digitally implemented with minimal computational effort. This modulation method creates a phase voltage composed of a rectangular component superimposed on the top of a quasi-square-shaped reference function. The reference functions are defined such that the utilization of the dc-link voltage is maximized in any modulation index, while the dv/dt of the switches is always the minimum possible value. In order to implement the proposed method, an update time that is much shorter than the fundamental period is defined in the algorithm for updating the rectangular components of the reference voltage. The high-frequency rectangular component can then be imposed on the reference function to generate the final switching function by switching between two voltage levels during the time between two update instances. Several experimental results are provided to evaluate the performance of the proposed method and to compare its operation to conventional methods. [ABSTRACT FROM PUBLISHER]

In this paper, the near-state pulse width modulation (NSPWM), adapted to be used in dual-voltage source inverter (VSI) fed open-end load, is introduced primarily aiming to appreciably minimize the voltage total harmonic distortion (THD). Within the framework of the proposed method, the active time of pulses at the second inverter is relatively adjusted within switching interval (compared to the first VSI). The phase voltage harmonics are formulated for dual-inverter modulated by NSPWM; then, optimal adjustment is identified via a three-dimensional curve of phase voltage THD versus modulation index (MI) and phase angle displacement (PAD). Due to the limitation of MI in NSPWM, the desired output voltage is synthesized with modifying not only MI but also PAD between references of two VSIs. Furthermore, NSPWM inherently takes advantage of better efficiency compared to conventional space vector modulation due to switching only two phases within an interval (by clamping one phase to positive/negative dc-rail). The dual-VSI supplied by two isolated dc sources is assembled in the laboratory to experimentally evaluate the THD reduction feature of the proposed method; also, the simulation results obtained by means of a MATLAB/Simulink environment show close agreement with experimental data. [ABSTRACT FROM PUBLISHER]

A fully integrated on-board battery charger for future electric vehicles (EVs) has been recently introduced. It reutilizes all the propulsion components of an EV in charging/vehicle-to-grid (V2G) modes, it does not require any additional components or hardware reconfiguration, and charging/V2G modes are realized with zero electromagnetic torque production. Both fast (three-phase) and slow (single-phase) chargings are possible, with unity power factor operation at the grid side. The solution is based on the use of a triple three-phase machine and a nine-phase inverter/rectifier. This paper reports on the results of efficiency evaluation for the said system. Testing is performed using both a nine-phase induction machine and a nine-phase permanent magnet machine for a range of operating conditions in charging/V2G modes, with both three-phase and single-phase grid connection. Additionally, the impact of converter interleaving on the losses and efficiency is also studied. Losses are separated for different subsystems, thus providing an insight into the importance of optimization of different EV power train components from the efficiency point of view. Promising efficiencies, in the order of 90%, are achieved although none of the system components have been optimized. [ABSTRACT FROM AUTHOR]

This paper proposes a novel harmonic suppression scheme for two-level inverter fed three-terminal induction motor drives using switched capacitive filter. Capacitor fed H-bridges used as filters are cascaded to conventional two-level inverter to eliminate fifth- and seventh-order harmonics for the full modulation range including a six-step operation. For the first time, two-level dodecagonal voltage space vector is implemented with single dc supply for three-terminal induction motor drive. Enabling the switched capacitive filtering at low-voltage domain and shifting the high frequency switching to the switched capacitive filter is shown. A uniform pulse width modulation technique is shown which charges and maintains the capacitor voltages while eliminating the fifth- and seventh-order harmonics for the full speed range. [ABSTRACT FROM AUTHOR]

For multilevel converters, as their selective harmonic elimination (SHE) equations are highly related to the switching patterns, it is almost impossible to give a complete study for all the switching patterns under the traditional SHE framework. In this paper, a unified SHE approach is proposed, in which the various SHE equations for different switching patterns are merged into one group of unified SHE equations and the inequality constraints on the switching angles are eliminated at all. This unified SHE equations can be solved by any methods, which have been used in solving the traditional SHE problems. By using the theory of Groebner bases and symmetric polynomials, all the possible switching patterns and the corresponding switching angles can be solved simultaneously. The study on the case for four switching angles discovers some unusual switching patterns that have the lowest total harmonic distortion for low-modulation indices. Also, the case for nine switching angles with modulation index m=\text0.72 is studied; in total, there exist 43 groups of switching angles, which belong to 33 different switching patterns. Experiments on a 13-level cascaded-H bridge converter verify the correctness of this unified multilevel SHE approach. [ABSTRACT FROM PUBLISHER]

In grid-connected inverters, a feedforward controller accurately compensates for a large number of the harmonic components of the injected current. This controller is fast and directly tackles the grid dynamic voltage disturbances without doing any further harmonic analysis. A feedforward controller was introduced to a three-phase grid connection with a wye configuration; however, for the widespread delta connections, such a scheme is less established. Moreover, the nonsinusoidal profile of the grid voltage waveform makes the online conversion of line-to-line values into phase values impossible. In this paper, implicit zero-sequence discontinuous pulse width modulation (IZDPWM) based feedforward control is implemented on the two-level grid-connected inverter. Regardless of the grid topology, the IZDPWM-based controller ensures sinusoidal current injection to the grid under balanced, unbalanced, and distorted conditions. [ABSTRACT FROM PUBLISHER]

Multilevel active neutral-point-clamped (ANPC) converter is popularly known for its higher medium voltage drives up to 6.9 kV. However, common-mode voltages (CMV) are generated when using the well-established carrier-based pulse width modulation (PWM) modulation technique. As a result, CMV will become the major cause of the premature bearing failures and the conducted electromagnetic interferences. In this paper, a reduced CMV strategy is proposed for the ANPC which employs an alternatively new hybrid carrier-based modulation named as interleaved sawtooth carrier phase-disposition PWM (ISC-PD-PWM). By doing so, enhanced harmonic profile is achieved as compared to the typically used classical phase-shifted carrier PWM (PSC-PWM). Therefore, a comparative evaluation of the seven-level (7L) ANPC performance using the proposed reduced CMV approach is made between the novel hybrid ISC-PD-PWM and the conventional PSC-PWM in terms of harmonic analysis. The experimental results have proven the feasibility of the proposed concepts with the CMV effectively reduced. Such perceived merits make ANPC be more attractive for its motor drives. [ABSTRACT FROM AUTHOR]

This paper proposes a new configuration for static ground power unit (GPU) based on the novel 25-level hybrid active neutral-point-clamped (HANPC) converter. The superiority of the proposed converter, as compared with conventional and other suggested multilevel converters, is significant decreasing the number of switches and minimizing the number of flying capacitors (FC) in converter. This improvement is possible by using suggested low-voltage submodule converter to the ANPC converter and proposed modulation method. This results in reduction of the size and cost of converter and makes it more feasible and reliable. Applying the active voltage balancing method for FC in the proposed HANPC converter guaranties fast charging and voltage-level regulation of FC without using balance booster circuit. Improving output voltage spectrum leads to inductance reduction of output L–C filter which enhances static GPU performance. The simulation and experimental results verify the validity and feasibility of the proposed converter. [ABSTRACT FROM AUTHOR]

This paper presents the design and implementation of a Class EF$_2$ inverter and Class EF$_2$ rectifier for two -W wireless power transfer (WPT) systems, one operating at 6.78 MHz and the other at 27.12 MHz. It will be shown that the Class EF$_2$ circuits can be designed to have beneficial features for WPT applications such as reduced second-harmonic component and lower total harmonic distortion, higher power-output capability, reduction in magnetic core requirements and operation at higher frequencies in rectification compared to other circuit topologies. A model will first be presented to analyze the circuits and to derive values of its components to achieve optimum switching operation. Additional analysis regarding harmonic content, magnetic core requirements and open-circuit protection will also be performed. The design and implementation process of the two Class-EF $_2$-based WPT systems will be discussed and compared to an equivalent Class-E-based WPT system. Experimental results will be provided to confirm validity of the analysis. A dc–dc efficiency of 75% was achieved with Class-EF$_2$-based systems. [ABSTRACT FROM AUTHOR]

Typical algorithms of multidimensional space-vector pulsewidth modulation (SVPWM) divide (n –1) dimensional space into (n–1)/2 subplanes with decoupling matrix or symmetrical component approach. However, the determination of effective sectors and appropriate space voltage vectors takes a heavy computing burden. Taking the five-phase inverter as example, the relationship between the operation time of branch switches and the dwell times of active space vectors in the SVPWM method is analyzed in this paper. Then, the branch space voltage vector (BSVV) corresponding to the individual active branch voltage is defined and the synthesis of other active space voltage vectors using BSVVs is given. Furthermore, only the BSVVs are chosen as the base vectors to synthesize the reference voltage vector, and a novel SVPWM algorithm is present. The operation time of branch switch is deduced, and the equivalence of the normalized load-phase voltages and operation times of branch switches is emphasized and used to analyze the simulation results. The zero-sequence voltage vector is also included in the algorithm as a parameter and its effects on the dwell time of the BSVVs, the modulation index and the common-mode voltage are explicated. Finally, the extension to an n-phase system is discussed. The algorithm eliminates the selection of sectors and proper active space vectors, and can effectively control the dwell time of switches of multiphase inverter. Experimental results proved the feasibility and effectiveness of the algorithm. [ABSTRACT FROM AUTHOR]

In this paper, a novel cascaded seven-level inverter topology with a single input source integrating switched-capacitor techniques is presented. Compared with the traditional cascade multilevel inverter, the proposed topology replaces all the separate dc sources with capacitors, leaving only one H-bridge cell with a real dc voltage source and only adds two charging switches. The capacitor charging circuit contains only power switches, so that the capacitor charging time is independent of the load. The capacitor voltage can be controlled at a desired level without complex voltage control algorithm and only use the most common carrier phase-shifted sinusoidal pulse width modulation strategy. The operation principle and the charging–discharging characteristic analysis are discussed in detail. A 1-kW experimental prototype is built and tested to verify the feasibility and effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid selective harmonic mitigation (SHM)-selective harmonic elimination (SHE) switching technique based on pulse-amplitude modulation (PAM) concept. It has been applied on a four-leg neutral-point-clamped (NPC) inverter to eliminate and mitigate more harmonic orders than recently proposed hybrid SHM-SHE-pulse width modulation (PWM) method while generating switching pulses at the same frequency. In conventional SHE and SHM techniques, equations are solved to attain the switching angles. Regarding the PAM, value of inverter dc voltage can be considered as an additional degree of freedom by which the flexibility of such techniques would be increased maintaining the switching frequency. In the proposed SHM-SHE-PAM, the conventional equations are reformulated to obtain constant switching angles for a vast range of modulation index (ma) applied on a four-leg NPC inverter. Switching pulses of the three-phase legs and the fourth leg are calculated to mitigate the nontriplen harmonics and eliminate the triplen ones, respectively. Due to the unique switching angles valid in the whole range for ma, the calculation time and volume (storage capacity) are significantly reduced leading to a simpler controller implementable on a low-risk and cheap AVR chip. Experimental tests’ results of a four-leg NPC inverter as UPS application prove the good dynamic performance and accuracy of the proposed implemented switching technique in producing associated pulses for the inverter switches at very low frequency to mitigate/eliminate undesired harmonic orders from the output phase/line voltage waveforms without using bulky filters. [ABSTRACT FROM AUTHOR]

This paper presents a new E-type module for asymmetrical multilevel inverters (MLIs) with reduced components. Each module produces 13 levels with four unequal dc sources and 10 switches. The design of the proposed module makes some preferable features with a better quality than similar modules such as the low number of semiconductors and dc sources and low switching frequency. Also, this module is able to create a negative level without any additional circuit such as an H-bridge, which causes reduction of voltage stress on switches. Cascade connection of the proposed structure leads to a modular topology with more levels and higher voltages. Selective harmonics elimination pulse width modulation (SHE-PWM) scheme is used to achieve high-quality output voltage with lower harmonics. MATLAB simulations and practical results are presented to validate the proposed module good performance. Module output voltage satisfies harmonics standard (IEEE519) without any filter in output. [ABSTRACT FROM AUTHOR]

This paper presents a harmonic elimination technique based on a three-level dodecagonal space vector structure for open-end winding induction motor (IM) drives with a single-dc supply. Advantages of dodecagonal space vector switching and multilevel inverters are achieved with a single-dc supply. A dc supply-fed three-level flying capacitor (FC) inverter feeds active power to one end of the IM winding terminals and H-bridge connected capacitors eliminate fifth- and seventh-order harmonics from the other end. A pulsewidth modulation (PWM) technique is developed to switch the three-level dodecagonal space vectors and simultaneously control the H-bridge capacitors at 0.1445V\text{dc}. The fifth- and seventh-order harmonics are eliminated for the full modulation range of the three-level FC inverter, including the extreme 6-step operation. An increase in the linear modulation range has been achieved, resulting in improved dc bus utilization. Harmonic elimination is achieved by increasing switching frequency of the low-voltage capacitor connected H-bridge inverter; thus, switching frequency for the high-voltage dc supply-fed FC inverter is not increased. Using the proposed scheme, the instantaneous phase voltage never exceeds \frac23V\text{dc} (maximum phase voltage applied for hexagonal space vector structure) for which the machine windings are rated. Additionally, the proposed inverter has also been shown to operate for field oriented control of the open-end winding IM drive. [ABSTRACT FROM AUTHOR]

Multilevel converters have received more attention recently. Multilevel converters can be used not only in high-voltage high-power applications, but also in energy storage systems, thanks to reduced harmonics and electromagnetic interferences. State-of-charge (SoC) balancing of the storage system cells within cascaded multilevel inverters, e.g., batteries, can be one of the challenges in practical applications. Different methods have been studied and reported in technical literature. However, the SoC balancing is still a challenging issue. In this paper, a new method is proposed to solve this problem by applying several clever but simple changes to the staircase modulation switching scheme without changing the output waveform properties. Validations for this simple method were performed through simulation and experimental prototype. Despite the simplicity of the method, the simulation and experimental results show that SoC balancing of the cells has significantly improved. [ABSTRACT FROM PUBLISHER]

The device switching frequency of current source converters (CSCs) in high-power medium-voltage (MV) drive applications is normally around 500 Hz. Conventional space vector modulation (SVM) features fast dynamic response but its output contains low-order harmonics with high magnitudes. In this paper, a natural-sampling-based SVM (NS-SVM) scheme is proposed to substantially suppress the low-order harmonics in practical CSC-based drives. This study proposes an equivalent discretization of NS-SVM wherein natural sampling pulse width modulation performance can be achieved with regular sampling frequency (same as a conventional SVM) instead of a high or even infinite sampling frequency. Equations for natural-sampling-based dwell time calculations for each selected vector are developed. The corresponding simplified but precise enough equations are derived on the basis of the Newton–Raphson algorithm to achieve fast online digital implementation. The proposed NS-SVM features superior low-order harmonic performance and inherits the high dynamic response and low sampling frequency of conventional SVM. Simulations and experiments are provided to verify the proposed NS-SVM scheme. [ABSTRACT FROM AUTHOR]

This paper presents the Bee optimization method for harmonic elimination in a cascaded multilevel inverter. The main objective in selective harmonic elimination pulsewidth modulation strategy is eliminating low-order harmonics by solving nonlinear equations, while the fundamental component is satisfied. In this paper, the Bee algorithm (BA) is applied to a 7-level inverter for solving the equations. The algorithm is based on the food foraging behavior of a swarm of a honeybees and it performs a neighborhood search combined with a random search. This method has higher precision and probability of convergence than the genetic algorithm (GA). MATLAB software is used for optimization and comparison of GA and BA. Simulation results show superiority of BA over GA in attaining accurate global minima and higher convergence rate. Also, its performance in 10 times run is the same as in 1 time run. Finally, for verifying purposes, an experimental study is performed. [ABSTRACT FROM AUTHOR]

In this paper, total harmonic distortion (THD) minimization of the output voltage of multilevel inverters is discussed. An efficient approach in reducing the harmonic contents of the inverter's output voltage is THD minimization. In multilevel inverters with a fundamental frequency switching strategy (each switch turning on and off once per output cycle), the switching angles can be selected so that the output THD is minimized (such as the so-called optimal-minimization-of-THD strategy). To obtain the optimum switching angles, an optimization algorithm is applied to the output-voltage THD. In three-phase multilevel inverters, the optimization algorithm is commonly applied to the phase voltage of the inverter. This results in the minimum THD in phase voltage but not necessarily in the line-to-line minimum THD, whereas in three-phase applications, the line-voltage harmonics are of the main concern from the load point of view. In this paper, using the genetic algorithm, a THD minimization process is directly applied to the line-to-line voltage of the inverter. This paper is based on a seven-level inverter. To verify the simulation results, a seven-level-cascaded-H-bridge-inverter-based hardware prototype, including an ATMEGA32 AVR microcontroller, has been implemented. Both simulation and experimental results indicate superiority of this approach over the commonly used phase-voltage THD minimization approach. [ABSTRACT FROM AUTHOR]

This paper presents a novel topology for a direct ac–ac power converter, called as the “three-to- k” phase matrix converter. The input to the proposed matrix converter configuration is a three-phase fixed voltage and a fixed frequency supply from the grid. The output is a variable voltage and variable frequency ac supply of any number of phases (k phase). However, the discussion is limited here for a k that is equal to odd number of phases. As an example, a “three-to-five” phase matrix converter is utilized for discussion and analysis. This paper also proposes two pulsewidth modulation (PWM) control techniques for the general topology of the “three-to- k” phase matrix converter. This is based on the so-called direct duty ratio PWM (DPWM). In one presented technique, the output voltage is limited to one half of the input voltage. For the other proposed scheme, the output voltage is enhanced to 78.86% of the input voltage. The proposed control algorithm is validated using simulation and an experimental approach. [ABSTRACT FROM AUTHOR]

Flux harmonic distortion factors (HDFs) of two space vector pulse width modulation (SVPWM) schemes, aimed at sinusoidal output voltage generation with five-phase voltage source inverters, have been evaluated in Part 1 of this paper. Analytical considerations and numerical integration have been applied in order to determine the switching properties of the considered SVPWM methods. It has been shown that the SVPWM based on four large vectors leads to a considerably higher overall per-phase flux HDF than the method based on two large and two medium space vectors. The purpose of the second part of the paper is to relate flux HDFs to the current ripple and current total harmonic distortion and thus explore further switching characteristics of the two SVPWM techniques. The applied approach is based on simulation and experimentation, in conjunction with the subsequent fast Fourier transform of the waveforms, so that all the results for the ripple are obtained using a methodology completely different from the one in Part 1. Relationships that correlate the current ripple and the flux HDFs are established, and it is further shown that the current ripple can be easily calculated from the flux HDF values of Part 1 if the relevant leakage inductances of the two planes are known. Hence, the complete theory of Part 1 is fully verified by both simulation and experimentation. It is also shown that, in certain cases, the SVPWM based on four large vectors may lead to a smaller current ripple despite a considerably higher flux HDF. [ABSTRACT FROM AUTHOR]

Multiphase variable-speed drives supplied from two-level voltage source inverters (VSIs) are, at present, contenders for numerous industrial applications. Various pulsewidth modulation (PWM) methods for multiphase VSIs, aimed at sinusoidal output voltage generation, have been developed using both carrier-based and space-vector approaches. An increased number of voltage space vectors, available for the synthesis of the output voltage, offer greater flexibility for the PWM scheme development, compared to the three-phase case. This paper presents comprehensive analytical analysis and comparison of switching ripple characteristics of two continuous space vector PWM (SVPWM) methods for a five-phase two-level VSI. Considered SVPWM schemes select a different set of four active space vectors per switching period in order to generate sinusoidal output voltages. This paper also presents the evaluation of the flux harmonic distortion factors of the SVPWM techniques. Correlation with corresponding current ripple and total harmonic distortion is established in Part 2 of this paper, where theoretical considerations are verified by simulations and through experimental investigation on a five-phase VSI-fed induction motor drive. [ABSTRACT FROM AUTHOR]

In this paper, the elimination of harmonics in a cascade multilevel inverter by considering the nonequality of separated dc sources by using particle swarm optimization is presented. Solving a nonlinear transcendental equation set describing the harmonic-elimination problem with nonequal dc sources reaches the limitation of contemporary computer algebra software tools using the resultant method. The proposed approach in this paper can be applied to solve the problem in a simpler manner, even when the number of switching angles is increased and the determination of these angles using the resultant theory approach is not possible. Theoretical results are verified by experiments and simulations for an 11-level H-bridge inverter. Results show that the proposed method does effectively eliminate a great number of specific harmonics, and the output voltage is resulted in low total harmonic distortion. [ABSTRACT FROM PUBLISHER]

This paper presents theoretical, simulation, and experimental investigations of input current interharmonics in modern variable-speed drives based on voltage source inverters and diode input rectifiers that are caused by motor current imbalance. It investigates how a disturbance in the inverter dc side current created by unbalanced motor currents propagates from the inverter to the rectifier stage and appears as variable frequency interharmonic distortion in the rectifier input currents. Particular emphasis is given to theoretical analysis of the frequency transformations created by the inverter and rectifier stages and the magnification of the disturbance current caused by parallel resonance in the drive dc bus circuit. The theoretical results are confirmed by simulation and experimental results. They demonstrate that motor current imbalance can be responsible for high non-characteristic inter-harmonic distortion in the drive input currents. A calculation example outlines a procedure for estimation of the drive input current interharmonic distortion based on measurements of the motor currents. The paper should be helpful for people investigating the origin of problems caused by variable frequency interharmonic currents. [ABSTRACT FROM PUBLISHER]

This paper addresses theoretical calculation of a single-phase multilevel pulsewidth modulation (PWM) inverter current total harmonic distortion (THD). Analytical approach introduced in late 1980s for a two-level inverter is generalized for an arbitrary level count for a single-phase inverter. Although the obtained closed-form piecewise analytical solutions assume (infinitely) large ratio of switching and fundamental frequencies and pure inductive load, they are practically very accurate for the ratios of (apparent) switching and fundamental frequencies larger than 25–30 and inductance-dominated loads. Along with strict mathematical solutions, simple accurate Bessel function approximation and hyperbolic average trend one are suggested. The formulas clearly reveal a single-phase PWM inverter current THD dependence on modulation index for an arbitrary voltage level count and are easily modified to cover grid-connected cases. [ABSTRACT FROM PUBLISHER]

The cost reduction of power-electronic devices, the increase in their reliability, efficiency, and power capability, and lower development times, together with more demanding application requirements, has driven the development of several new inverter topologies recently introduced in the industry, particularly medium-voltage converters. New more complex inverter topologies and new application fields come along with additional control challenges, such as voltage imbalances, power-quality issues, higher efficiency needs, and fault-tolerant operation, which necessarily requires the parallel development of modulation schemes. Therefore, recently, there have been significant advances in the field of modulation of dc/ac converters, which conceptually has been dominated during the last several decades almost exclusively by classic pulse-width modulation (PWM) methods. This paper aims to concentrate and discuss the latest developments on this exciting technology, to provide insight on where the state-of-the-art stands today, and analyze the trends and challenges driving its future. [ABSTRACT FROM PUBLISHER]

In this paper, a new inverter topology is proposed for generating a multilevel dodecagonal voltage space vector structure for open-end winding induction motor (IM) using a single dc source. Dodecagonal voltage space vector structure eliminates fifth- and seventh-order harmonic voltages from phase voltage output and hence eliminates the fifth- and seventh-order harmonic currents through the motor leading to removal of the dominant sixth-order torque ripple generation in the motor over the entire modulation range. Multilevel space vector structure generates output voltage with better THD and low dv/dt. In the proposed topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a dc source which delivers the entire active power, whereas the secondary inverter dc-link is maintained by a capacitor, which is self balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small dc-link voltage. Hence, switching losses are small for both primary and secondary inverters. Experimental results show the elimination of fifth- and seventh-order harmonic voltages over the entire modulation range, validating effectiveness of the proposed multilevel inverter scheme. [ABSTRACT FROM PUBLISHER]