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Four-level hybrid-clamped inverter is a newly proposed topology that can operate under a wide voltage range without switches connected in series. However, when it is applied in medium voltage high power conversions, the flying capacitors in each phase will occupy a huge volume and a high switching frequency is required to restrain the voltage ripples. In order to overcome this drawback, a four-level active neutral-point clamped inverter is discussed in this paper, which consists of only six switches and no diodes or flying capacitors are required. In order to balance the neutral-point voltages under the full power factor and modulation index range, a capacitor voltage balance method based on carrier-overlapped pulsewidth modulation is proposed in this paper. The upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection and the central dc-link capacitor voltage is balanced by adjusting the duty cycles of switching signals slightly. Simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n-level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme. [ABSTRACT FROM AUTHOR]

This paper proposes a two-degree-of-freedom (2DoF) interleaving scheme based on phase-disposition (PD) PWM for minimizing the high-frequency zero-sequence circulating current (ZSCC) in modular interleaved three-level converters. The method incorporates an internal interleaving by phase-shifting the carriers in each individual converter, and an external interleaving by phase-shifting the carriers of the different converters. A general harmonic distribution analysis which is valid for all types of voltage source converters is carried out to simplify the evaluation of the proposed method. A comprehensive evaluation of the proposed method shows that the PD-2DoF interleaving scheme produces the lowest ZSCC maximum value as compared to existing approaches. Moreover, it can achieve comparable performances as existing methods do in terms of output quality and common mode voltage magnitude, showing a great potential for practical implementation. Simulation and experimental results are obtained to demonstrate the performance of the proposed method. Generalization of the 2DoF interleaving scheme to high-level converter is also discussed in this paper. [ABSTRACT FROM AUTHOR]

The benefits of employing multilevel pulsewidth-modulated (PWM) waveforms for diagnostic purposes compared to sinusoidal- and square-shaped voltages are presented in this paper. Examples on how the high voltage circuits are designed to enable these studies, as well as results, are discussed. To demonstrate the approach, it is investigated what influence the choice of PWM levels has on the partial discharge (PD) characteristics for two similar wire specimens insulated by different materials. Here, to resemble a motor winding, two different twisted pair test objects insulated by either pure polyamide-imid (PAI) material or with added conductive Cr2O3 material were exposed to voltages with ultrashort rise times. The test objects were fed from either two-, three-, five-, or seven-level inverter waveforms of similar shape as in actual applications. To compare the performances, measurements of the PD characteristics were conducted. Specifically, the total number of PDs, as well as their average maximum amplitude per cycle, was obtained together with the phase-resolved PD pattern for each case. The experimental results presented in this paper show that the total peak and summed PD magnitude (exposure) drop considerably more for the Cr2O3 insulation compared to PAI when applying a five-level or higher level inverter. This reduction is more significant for the insulation with added Cr2O3 material and the usage of higher inverter levels reveals this. As more information can be obtained using higher inverter levels, the evaluation of new material constitutions is preferably done utilizing at least a three-level inverter or higher. [ABSTRACT FROM AUTHOR]

Motors and inverters are increasingly being used in vehicles. As more vehicle components are being adopted, requirement for safety and installation space are increasing. Growing attention is being paid to the use of six-phase permanent magnet synchronous motors (PMSMs) and their parallel control by two inverters, because of their reduced size and enhanced safety. This paper proposes a pulsewidth modulation (PWM) control algorithm for a six-phase PMSM. In low-voltage vehicle components such as electric power steering, the current is usually acquired with resistors placed under the low-side switching devices. In the proposed control algorithm, the neutral voltage of the two inverters is shifted to either a lower or higher voltage within a certain range to allow for the signal conditioning time delay after the switching device turns on or off, and the time taken for the phase current to rise or settle. The paper proposes a novel PWM control algorithm that ensures that the on-time of the low-side switching devices satisfies the restriction on current sensing with resistors and reduces the current in the capacitor at the same time. The work contributes to reducing the current in a practical configuration involving low-voltage vehicle components. [ABSTRACT FROM AUTHOR]

Standard pulsewidth modulation (PWM) schemes for modular multilevel converters (MMC) have neglected deviations of the module voltages from the mean module voltage of an MMC arm as well as the dynamic change in the module voltages since their last measurement and during the switching period. This induces an output voltage error. Large output voltage errors disturb the higher level closed-loop control of the MMC, such that control targets cannot be met anymore. The output voltage error can be reduced using advanced PWM methods that predict and include the dynamic change of the individual module voltages during a switching period in the calculations for the duty cycle. This paper shows measurement results obtained from an experimental medium-voltage prototype, proving that advanced methods lead to much lower output voltage errors than the standard methods, but cannot fulfill the expectations raised by the simulations documented in the literature. In order to overcome the limitations of the old method, a new method that includes the semiconductor voltage drop and parasitic resistances is introduced and evaluated with measurements in this paper. Furthermore, simulation results showing the influence of the considered modulation methods on the closed-loop current control performance are presented. [ABSTRACT FROM AUTHOR]

This paper presents two capacitor voltage balancing (CVB) strategies for modular multilevel converter (MMC) applications. Both balancing schemes are based on model predictive control and are designed to efficiently solve a constrained optimal control problem, where the predicted capacitor voltage errors are included in the cost function with the demanded output voltage of a cluster being forced through an equality constraint. The first method proposed in this paper computes specific modulation indexes for each module using the explicit solution of a relaxed version of the original optimization problem. The second approach proposed in this paper reduces the complexity of the original problem by linearizing the objective function and using an optimal sorting network based on a greedy algorithm to solve this approximation. Considering the structures of both solution approaches, they are integrated into modulation schemes based on phase-shifted and level-shifted pulsewidth modulation algorithms, respectively. Experimental results obtained from a nine-cell single-phase MMC prototype demonstrate the good performance achieved with the proposed methodologies, as well as the implementation simplicity offered by the proposed CVB algorithms. [ABSTRACT FROM AUTHOR]

Induction motor drives operated with a low ratio of the switching frequency to the fundamental frequency (i.e., pulse number) are prone to have high magnitudes of low-order torque harmonics. This paper proposes a method to analytically evaluate the harmonic torque spectrum based on the pulsewidth-modulated voltage waveforms for low pulse number operation. The predicted torque harmonic spectra for different pulsewidth-modulated waveforms are validated through simulations and experiments. This paper also reports optimal switching angles to minimize the total rms value of torque harmonics of order 6, 12, 18 $,\dots,$ $6(N-1)$ , considering the number of switching angles per quarter ($N$) to be 4 and 5. Compared to sine triangle pulsewidth modulation and selective harmonic elimination pulsewidth modulation with the same pulse number, the proposed optimal switching angles significantly reduce the total rms value of all harmonic torques of order lower than $6N$. Extensive simulation and experimental results on a 3.7-kW induction motor drive are presented to demonstrate the superior performance of the proposed optimal pulsewidth modulation. [ABSTRACT FROM AUTHOR]

This paper presents a novel multilevel radio frequency (RF) pulsewidth modulation (PWM) method for all-digital transmitters (ADTx) that actively eliminates the selected harmonics of RF-PWM. Compared with existing multilevel RF-PWM techniques, this method uses several adaptive thresholds and controls the pulsewidth of the corresponding subpulses to make the selected harmonics cancel each other out and keep the fundamental frequency component proportional to input envelope. For the third-harmonic elimination, the corresponding five-level RF-PWM scheme presented in this paper shows that it can significantly relax the filtering requirements and improve the wideband performance of the ADTx. The proposed scheme is verified by extensive simulations and offline measurements. The simulations show good potential for high-frequency operation up to gigahertz ADTx. The measured results show that the third-harmonic suppression of the proposed scheme has increased with the decreasing of the time resolution for digital implementations. For a 3.80-dB peak-to-average power ratio (PAPR) QPSK signal and a 6.04-dB PAPR 16QAM signal at 200-MHz carrier, the proposed scheme can achieve above −51- and −48-dBc third-harmonic suppression, respectively, when the time resolution is 50 ps and relative time resolution is 1%, and improves above 30 dBc to the existing schemes. [ABSTRACT FROM AUTHOR]

Real-time frequency agility is one of the key limitations of current all-digital transmitters (ADTs). In this paper, to address this problem, an ADT based on direct-RF generation is proposed and implemented in a field-programmable gate array (FPGA). To achieve this, the pulse encoding is performed after the digital upconversion, which presents challenges in the pulse encoder implementation. However, the proposed design considerably improves the frequency agility when compared with current state-of-the-art approaches. Two different pulse encoders were designed in this paper, one is based on pulsewidth modulation (PWM) and the other on delta–sigma modulation ( \mathrm \Delta \Sigma \textM ). These units are implemented with high parallelization to achieve the required equivalent sampling rates. The proposed design enables the implementation of all-digital RF transmitters in FPGA with a widely tunable carrier frequency. In this paper, a variation from 0.1 up to 6 GHz of carrier frequency, with a maximum frequency resolution of 1.5625 MHz, is demonstrated. Measurement results in terms of signal-to-noise ratio (SNR) and error-vector magnitude are presented and discussed. In the case of the PWM, maximum SNRs of 39 and 36 dB were obtained for a 5 and 10 MBd of symbol rates (SRs). In the case of \mathrm \Delta \Sigma \textM , maximum SNRs of 38 and 35 dB were obtained for 20 and 40 MBd of the SR. [ABSTRACT FROM PUBLISHER]

The advancement in modulation strategies brings emergent solutions to suppress the leakage current in three-phase two-level transformerless grid-connected voltage source inverters (VSIs). However, most of the techniques are analyzed based on reduced common-mode voltage pulsewidth modulation (PWM) in motor drivers but fail to satisfy the specific requirement of grid-connected applications, such as wider power factor operation and lesser current distortion. To overcome such substantial drawbacks, this paper proposes a novel scalar PWM method for transformerless grid-connected VSIs. First, presented through a generalized scalar approach with unified zero-sequence voltage generation, the method is simple to implement and favored in practice. Besides, systematic and comprehensive mathematical analysis is illustrated to exhibit the validity of implemented method in reducing leakage current and shows its advantages over whole power factor range in terms of dc-link current harmonic, output current quality, and switching losses. Finally, simulations and experimental results are carried out to verify the effectiveness and superiority of the proposed method. [ABSTRACT FROM AUTHOR]

In the topology of double-inverter fed wound rotor induction machine (DI-WRIM) two voltage source inverters (VSIs) are connected one each on stator and rotor terminals. This leads to ripple in both stator and rotor currents. In this paper, these current ripples are analyzed in terms of the stator- and rotor-flux ripples, which are estimated from their respective terminals. To reduce the current ripples, the VSIs of the stator and rotor terminals are modulated with different pulsewidth modulation (PWM) sequences. The switching loss in the DI-WRIM is also analyzed for the proposed stator–rotor PWM sequence combinations, based on the flexibility of changing the power factor, by changing the flux component of the current fed from either side of a DI-WRIM drive. The proposed PWM combinations with the proposed flux component in currents are found to reduce the stator and rotor current ripples and, the switching losses. The analytically estimated root mean square current ripples for the proposed PWM combinations are validated using the simulation and the experimental results obtained from a 3-kW DI-WRIM drive. The analysis on switching losses is validated by measuring the temperature rise of heat sinks present in the individual stator and rotor side VSIs of the DI-WRIM drive. [ABSTRACT FROM AUTHOR]

This paper presents a novel fault-tolerant method for active–neutral-point-clamped (ANPC) inverter using a modified carrier-based pulsewidth modulation. At a fault event, the ANPC inverter is divided into subinverters, and the modulating signal is modified to two modulating signals. The modified modulating signals are used to control the subinverters and allow continuous operation of the three-level ANPC inverter during faulty conditions even up to four open-switch faults per phase. This technique provides the fault-tolerant capability of the ANPC inverter without the need to add any additional phase legs or complex control strategies. Furthermore, the proposed technique ensures the voltage balancing of the dc-link capacitors. The performance of the proposed fault-tolerant technique is verified through simulation studies in MATLAB/Simulink under different faulty conditions. The feasibility of the proposed technique is also verified experimentally. [ABSTRACT FROM AUTHOR]

This paper introduces a novel pulsewidth modulation (PWM) scheme for an open-winding permanent magnet synchronous machine (OW-PMSM) driven by dual two-level three-phase inverter with common dc bus, which can effectively deal with the inherent zero-sequence current (ZSC) problem. Based on the conventional symmetrical unipolar double-frequency sinusoidal PWM scheme with an appropriate phase shift, the common mode voltage (CMV) of two inverters remains same and cancel out each other to eliminate the modulated zero-sequence voltage (ZSV) disturbance source. In this case, the double-frequency effect can be retained to reduce the ac side current ripple and suppress both corresponding motor vibration and acoustic noise, which is advantageous to improve the synthetic performance of motor. The dc-bus voltage utilization of the novel PWM scheme is proved to reach the same maximum value comparing to the conventional modulated ZSV elimination scheme. Meanwhile, a zero-sequence controller is designed to suppress ZSC by further adjusting the two CMVs to counteract other zero-sequence disturbance sources. To verify the analysis, the proposed PWM technique associated with the control method is implemented in an OW-PMSM experimental setup to validate the superiority of the proposed method. [ABSTRACT FROM AUTHOR]

Parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) are widely used due to their distinct advantages of high power delivery, modularity, low current rating devices, etc. Along with these advantages, the parallel interleaved 2L VSIs could also be analyzed as a single three-level (3L) VSI. Conventionally parallel interleaved 2L VSIs are modulated using the 2L pulsewidth modulation (PWM) techniques. However, implementation of parallel interleaved 2L VSIs using the 2L PWM techniques may generate a higher ac side current ripple as compared to implementing the parallel interleaved 2L VSIs using 3L PWM techniques. This paper proposes a carrier-based method for implementing different 3L discontinuous PWM (DPWM) techniques for parallel interleaved 2L three-phase VSIs. Comparison of different 2L switching sequences for implementing a 3L DPWM switching sequence based on circulating current, line current ripple, and switching loss is also carried out. Simulation and experimental results are also displayed to validate the proposal. [ABSTRACT FROM AUTHOR]

It is well known that spatial field harmonics will cause high eddy current losses in surface-mounted permanent magnets (PMs) especially for the fractional-slot PM motors. However, the influence of temporal current harmonics, especially of the high-order temporal harmonics caused by pulsewidth modulation voltages from an inverter, lacks attentions. This paper studies the eddy current losses of the PMs caused by high-order current harmonics. In order to simplify the calculation and save computation time, analytical methods are used to predict the current harmonics caused by the PWM inverter, and the armature reaction field, the eddy current density, and losses in the PMs generated by the current harmonics. Finite element analysis, coupling simulation, and experimental studies are used to verify the analytical results. The study results show that the high-order current harmonics cause much higher eddy current losses than those caused by slotting and fundamental current even though the amplitudes of the high-order current harmonics are much lower. [ABSTRACT FROM AUTHOR]

In domestic induction heating applications, the modulation technique applied to the inverter has a high influence on the acoustic noise emissions. These noise emissions must be avoided, since they may be audible and annoying to the final user. This paper analyzes the acoustic noise emissions that appear when a series half-bridge resonant inverter is operated with a phase-accumulator-based modulator. This modulation technique has the advantage of operating in the frequency domain, and it is compared with the classical pulsewidth modulator regarding the audible noise generated. The frequencies of the tones in the acoustic noise spectrum are theoretically calculated from the parameters of the phase-accumulator-based modulator. The spectral flatness measure is used to quantify the number of cases in which tones are generated by the modulation. Two techniques are applied to the phase-accumulator-based modulator, and their effect is tested. Theoretical results are experimentally verified. [ABSTRACT FROM AUTHOR]

Among multilevel converter topologies, the cascaded H-bridge (CHB) converter is one suitable solution for multiple applications, such as flexible ac transmission systems and motor drives. CHB presents a natural high modularity because it is formed by the serial connection of H-bridges. This paper deals with a CHB where the cells do not have the same aging because the maintenance during the years of operation forces to replace some damaged cells of the converter with new or repaired ones. A method based on clamping one power cell can be used to reduce the power losses of that cell reducing its temperature and increasing its lifetime. However, clamping one cell of the CHB introduces high harmonic distortion around twice the carrier frequency due to the CHB unbalanced operation when a conventional phase-shifted pulsewidth modulation (PWM) is applied. A deep harmonic distortion analysis of the CHB output voltage with thermal control based on clamping one cell is presented. Using this analysis, the harmonic distortion at twice the carrier frequency is eliminated applying a nonconventional phase-shifted PWM where the angles between the carriers of consecutive power cells are modified. Experimental results show how the thermal control applying the clamping of a power cell is achieved while the harmonic distortion around twice the carrier frequency is eliminated. [ABSTRACT FROM AUTHOR]

A bidirectional three-phase dc–ac converter with embedded dc–dc converter for bidirectional storage interface is proposed in this paper. With the help of the embedded dc–dc converter, the voltage of the storage battery can vary in a wide range. To minimize the power rating and power losses of the embedded dc–dc converter, a simple carrier-based pulsewidth modulation (PWM) strategy with zero-sequence injection is proposed. By adopting the proposed PWM strategy, only a small ratio of total power needs to be processed by the embedded dc–dc converter, while most of the power is only processed by the three-phase dc–ac stage within a single conversion stage. As a result, quasi single-stage power conversion is achieved to improve the conversion efficiency of the overall dc–ac power system. Principles, characteristics, and implementations of the proposed three-phase dc–ac converter and its PWM strategy are analyzed in detail. The feasibility and effectiveness of the proposed solutions are verified with experimental results. [ABSTRACT FROM AUTHOR]

Two parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) can be analyzed as a single three-level (3L) VSI. A generalized carrier-based method is proposed in this paper for implementing different 3L pulsewidth modulation (PWM) techniques using two parallel interleaved 2L VSIs. The proposed method modifies the given three-phase reference signals of 3L VSI for implementation of the PWM technique using two parallel interleaved 2L VSIs. The influence of nonidealities on the equivalent 3L PWM switching sequences is also discussed. To overcome the effect of nonidealities, a new modified discontinuous PWM technique (MDPWM1) is proposed. The analysis of different performance indices is carried out for different 3L PWM techniques, and the key advantages of different PWM techniques are identified. Simulation and experimental results are also presented. [ABSTRACT FROM AUTHOR]

Core loss estimation of filter inductors is increasingly important for modeling and optimizing high-frequency, high-efficiency, and high-density pulsewidth modulation (PWM) power electronic converters. However, data provided by inductor core manufacturers are insufficient for core loss estimation in PWM converters, particularly in the case of customized gapped inductors. This paper presents a whole process of characterizing and estimating the core loss of a customized high-current gapped inductor for PWM converters. To excite the inductor for the B–H loop measurement, a test circuit formed by a half-bridge structure is proposed, which has the ability to compensate the asymmetric rectangular voltage on the inductor caused by the device voltage drops. To overcome the other challenges raised by a high excitation current, a refined discontinuous test procedure, triple pulse test, is proposed to reduce the requirements of the high-current test setup (thermal stress, current–time stress for current probes, capacity of dc sources, etc.). For practical purposes, a user-friendly loss map approach is proposed involving only time-domain and electrical variables to replace magnetic variables to enable the straightforward loss mapping process and core loss calculations. Presented experimental results show consistency between the estimated inductor loss and measured values. Overall, the proposed testing approach can be easily implemented on the user's side to develop a loss map of a given inductor. The established core loss map enables the users to accurately and rapidly estimate the core loss of a tested inductor for given PWM waveforms. [ABSTRACT FROM AUTHOR]

It is generally known that averaged models are inadequate in describing the effects of leading-edge and trailing-edge pulsewidth modulation (PWM) on the stability of dc–dc converters. In this paper, using discrete-time models of the buck, boost, and buck–boost converters and considering the effects of leading-edge and trailing-edge PWM, the general expressions of the duty-cycle-to-output-voltage transfer function, Gvd(z), in the discrete-time domain are derived. Based on the low-pass characteristics of the dc-dc converters and related properties of the matrix functions, approximate expressions of Gvd in the frequency domain are derived, which are simple and accurate up to half the switching frequency. Using the approximate Gvd, the stability of the three basic dc–dc converters under leading-edge and trailing-edge PWM is analyzed. It is shown that the stability of the buck converter is unaffected by the type of PWM, while the leading-edge modulated boost and buck–boost converters have better stability than the trailing-edge modulated ones. Since the trailing-edge modulation is commonly available in PWM controller integrated circuits, the modulation signal zero-order holding (ZOH) method and the inductor current feedback control method are proposed for use in the trailing-edge modulated boost and buck–boost converters to achieve the same effect of leading-edge modulated converters. Experimental buck and boost converters were constructed for verification of the accuracy of the proposed model and the validity of the proposed control schemes. [ABSTRACT FROM AUTHOR]

The highly efficient and reliable inverter concept (HERIC) inverter is a cost-effective topology, which has low leakage currents and a relatively high efficiency. Thus, it is very suitable for transformerless photovoltaic systems. However, with the reported modulation methods, it is difficult to simultaneously maintain the high efficiency, good power quality, and reactive power injection of the HERIC inverter. In this paper, a hybrid unipolar pulsewidth modulation (UP-PWM) scheme is thus proposed to achieve those performances. The hybrid scheme adopts the conventional UP-PWM in the case of generating the positive power. When generating the negative power, a modulation scheme, which only requires the operation of freewheeling switches, is specifically proposed. Additionally, in the region of the output voltage and current zero-crossing points, a UP-PWM with modified deadtime is introduced. In order to validate the effectiveness of the proposed scheme, simulations and experiments are performed on a 4-kW HERIC inverter system with a 20-kHz switching frequency. The results demonstrate that the proposed hybrid UP-PWM method achieves a better performance in terms of reactive power injection than the conventional UP-PWM scheme, and a higher efficiency than the UP-PWM with deadtime. In addition, the proposed UP-PWM scheme also enables a better power quality. [ABSTRACT FROM AUTHOR]

In this paper, a fast-processing implementation method of the current-ripple-loss-optimized common-mode voltage reduction pulsewidth modulation (CRLO-CMVRPWM) is studied. With the novel sector definitions and the simplified method to solve the constraint nonlinear programming model, the compute burden of the proposed method is reduced by 82.8% and 50.5% for the case where the modulation index is below and above $4\sqrt 3 /9$ , respectively. In addition, the effects of the optimized zero-sequence voltage errors caused by the adopted linear fitting strategy are proven to be negligible by studying the harmonic characteristics difference between the fast-processing and original CRLO-CMVRPWM. Simulated and experimental results are given to validate the effectiveness. [ABSTRACT FROM AUTHOR]

A fully digital driving circuit for thin-film transistor liquid crystal display can offer benefits, including less power consumption and a shortened design schedule. Using the pulsewidth signal to control the moment to stop the ramp voltage, the pixel voltage can be set accurately. In this paper, the possible issues of power consumption, device nonuniformity, and parasitic capacitance are well-studied to prove the feasibility and advantages of the digital driving method. It is prospectively expected to substitute for the conventional analog driving method in the future. [ABSTRACT FROM AUTHOR]

Interleaved three-phase voltage source converters (VSCs) are widely applied in industry. The circulating current issue has been the focus so far in literature. However, the common-mode voltage (CMV) generated from interleaved VSCs, which is also a key factor that influences the system's performance, has not yet been studied in detail. In this paper, the impact of pulsewidth modulation (PWM) strategies on the CMV of interleaved two-level VSCs is analyzed. The analysis is conducted based on the double Fourier integral theory and in a generalized way considering an arbitrary number of interleaved converters. Five PWM schemes are considered, including the interleaved sinusoidal PWM (ISPWM), the interleaved space vector modulation (ISVM), the interleaved discontinuous PWM (IDPWM), and the recently proposed interleaved carrier phase-shift PWM (ICPS PWM), and interleaved carrier phase-shift SVM (ICPS SVM). Both magnitude and harmonic content of CMV are examined for each method. The analysis reveals that with ISPWM, ISVM, ICPS PWM, and ICPS SVM, the CMV can be reduced. In contrast, interleaving has little impact on the CMV with IDPWM, which is always at VDC/2 due to high low-order harmonics, making it less attractive for drive applications using coupled architecture. For modular architecture, ICPS PWM and ICPS SVM are more desirable considering their low-ZSCC peak value. The study is verified through experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a general control scheme for the dual-input three-level inverter, which comes from a neutral point clamped three-level inverter. It can be used for photovoltaic (PV) systems or battery storage systems with two dc sources. The dual-input three-level inverter can be connected with two PV arrays, which are able to realize maximum power point tracking independently. First, the dynamic model of the dual-input three-level inverter is established, which describes the relationship between the dual-input voltages and the duty cycle. After discussing the control theory of the dual-input voltages, a typical control scheme is proposed. The design of a control loop is introduced in details. Afterward, modulation and restriction of the proposed method are discussed. Finally, experiment on a 125 kW dual-input three-level PV inverter is implemented to verify the validity and feasibility of the proposed method. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) problem brings severe negative effects in three-phase voltage source inverters (VSIs), particularly for high-frequency silicon (Si) carbide (SiC) VSIs. However, most traditional CMV reduction strategies, which are studied based on Si VSIs, are hard to be implemented and sacrifice the other performance of the VSIs. To overcome such drawbacks, this paper proposes a novel generalized tri-state pulsewidth modulation (GTSPWM) for high-frequency SiC VSIs over power factor of 0–1 and whole linear modulation index range. The working principle of conventional space vector based reduced CMV PWM (RCMV-PWM) methods are reviewed, and their switching signals and CMV patterns are illustrated. The proposed GTSPWM method is described in a generalized scalar PWM approach for simple application and compared with other RCMV-PWM methods. Mathematical analysis, simulations, and experimental results have been used to verify that GTSPWM based high-frequency SiC VSIs can achieve minimum switching losses, improved output waveform quality, smaller dc-link current ripples, and RCMV characteristics. Moreover, with the usage of GTSPWM method, the switching frequency of SiC VSIs can be further increased, and the performance of high-frequency SiC VSIs could be improved appreciably. [ABSTRACT FROM AUTHOR]

Most photovoltaic (PV) systems are composed of series and parallel inverters. The electromagnetic interference (EMI) mainly comes from the off–on of inverter switches with pulsewidth modulation (PWM). The output EMI peaks of PV systems would increase markedly due to the interference superposition effect caused by parallel inverters, whose carrier initial phases are in phase or close to each other. In this paper, an auto-screening carrier phase-shift scheme is proposed to weaken the superposition effect of EMI peaks and to get the result of reverse offset at its best. In a PV system, through voltage detections and spectrum estimations of each inverter with a series of phase-shift carriers, a best carrier phase of each inverter is obtained automatically to minimize EMI peaks of the PV system. In order to avoid the conflict that the screening processes of two or more inverters are underway at the same time, a specific frequency signal is output temporarily as an occupancy mark in one of the inverters. The feasibility and effectiveness of the proposed scheme are verified by experimental results in a PV system composed of four parallel single-phase inverters. [ABSTRACT FROM AUTHOR]

In this paper, a new method is applied to predict the average value of the phase currents of a two-level voltage source converter. The method uses a suitable model of the converter, the modulation method, and the measurement. The samples given by the analog-to-digital converter (ADC) are used to predict the time progress of the currents in every switching cycle and then calculate its average. This allows removal of the delay introduced by filtering and avoids aliasing in the measurements. The average prediction is contrasted with the pulsewidth modulation (PWM) synchronous sampling method and the sigma-delta ADC with a moving average filter. Applied to a load observer, the method effectively reduces its estimation error. The findings are verified experimentally. [ABSTRACT FROM AUTHOR]

This paper presents a novel single-phase multicell converter for ac–dc power conversion, which is formed by a series connection of several full-bridge converter stages through passive components. The proposed topology employs a simple control scheme based on the carrier-based sinusoidal pulsewidth modulation technique. Detailed design procedure of the passive filter components are analyzed and discussed. An efficient optimization method based on a differential evolution algorithm is utilized to optimize the filter parameters. Considering the filter structure, active damping is introduced in the control scheme to improve the stability of the overall system, which is later verified by experiments. The systematic design approach of the controller parameter is also highlighted, focusing a specific set of goals. Experimental results for a 1-kW prototype are presented to further validate the concept. [ABSTRACT FROM AUTHOR]

This paper presents an improved analytical model for estimating the high-frequency current ripple of interior permanent magnet synchronous machines due to pulsewidth modulation (PWM) switching. The proposed model accounts for the impact of slotting effect, magnetic saturation, and cross-coupling between the $d$ - and $q$ -axis. The model is subsequently used to investigate several factors that influence the PWM-induced current ripple. These include the PWM switching frequency, fundamental frequency (i.e., machine speed), dc-bus voltage, current control angle (i.e., γ angle), and the excitation current amplitude (i.e., saturation level). Experiments have been conducted to verify the analytical prediction results. These results show that the analytical model can predict the PWM-induced current ripple waveshape very well for many operating conditions and accurately estimate its rms value over a complete fundamental period. [ABSTRACT FROM AUTHOR]

This paper investigates a multilevel inverter composed of series/parallel-connected H-bridges. The presented structure can be used for applications in which the use of semiconductor switches with low-voltage and low-current ratings is intended. A comprehensive system model, an overall control strategy to adjust the output voltage with constant magnitude and frequency, and a level-shifted PWM (LS-PWM) strategy based on a voltage vectors unidimensional analysis and a plane analysis are presented. The LS-PWM is capable of mitigating the low-frequency circulating current, thus generating multilevel voltage signals with low harmonic distortion, maximum number of levels, and low dv/dt. In addition, considering a wide range of values of voltages and currents and various power levels, the total converter losses are reduced compared with the conventional multilevel converters. Two multilevel conventional inverters with the same number of semiconductor switches are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. [ABSTRACT FROM AUTHOR]

This paper illustrates the application of a solving method of linear systems to a multilevel inverter. This study applies a generic pulsewidth modulation (PWM) method to a multilevel topology. This method finally highlights some specific modulation schemes. First, the study describes the mathematical model of the inverter leg. The leg is made of three level T-type structure. The model is extended to the three-phase inverter. The generalized inverse is used to generate the solution set of the conduction rates. Among the modulation strategies possible, three specific modulation schemes are proposed. The modulation schemes are applied to simulate a PWM three-phase inverter. Finally, some experimental results complete the analysis. [ABSTRACT FROM AUTHOR]

A drive train system (DTS) powered by an ideal voltage source and driving a permanent-magnet synchronous motor (PMSM) is discussed in this paper. A two-level three-phase voltage source inverter is used as a means of power conditioning. This converter is not equipped with any harmonic filters on neither the ac nor the dc side. The mechanical part of the DTS is modeled as a double oscillator according to a drive train in an electric vehicle (EV). Various inverter modulation schemes are applied, namely, a single-phase hysteresis scheme, two-space vector-based hysteresis control schemes, for one, a stator aligned hysteresis and for another, a rotor aligned hysteresis, a modulation scheme based on pulsewidth modulation (PWM), such as sinusoidal modulation (including zero-sequence components) and space-vector pulsewidth modulation (SVPWM). The hysteresis-based pulsing methods are nondeterministic and build a current controller in their structure by nature. The other pulsing methods are deterministic due to their underlying PWM and require a separate control unit. The influence of these modulation schemes on the performance of the DTS is determined by assessing the level of inverter generated harmonics flowing to the PMSM and to the tires [downforce, (mechanical part)] as well as the resulting switching frequency (electrical part). The simulated results presented in the paper indicate that the pulsing frequency can be reduced by means of the hysteresis controller. In addition, the dispersion of the harmonic energy of the inverter generated spectrum partly compensate the absence of filters. [ABSTRACT FROM PUBLISHER]

This paper investigates a method to increase fuel economy of motors for an electric vehicle (EV) traction system. The low-torque region of an EV motor is frequently used in everyday urban driving and in fuel economy measurement. Pulsewidth modulation (PWM) carrier harmonic iron loss accounts for a high percentage of total loss for EV motors in this region. This paper reveals the relationship between phase current and carrier harmonic iron loss for a permanent-magnet synchronous motor (PMSM) in the low-torque region. Thus, a novel carrier harmonic loss reduction technique is proposed and applied to two sets of three-phase windings for a concentrated winding PMSM. The loss is successfully reduced in a 70-kW EV motor as well as a two-dimensional finite-element method (2-D-FEM) calculation. The efficiency of the developed motor is calculated and compared with that of a conventional motor in the JC08 mode driving cycle. [ABSTRACT FROM PUBLISHER]

A modular multilevel converter (MMC) is an attractive solution for power conversion without transformers. The MMC consists of cascade connections of floating dc capacitors. In this paper, an adaptive observer design has been proposed to estimate the capacitor voltages from the measurement of arm currents. This work introduces the capacitance value of the cell capacitors as a parameter uncertainty for making the system performance robust with unknown constant parameters. It may be used for predictive control, condition monitoring for capacitors, and diagnosis check for capacitor health. In addition, a pulsewidth modulation (PWM) technique for MMC has been explored. The PWM technique is performed using a carrier-based level-shifted PWM strategy. It does not necessitate the calculation of duty cycles, and can be easily implemented in a DSP. By using the PWM technique, harmonics in the phase voltage is shifted to twice the switching frequency. Theoretical analysis is included in this paper for showing stability and convergence of the proposed observer. Analytical expressions are verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

Conventional zero-voltage and zero-current-switching (ZVZCS) full-bridge converters are widely used because they can realize zero-voltage switching (ZVS) for the leading leg and zero-current switching (ZCS) for the lagging leg. However, the large turn-off loss of the leading leg is still unacceptable in high-voltage high-power applications where insulated-gate bipolar transistors (IGBTs) with current tailing are employed. Hence, it is preferable to achieve ZCS for all IGBTs of full-bridge converters. This paper analyzes the ZCS conditions for pulsewidth modulated (PWM) full-bridge converters and proposes a general strategy for achieving ZCS for main switches, including the control strategy and design method of the topology. Based on this theory, a novel ZCS PWM full-bridge converter with simple auxiliary circuit is derived and tested. It can achieve ZCS not only for the main switches of full-bridge converter, but for the auxiliary switch as well, and obtain high efficiency. The operation principle of the proposed ZCS PWM full-bridge converter and the design procedure are presented. The experimental results of a 600 V/2.5 kW prototype are also included to verify the theoretical analysis. [ABSTRACT FROM PUBLISHER]

The pulsewidth modulation (PWM) technique is commonly used to supply modern high-speed electrical machines. The fundamental frequency is typically in the kilohertz range, with switching frequencies of several tens of kilohertz, as determined by the new SiC- or GaAs-based power transistors modules. Switching introduces minor loops in the major hysteresis cycle, with durations of the order of 100~\mu \texts or lower, with the resulting magnetization dynamics influenced by strong skin effect. However, since these minor loops have relatively small amplitude, their constitutive equation may be described by an equivalent permeability (real or complex), depending on the mean slope of the minor loop and its static energy loss. By retrieving this permeability, the classical loss is straightforwardly calculated by analytical solution of Maxwell's equations. In this paper, we measure and calculate, according to the quasi-linear approximation for the minor loops, the magnetic energy losses of 0.194 mm thick non-oriented Fe–Si 3.2% sheets subjected to PWM induction waveform. Minor loop peak amplitudes ranging between 50 mT and 0.2 T and frequencies up to 10 kHz are investigated. The results are consistent with the proposed model, to within 5%. [ABSTRACT FROM AUTHOR]

This paper presents a new all-digital transceiver architecture fully integrated into a single field-programmable gate array chip. Both the radio frequency (RF) receiver and the transmitter were entirely implemented using a digital datapath from the baseband up to the RF stage without the use of conventional analog-to-digital converter, digital-to-analog converter, or analog mixer. The transmitter chain uses delta-sigma modulation and digital upconversion to produce a two-level RF output signal. The receiver uses a high-speed comparator and pulsewidth modulation to convert the RF signal into a single-bit data stream, which is digitally filtered and then downconverted. Both the transmitter and the receiver are agile with flexible carrier frequency, bandwidth, and modulation capabilities. The transceiver error vector magnitude and the signal-to-noise ratio figures of merit were analyzed in a point-to-point transmission to evaluate the transmitter’s performance. The results show the feasibility of this approach as a more flexible alternative to common radio architectures. [ABSTRACT FROM PUBLISHER]

Due to the inductor–capacitor (LC) filter, a pulsewidth-modulation (PWM) current-source converter may experience LC resonance. The resonance can be excited by system harmonics either from the PWM process or from the grid voltage distortions and hence results in the line current distorted. In this paper, feedback controls using different variables in the LC filter are first investigated and comprehensively analyzed. It is shown that the inductor-voltage feedback or the capacitor-voltage feedback can damp the current oscillations by increasing the damping ratio, while the inductor-current feedback or the capacitor-current feedback is able to suppress low-order harmonics by raising the resonance frequency. On this basis, a group of combined variable feedback control methods is presented by combining the feedbacks of the inductor/capacitor current and the inductor/capacitor voltage. Thus, not only the current oscillations can be damped, but also the low-order harmonics can be suppressed. Therefore, the line current waveform is improved, and the system performance can be flexibly optimized. A practical design method for feedback gains is also presented in this paper. Finally, the simulation and experimental results verify the feasibility and validity of the proposition. [ABSTRACT FROM PUBLISHER]

For variable-speed drives, the interaction of the machine and the converter is becoming increasingly important, especially for high-speed applications, mainly due to the effect of the converter modulation on the machine losses. The allocation of the losses to different components of the drive system needs to be known in order to choose the ideal machine and modulation combination. In this paper, individual models are introduced for calculating the rotor, copper, and core losses of the machine as well as the inverter losses, taking the modulation type into account. These models are developed by considering two typical high-speed permanent-magnet synchronous motor topologies (slotted and slotless machines) driven by pulse-amplitude modulation (PAM) and pulsewidth modulation (PWM) converters. The models are applied to two off-the-shelf machines and a converter operating with either PAM or PWM. The test bench used to experimentally verify the models is also described, and the model results are compared to the measurements. The results show that PAM produces a higher overall efficiency for the high-speed machines considered in this paper. However, PWM can be used to move the losses from the rotor to the converter at the expense of decreasing the overall drive efficiency. The possible benefits of these results are discussed. [ABSTRACT FROM PUBLISHER]

The Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. The unique feature of the ZSI is that it can operate either in buck or boost mode with a wide range of obtainable output voltages from a given input voltage. This topology also exhibits better electromagnetic-interference noise immunity when compared to a traditional voltage-source inverter (VSI). However, the LC impedance network of ZSI significantly increases the size and cost of the power converter and can make it unsuitable for low-power applications. This paper proposes a novel topology called switched boost inverter (SBI) which exhibits similar advantages of ZSI with lower number of passive components and more active components compared to ZSI. The steady-state and small-signal analyses of SBI, along with its pulsewidth modulation (PWM) control strategies, have been discussed in this paper. This paper also presents a comparison of SBI and ZSI with the same input and output parameters. The theoretical analysis given in this paper has been validated using a laboratory prototype of SBI, and the experimental results are presented for verification. The experimental harmonic spectrum of the inverter's output voltage with the proposed PWM technique is also plotted and compared with that of a traditional VSI. All the experimental results show good correlation between theory and experiments. [ABSTRACT FROM PUBLISHER]

A dual two-level voltage source inverter (VSI) can synthesize a three-level voltage space vector employing an open-end winding induction motor. Space-vector-based pulsewidth modulation (PWM) variants for this dual VSI are proposed in this paper that offer the dual advantage of limiting the switching power loss to a single VSI at all instants and also reducing the switching commutations in the dual VSI by 50%. The influence of different error volt seconds (affected with different PWM variants) on the motor phase current in the dual VSI is critically analyzed. To this end, two analytical approaches (one using error-voltage trajectory information and the other using switching state information of the dual VSI) are also proposed in this paper to predict the current trajectory and the ripple content in the drive system. Expressions for rms ripple current are developed with different PWM variants. The efficacy of the proposed analytical approaches to predict the current trajectory and the ripple content is confirmed from the experimental results. All the PWM variants are first simulated using MATLAB and verified experimentally by conducting tests on a three-phase open-end winding induction motor drive controlled with volts per hertz control. The implementation of the PWM algorithms only requires instantaneous magnitudes of three-phase reference voltages and completely avoids the sector identification and lookup tables. [ABSTRACT FROM PUBLISHER]

This paper presents investigations on current ripple in a dual 2-level inverter feeding an open-end winding induction motor drive. Pulsewidth modulations (PWMs) for the independently controlled inverters are implemented using a simple effective time placement affected by offset-time concept, thus, eliminating the use of sector identification and lookup tables. Analytical expressions for ripple content in the motor phase current are developed and a current trajectory is theoretically obtained directly from the switching states of the dual inverter in a stationary reference frame. In addition, this paper also describes a current ripple trajectory in the motor by exploring the freedom of independently operating the individual inverters with different PWMs. Based on the analysis, discontinuous PWMs are employed for the individually inverters that not only offer the advantage of reducing the total switching commutations in the inverters but also reduces the current ripple. Analytical expression for the RMS ripple current and variation in RMS ripple current in one cycle of operation for different PWMs are also presented for the entire speed range of the dual-inverter drive. The performance of the dual-inverter drive with the proposed PWM variants is first studied analytically and then verified by performing suitable experiments on a 1-kW open-end winding induction motor drive. [ABSTRACT FROM AUTHOR]

Pulsewidth modulation (PWM) ac drives generate high line–line motor voltage, up to twice dc bus voltage, due to the reflected-wave phenomenon. Under certain conditions, motor voltage greater than twice the dc bus voltage can occur, resulting in winding insulation failure. It is well known that by suitably adjusting the PWM pulse pattern, the occurrence of voltages greater than twice the dc bus voltage can be avoided, up to a certain maximum cable length; beyond which, output filters are typically used to limit peak motor voltage. It will be shown in this paper that when the inverter operates in the pulse dropping region, voltages greater than twice the dc bus voltage will occur, with existing methods for pulse pattern compensation. A method to adjust the PWM pulse pattern in the pulse dropping region to ensure the same reflected-wave performance as the linear PWM region is presented in this paper. Experimental results are provided to demonstrate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Part I of this paper has proposed a duty-cycle-space-vector (DCSV)-based modulation strategy for three- and four-leg matrix converters (MCs). This paper develops a digital DCSV-based modulation strategy for the three- and four-leg MCs based on the results of Part I of this paper. The digital DCSV-based modulation strategy is implemented in a DSP–field programmable gate array (FPGA) platform. The objective is to reduce the calculation time of the modulation algorithm by performing the following: 1) reducing the total number of instructions needed to implement the modulation algorithm in the DSP and 2) implementing parts of the modulation algorithm in an FPGA to generate the switching pattern. Therefore, the calculation process of the modulation algorithm is split between the DSP and the FPGA. [ABSTRACT FROM PUBLISHER]

This paper provides a theoretical discussion on a new phase-shifted rotating-carrier (PSRC) pulsewidth modulation (PWM) method for a modular multilevel double-star chopper-cell (DSCC) converter. The new method enables the DSCC converter to operate at a low switching frequency in a range of 50 to 100 Hz where the ac grid or line frequency is 50 Hz. The phase shift of each carrier signal is rotated to enable capacitor–voltage balancing in such a low-carrier-frequency range while maintaining the same voltage in each arm as that of the original phase-shifted-carrier PWM. Theoretical analysis of harmonic-voltage spectrum at the arm side of a chopper cell is conducted on the basis of double-variable Fourier series. Then, the analytical results are compared to numerical ones. A three-phase grid-connected DSCC converter rated at 66 kV, 50 Hz, and 100 MW with 64 chopper cells per leg is used in circuit simulation to confirm the validity of the proposed PSRC-PWM method. The simulation results show that the PSRC-PWM can maintain stable operation of the DSCC converter even if the carrier frequency goes lower than 100 Hz. Several performance criteria conclude that the optimal carrier frequency is 75 Hz. [ABSTRACT FROM AUTHOR]

Applying pulsewidth modulation (PWM) to control the gain in audio codecs for mobile applications leads to several advantages, such as the smooth control of tuning parameters, smaller silicon area, and lower power consumption, as compared with other tuning techniques using programmable gain amplifiers and zero crossing detectors. The PWM has to be embedded into the main signal path, preferably in a closed-loop control scheme, in order to exploit its benefits. However, the insertion of dithering and offset controls in a gain setting loop poses the problem of controlling their effects in all gain conditions. This paper reports a novel technique aimed at solving the associated issues and limitations, and provides the experimental proof of the concept through the implementation of a test-chip design on silicon. In particular, this paper reports the design and experimental results of a delta–sigma analog-to-digital converter featuring a click-free gain control technique, dithering insertion, and idle-tone shifting, which has been implemented in a 40-nm complementary metal–oxide–semiconductor technology for commercial telecom audio codec applications. [ABSTRACT FROM PUBLISHER]