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Four-level hybrid-clamped inverter is a newly proposed topology that can operate under a wide voltage range without switches connected in series. However, when it is applied in medium voltage high power conversions, the flying capacitors in each phase will occupy a huge volume and a high switching frequency is required to restrain the voltage ripples. In order to overcome this drawback, a four-level active neutral-point clamped inverter is discussed in this paper, which consists of only six switches and no diodes or flying capacitors are required. In order to balance the neutral-point voltages under the full power factor and modulation index range, a capacitor voltage balance method based on carrier-overlapped pulsewidth modulation is proposed in this paper. The upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection and the central dc-link capacitor voltage is balanced by adjusting the duty cycles of switching signals slightly. Simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n-level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme. [ABSTRACT FROM AUTHOR]

Motors and inverters are increasingly being used in vehicles. As more vehicle components are being adopted, requirement for safety and installation space are increasing. Growing attention is being paid to the use of six-phase permanent magnet synchronous motors (PMSMs) and their parallel control by two inverters, because of their reduced size and enhanced safety. This paper proposes a pulsewidth modulation (PWM) control algorithm for a six-phase PMSM. In low-voltage vehicle components such as electric power steering, the current is usually acquired with resistors placed under the low-side switching devices. In the proposed control algorithm, the neutral voltage of the two inverters is shifted to either a lower or higher voltage within a certain range to allow for the signal conditioning time delay after the switching device turns on or off, and the time taken for the phase current to rise or settle. The paper proposes a novel PWM control algorithm that ensures that the on-time of the low-side switching devices satisfies the restriction on current sensing with resistors and reduces the current in the capacitor at the same time. The work contributes to reducing the current in a practical configuration involving low-voltage vehicle components. [ABSTRACT FROM AUTHOR]

Standard pulsewidth modulation (PWM) schemes for modular multilevel converters (MMC) have neglected deviations of the module voltages from the mean module voltage of an MMC arm as well as the dynamic change in the module voltages since their last measurement and during the switching period. This induces an output voltage error. Large output voltage errors disturb the higher level closed-loop control of the MMC, such that control targets cannot be met anymore. The output voltage error can be reduced using advanced PWM methods that predict and include the dynamic change of the individual module voltages during a switching period in the calculations for the duty cycle. This paper shows measurement results obtained from an experimental medium-voltage prototype, proving that advanced methods lead to much lower output voltage errors than the standard methods, but cannot fulfill the expectations raised by the simulations documented in the literature. In order to overcome the limitations of the old method, a new method that includes the semiconductor voltage drop and parasitic resistances is introduced and evaluated with measurements in this paper. Furthermore, simulation results showing the influence of the considered modulation methods on the closed-loop current control performance are presented. [ABSTRACT FROM AUTHOR]

This paper presents two capacitor voltage balancing (CVB) strategies for modular multilevel converter (MMC) applications. Both balancing schemes are based on model predictive control and are designed to efficiently solve a constrained optimal control problem, where the predicted capacitor voltage errors are included in the cost function with the demanded output voltage of a cluster being forced through an equality constraint. The first method proposed in this paper computes specific modulation indexes for each module using the explicit solution of a relaxed version of the original optimization problem. The second approach proposed in this paper reduces the complexity of the original problem by linearizing the objective function and using an optimal sorting network based on a greedy algorithm to solve this approximation. Considering the structures of both solution approaches, they are integrated into modulation schemes based on phase-shifted and level-shifted pulsewidth modulation algorithms, respectively. Experimental results obtained from a nine-cell single-phase MMC prototype demonstrate the good performance achieved with the proposed methodologies, as well as the implementation simplicity offered by the proposed CVB algorithms. [ABSTRACT FROM AUTHOR]

Induction motor drives operated with a low ratio of the switching frequency to the fundamental frequency (i.e., pulse number) are prone to have high magnitudes of low-order torque harmonics. This paper proposes a method to analytically evaluate the harmonic torque spectrum based on the pulsewidth-modulated voltage waveforms for low pulse number operation. The predicted torque harmonic spectra for different pulsewidth-modulated waveforms are validated through simulations and experiments. This paper also reports optimal switching angles to minimize the total rms value of torque harmonics of order 6, 12, 18 $,\dots,$ $6(N-1)$ , considering the number of switching angles per quarter ($N$) to be 4 and 5. Compared to sine triangle pulsewidth modulation and selective harmonic elimination pulsewidth modulation with the same pulse number, the proposed optimal switching angles significantly reduce the total rms value of all harmonic torques of order lower than $6N$. Extensive simulation and experimental results on a 3.7-kW induction motor drive are presented to demonstrate the superior performance of the proposed optimal pulsewidth modulation. [ABSTRACT FROM AUTHOR]

This paper presents a novel multilevel radio frequency (RF) pulsewidth modulation (PWM) method for all-digital transmitters (ADTx) that actively eliminates the selected harmonics of RF-PWM. Compared with existing multilevel RF-PWM techniques, this method uses several adaptive thresholds and controls the pulsewidth of the corresponding subpulses to make the selected harmonics cancel each other out and keep the fundamental frequency component proportional to input envelope. For the third-harmonic elimination, the corresponding five-level RF-PWM scheme presented in this paper shows that it can significantly relax the filtering requirements and improve the wideband performance of the ADTx. The proposed scheme is verified by extensive simulations and offline measurements. The simulations show good potential for high-frequency operation up to gigahertz ADTx. The measured results show that the third-harmonic suppression of the proposed scheme has increased with the decreasing of the time resolution for digital implementations. For a 3.80-dB peak-to-average power ratio (PAPR) QPSK signal and a 6.04-dB PAPR 16QAM signal at 200-MHz carrier, the proposed scheme can achieve above −51- and −48-dBc third-harmonic suppression, respectively, when the time resolution is 50 ps and relative time resolution is 1%, and improves above 30 dBc to the existing schemes. [ABSTRACT FROM AUTHOR]

In the topology of double-inverter fed wound rotor induction machine (DI-WRIM) two voltage source inverters (VSIs) are connected one each on stator and rotor terminals. This leads to ripple in both stator and rotor currents. In this paper, these current ripples are analyzed in terms of the stator- and rotor-flux ripples, which are estimated from their respective terminals. To reduce the current ripples, the VSIs of the stator and rotor terminals are modulated with different pulsewidth modulation (PWM) sequences. The switching loss in the DI-WRIM is also analyzed for the proposed stator–rotor PWM sequence combinations, based on the flexibility of changing the power factor, by changing the flux component of the current fed from either side of a DI-WRIM drive. The proposed PWM combinations with the proposed flux component in currents are found to reduce the stator and rotor current ripples and, the switching losses. The analytically estimated root mean square current ripples for the proposed PWM combinations are validated using the simulation and the experimental results obtained from a 3-kW DI-WRIM drive. The analysis on switching losses is validated by measuring the temperature rise of heat sinks present in the individual stator and rotor side VSIs of the DI-WRIM drive. [ABSTRACT FROM AUTHOR]

This paper presents a novel fault-tolerant method for active–neutral-point-clamped (ANPC) inverter using a modified carrier-based pulsewidth modulation. At a fault event, the ANPC inverter is divided into subinverters, and the modulating signal is modified to two modulating signals. The modified modulating signals are used to control the subinverters and allow continuous operation of the three-level ANPC inverter during faulty conditions even up to four open-switch faults per phase. This technique provides the fault-tolerant capability of the ANPC inverter without the need to add any additional phase legs or complex control strategies. Furthermore, the proposed technique ensures the voltage balancing of the dc-link capacitors. The performance of the proposed fault-tolerant technique is verified through simulation studies in MATLAB/Simulink under different faulty conditions. The feasibility of the proposed technique is also verified experimentally. [ABSTRACT FROM AUTHOR]

Parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) are widely used due to their distinct advantages of high power delivery, modularity, low current rating devices, etc. Along with these advantages, the parallel interleaved 2L VSIs could also be analyzed as a single three-level (3L) VSI. Conventionally parallel interleaved 2L VSIs are modulated using the 2L pulsewidth modulation (PWM) techniques. However, implementation of parallel interleaved 2L VSIs using the 2L PWM techniques may generate a higher ac side current ripple as compared to implementing the parallel interleaved 2L VSIs using 3L PWM techniques. This paper proposes a carrier-based method for implementing different 3L discontinuous PWM (DPWM) techniques for parallel interleaved 2L three-phase VSIs. Comparison of different 2L switching sequences for implementing a 3L DPWM switching sequence based on circulating current, line current ripple, and switching loss is also carried out. Simulation and experimental results are also displayed to validate the proposal. [ABSTRACT FROM AUTHOR]

Two parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) can be analyzed as a single three-level (3L) VSI. A generalized carrier-based method is proposed in this paper for implementing different 3L pulsewidth modulation (PWM) techniques using two parallel interleaved 2L VSIs. The proposed method modifies the given three-phase reference signals of 3L VSI for implementation of the PWM technique using two parallel interleaved 2L VSIs. The influence of nonidealities on the equivalent 3L PWM switching sequences is also discussed. To overcome the effect of nonidealities, a new modified discontinuous PWM technique (MDPWM1) is proposed. The analysis of different performance indices is carried out for different 3L PWM techniques, and the key advantages of different PWM techniques are identified. Simulation and experimental results are also presented. [ABSTRACT FROM AUTHOR]

It is generally known that averaged models are inadequate in describing the effects of leading-edge and trailing-edge pulsewidth modulation (PWM) on the stability of dc–dc converters. In this paper, using discrete-time models of the buck, boost, and buck–boost converters and considering the effects of leading-edge and trailing-edge PWM, the general expressions of the duty-cycle-to-output-voltage transfer function, Gvd(z), in the discrete-time domain are derived. Based on the low-pass characteristics of the dc-dc converters and related properties of the matrix functions, approximate expressions of Gvd in the frequency domain are derived, which are simple and accurate up to half the switching frequency. Using the approximate Gvd, the stability of the three basic dc–dc converters under leading-edge and trailing-edge PWM is analyzed. It is shown that the stability of the buck converter is unaffected by the type of PWM, while the leading-edge modulated boost and buck–boost converters have better stability than the trailing-edge modulated ones. Since the trailing-edge modulation is commonly available in PWM controller integrated circuits, the modulation signal zero-order holding (ZOH) method and the inductor current feedback control method are proposed for use in the trailing-edge modulated boost and buck–boost converters to achieve the same effect of leading-edge modulated converters. Experimental buck and boost converters were constructed for verification of the accuracy of the proposed model and the validity of the proposed control schemes. [ABSTRACT FROM AUTHOR]

A fully digital driving circuit for thin-film transistor liquid crystal display can offer benefits, including less power consumption and a shortened design schedule. Using the pulsewidth signal to control the moment to stop the ramp voltage, the pixel voltage can be set accurately. In this paper, the possible issues of power consumption, device nonuniformity, and parasitic capacitance are well-studied to prove the feasibility and advantages of the digital driving method. It is prospectively expected to substitute for the conventional analog driving method in the future. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) problem brings severe negative effects in three-phase voltage source inverters (VSIs), particularly for high-frequency silicon (Si) carbide (SiC) VSIs. However, most traditional CMV reduction strategies, which are studied based on Si VSIs, are hard to be implemented and sacrifice the other performance of the VSIs. To overcome such drawbacks, this paper proposes a novel generalized tri-state pulsewidth modulation (GTSPWM) for high-frequency SiC VSIs over power factor of 0–1 and whole linear modulation index range. The working principle of conventional space vector based reduced CMV PWM (RCMV-PWM) methods are reviewed, and their switching signals and CMV patterns are illustrated. The proposed GTSPWM method is described in a generalized scalar PWM approach for simple application and compared with other RCMV-PWM methods. Mathematical analysis, simulations, and experimental results have been used to verify that GTSPWM based high-frequency SiC VSIs can achieve minimum switching losses, improved output waveform quality, smaller dc-link current ripples, and RCMV characteristics. Moreover, with the usage of GTSPWM method, the switching frequency of SiC VSIs can be further increased, and the performance of high-frequency SiC VSIs could be improved appreciably. [ABSTRACT FROM AUTHOR]

Most photovoltaic (PV) systems are composed of series and parallel inverters. The electromagnetic interference (EMI) mainly comes from the off–on of inverter switches with pulsewidth modulation (PWM). The output EMI peaks of PV systems would increase markedly due to the interference superposition effect caused by parallel inverters, whose carrier initial phases are in phase or close to each other. In this paper, an auto-screening carrier phase-shift scheme is proposed to weaken the superposition effect of EMI peaks and to get the result of reverse offset at its best. In a PV system, through voltage detections and spectrum estimations of each inverter with a series of phase-shift carriers, a best carrier phase of each inverter is obtained automatically to minimize EMI peaks of the PV system. In order to avoid the conflict that the screening processes of two or more inverters are underway at the same time, a specific frequency signal is output temporarily as an occupancy mark in one of the inverters. The feasibility and effectiveness of the proposed scheme are verified by experimental results in a PV system composed of four parallel single-phase inverters. [ABSTRACT FROM AUTHOR]

In this paper, a new method is applied to predict the average value of the phase currents of a two-level voltage source converter. The method uses a suitable model of the converter, the modulation method, and the measurement. The samples given by the analog-to-digital converter (ADC) are used to predict the time progress of the currents in every switching cycle and then calculate its average. This allows removal of the delay introduced by filtering and avoids aliasing in the measurements. The average prediction is contrasted with the pulsewidth modulation (PWM) synchronous sampling method and the sigma-delta ADC with a moving average filter. Applied to a load observer, the method effectively reduces its estimation error. The findings are verified experimentally. [ABSTRACT FROM AUTHOR]

This paper presents an improved analytical model for estimating the high-frequency current ripple of interior permanent magnet synchronous machines due to pulsewidth modulation (PWM) switching. The proposed model accounts for the impact of slotting effect, magnetic saturation, and cross-coupling between the $d$ - and $q$ -axis. The model is subsequently used to investigate several factors that influence the PWM-induced current ripple. These include the PWM switching frequency, fundamental frequency (i.e., machine speed), dc-bus voltage, current control angle (i.e., γ angle), and the excitation current amplitude (i.e., saturation level). Experiments have been conducted to verify the analytical prediction results. These results show that the analytical model can predict the PWM-induced current ripple waveshape very well for many operating conditions and accurately estimate its rms value over a complete fundamental period. [ABSTRACT FROM AUTHOR]

This paper investigates a multilevel inverter composed of series/parallel-connected H-bridges. The presented structure can be used for applications in which the use of semiconductor switches with low-voltage and low-current ratings is intended. A comprehensive system model, an overall control strategy to adjust the output voltage with constant magnitude and frequency, and a level-shifted PWM (LS-PWM) strategy based on a voltage vectors unidimensional analysis and a plane analysis are presented. The LS-PWM is capable of mitigating the low-frequency circulating current, thus generating multilevel voltage signals with low harmonic distortion, maximum number of levels, and low dv/dt. In addition, considering a wide range of values of voltages and currents and various power levels, the total converter losses are reduced compared with the conventional multilevel converters. Two multilevel conventional inverters with the same number of semiconductor switches are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. [ABSTRACT FROM AUTHOR]

This paper illustrates the application of a solving method of linear systems to a multilevel inverter. This study applies a generic pulsewidth modulation (PWM) method to a multilevel topology. This method finally highlights some specific modulation schemes. First, the study describes the mathematical model of the inverter leg. The leg is made of three level T-type structure. The model is extended to the three-phase inverter. The generalized inverse is used to generate the solution set of the conduction rates. Among the modulation strategies possible, three specific modulation schemes are proposed. The modulation schemes are applied to simulate a PWM three-phase inverter. Finally, some experimental results complete the analysis. [ABSTRACT FROM AUTHOR]

Conventional zero-voltage and zero-current-switching (ZVZCS) full-bridge converters are widely used because they can realize zero-voltage switching (ZVS) for the leading leg and zero-current switching (ZCS) for the lagging leg. However, the large turn-off loss of the leading leg is still unacceptable in high-voltage high-power applications where insulated-gate bipolar transistors (IGBTs) with current tailing are employed. Hence, it is preferable to achieve ZCS for all IGBTs of full-bridge converters. This paper analyzes the ZCS conditions for pulsewidth modulated (PWM) full-bridge converters and proposes a general strategy for achieving ZCS for main switches, including the control strategy and design method of the topology. Based on this theory, a novel ZCS PWM full-bridge converter with simple auxiliary circuit is derived and tested. It can achieve ZCS not only for the main switches of full-bridge converter, but for the auxiliary switch as well, and obtain high efficiency. The operation principle of the proposed ZCS PWM full-bridge converter and the design procedure are presented. The experimental results of a 600 V/2.5 kW prototype are also included to verify the theoretical analysis. [ABSTRACT FROM PUBLISHER]

The Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. The unique feature of the ZSI is that it can operate either in buck or boost mode with a wide range of obtainable output voltages from a given input voltage. This topology also exhibits better electromagnetic-interference noise immunity when compared to a traditional voltage-source inverter (VSI). However, the LC impedance network of ZSI significantly increases the size and cost of the power converter and can make it unsuitable for low-power applications. This paper proposes a novel topology called switched boost inverter (SBI) which exhibits similar advantages of ZSI with lower number of passive components and more active components compared to ZSI. The steady-state and small-signal analyses of SBI, along with its pulsewidth modulation (PWM) control strategies, have been discussed in this paper. This paper also presents a comparison of SBI and ZSI with the same input and output parameters. The theoretical analysis given in this paper has been validated using a laboratory prototype of SBI, and the experimental results are presented for verification. The experimental harmonic spectrum of the inverter's output voltage with the proposed PWM technique is also plotted and compared with that of a traditional VSI. All the experimental results show good correlation between theory and experiments. [ABSTRACT FROM PUBLISHER]

A dual two-level voltage source inverter (VSI) can synthesize a three-level voltage space vector employing an open-end winding induction motor. Space-vector-based pulsewidth modulation (PWM) variants for this dual VSI are proposed in this paper that offer the dual advantage of limiting the switching power loss to a single VSI at all instants and also reducing the switching commutations in the dual VSI by 50%. The influence of different error volt seconds (affected with different PWM variants) on the motor phase current in the dual VSI is critically analyzed. To this end, two analytical approaches (one using error-voltage trajectory information and the other using switching state information of the dual VSI) are also proposed in this paper to predict the current trajectory and the ripple content in the drive system. Expressions for rms ripple current are developed with different PWM variants. The efficacy of the proposed analytical approaches to predict the current trajectory and the ripple content is confirmed from the experimental results. All the PWM variants are first simulated using MATLAB and verified experimentally by conducting tests on a three-phase open-end winding induction motor drive controlled with volts per hertz control. The implementation of the PWM algorithms only requires instantaneous magnitudes of three-phase reference voltages and completely avoids the sector identification and lookup tables. [ABSTRACT FROM PUBLISHER]

This paper presents investigations on current ripple in a dual 2-level inverter feeding an open-end winding induction motor drive. Pulsewidth modulations (PWMs) for the independently controlled inverters are implemented using a simple effective time placement affected by offset-time concept, thus, eliminating the use of sector identification and lookup tables. Analytical expressions for ripple content in the motor phase current are developed and a current trajectory is theoretically obtained directly from the switching states of the dual inverter in a stationary reference frame. In addition, this paper also describes a current ripple trajectory in the motor by exploring the freedom of independently operating the individual inverters with different PWMs. Based on the analysis, discontinuous PWMs are employed for the individually inverters that not only offer the advantage of reducing the total switching commutations in the inverters but also reduces the current ripple. Analytical expression for the RMS ripple current and variation in RMS ripple current in one cycle of operation for different PWMs are also presented for the entire speed range of the dual-inverter drive. The performance of the dual-inverter drive with the proposed PWM variants is first studied analytically and then verified by performing suitable experiments on a 1-kW open-end winding induction motor drive. [ABSTRACT FROM AUTHOR]

Pulsewidth modulation (PWM) ac drives generate high line–line motor voltage, up to twice dc bus voltage, due to the reflected-wave phenomenon. Under certain conditions, motor voltage greater than twice the dc bus voltage can occur, resulting in winding insulation failure. It is well known that by suitably adjusting the PWM pulse pattern, the occurrence of voltages greater than twice the dc bus voltage can be avoided, up to a certain maximum cable length; beyond which, output filters are typically used to limit peak motor voltage. It will be shown in this paper that when the inverter operates in the pulse dropping region, voltages greater than twice the dc bus voltage will occur, with existing methods for pulse pattern compensation. A method to adjust the PWM pulse pattern in the pulse dropping region to ensure the same reflected-wave performance as the linear PWM region is presented in this paper. Experimental results are provided to demonstrate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Part I of this paper has proposed a duty-cycle-space-vector (DCSV)-based modulation strategy for three- and four-leg matrix converters (MCs). This paper develops a digital DCSV-based modulation strategy for the three- and four-leg MCs based on the results of Part I of this paper. The digital DCSV-based modulation strategy is implemented in a DSP–field programmable gate array (FPGA) platform. The objective is to reduce the calculation time of the modulation algorithm by performing the following: 1) reducing the total number of instructions needed to implement the modulation algorithm in the DSP and 2) implementing parts of the modulation algorithm in an FPGA to generate the switching pattern. Therefore, the calculation process of the modulation algorithm is split between the DSP and the FPGA. [ABSTRACT FROM PUBLISHER]

Applying pulsewidth modulation (PWM) to control the gain in audio codecs for mobile applications leads to several advantages, such as the smooth control of tuning parameters, smaller silicon area, and lower power consumption, as compared with other tuning techniques using programmable gain amplifiers and zero crossing detectors. The PWM has to be embedded into the main signal path, preferably in a closed-loop control scheme, in order to exploit its benefits. However, the insertion of dithering and offset controls in a gain setting loop poses the problem of controlling their effects in all gain conditions. This paper reports a novel technique aimed at solving the associated issues and limitations, and provides the experimental proof of the concept through the implementation of a test-chip design on silicon. In particular, this paper reports the design and experimental results of a delta–sigma analog-to-digital converter featuring a click-free gain control technique, dithering insertion, and idle-tone shifting, which has been implemented in a 40-nm complementary metal–oxide–semiconductor technology for commercial telecom audio codec applications. [ABSTRACT FROM PUBLISHER]

Several pulsewidth modulation (PWM) strategies have been proposed for three-phase multilevel converters. Typically, these PWM methods can be either space-vector or carrier-based implemented, where the carrier-based implementation usually presents a lower computation complexity. In this paper, a novel approach for the carrier-based implementation of different existing PWM methods is proposed for three- (3L) and four-level (4L) dc–ac converters, which can be easily extended to any number of levels. The main features of the proposed approach are its reduced computation complexity and computation time. On the other hand, the proposed approach suggests the derivation of novel PWM strategies which can potentially present improved performance features. As an example, two new discontinuous PWM (DPWM) strategies are proposed for the 4L converter. One of these DPWM strategies presents lower weighted total harmonic distortion than other previously proposed strategies. Simulation and experimental results verify the effectiveness of the proposed approach and novel DPWM strategies. [ABSTRACT FROM AUTHOR]

Variable-speed multiphase (more than three phases) drive systems are seen as serious contenders to the existing three-phase drives due to their distinct advantages. Supply to the multiphase drives is invariably given from a voltage source inverter. However, this paper proposes an alternative solution for supplying multiphase drive system using a direct ac–ac converter called a matrix converter. This paper proposes the pulsewidth modulation (PWM) algorithm for the matrix converter topology with three-phase grid input and five-phase variable-voltage and variable-frequency output. The PWM control technique developed and presented in this paper is based on space vector approach. This paper presents the complete space vector model of the three-to-five-phase matrix converter topology. The space vector model yield 2^15 total switching combinations which reduce to 243 states considering the imposed constraints, out of which 240 are active and 3 are zero vectors. However, for space vector PWM (SVPWM) implementation, only 90 active and 3 zero vectors can be used. The SVPWM algorithm is presented in this paper. The viability of the proposed solution is proved using analytical, simulation, and experimental approaches. [ABSTRACT FROM AUTHOR]

Multimodule converter-based high-voltage dc (HVDC) power transmission incorporates numerous voltage-source converters (VSCs) connected in series/parallel to provide increased voltage/current and, hence, power ratings. When a selective harmonic elimination pulsewidth-modulation (SHE-PWM) technique is employed, the switching losses of the VSC modules are reduced but the voltages of the series-connected dc capacitors are not naturally balanced. In this paper, a voltage-balancing technique is reported. The technique relies on monitoring the voltage of each dc capacitor and when such voltage exceeds its preset band, the realization of the multilevel waveform reallocates the task to another VSC module to ensure that voltage balance between all capacitors is achieved. Three-phase bipolar VSC modules are considered in this paper and each one is modulated by a precalculated multilevel SHE-PWM waveform. The time-domain waveforms and their line-to-line voltage spectra are verified by simulation using PSCAD/EMTDC. The selected results are presented to confirm the viability of the proposed method. [ABSTRACT FROM PUBLISHER]

This paper proposes a new space-vector pulsewidth modulation (SV-PWM) strategy for a three-level neutral point clamped inverter. The presented SV-PWM strategy makes it possible to control the neutral point voltage by optimum choice of switch sequence for any position and length of output voltage vector. The proposed solution takes into consideration the unbalance of the dc-link voltages. It also analyzes the influence of vector sequences on the predicted unbalance of the dc-link voltage. The solution allows selecting optimum vectors and their on-time durations in order to reduce quickly the dc-link voltage unbalance. The calculation of the space vector area proposed in this paper takes into consideration voltage unbalance and its influence on the length and position of vectors. The proposed approach assures properly generating the voltage output vectors, even in the case of the existing large voltage unbalance in the dc-link. The results of the experimental investigation of the proposed modulation strategy are presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper proposes the sliding-mode (SM) control method for the pulsewidth modulation –pulse frequency modulation (PWM–PFM) converters, in which both the duty cycle and the switching frequency are utilized as control parameters. Being different from the conventional PWM–PFM modulator, the proposed method utilizes a direct hysteresis modulation (HM) SM controller to perform the PWM, and, meanwhile, employs a quasi-indirect SM controller to control the bandwidth of the HM, so as to realize the PFM. With the proposed method, the control circuit is of low cost and is simple but the transient and steady responses are still satisfactory. The design, simplification, and implementation of the proposed SM control method are illustrated by using a typical single-switch-double-buck converter in this paper. The experimental results agree well with the analysis and show the validity of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a novel topology for a direct ac–ac power converter, called as the “three-to- k” phase matrix converter. The input to the proposed matrix converter configuration is a three-phase fixed voltage and a fixed frequency supply from the grid. The output is a variable voltage and variable frequency ac supply of any number of phases (k phase). However, the discussion is limited here for a k that is equal to odd number of phases. As an example, a “three-to-five” phase matrix converter is utilized for discussion and analysis. This paper also proposes two pulsewidth modulation (PWM) control techniques for the general topology of the “three-to- k” phase matrix converter. This is based on the so-called direct duty ratio PWM (DPWM). In one presented technique, the output voltage is limited to one half of the input voltage. For the other proposed scheme, the output voltage is enhanced to 78.86% of the input voltage. The proposed control algorithm is validated using simulation and an experimental approach. [ABSTRACT FROM AUTHOR]

A family of isolated buck–boost dc/dc converter for wide input-voltage range is proposed in this paper, and the full-bridge (FB) boost converter, being one of the typical topologies, is analyzed. Due to the existence of the resonant inductor (including the leakage inductor), the FB-boost converter can only adopt the two-edge-modulation (TEM) scheme with the FB cell being leading-edge modulated and the boost cell being trailing-edge modulated to minimize the inductor current ripple over the input-voltage range, and a phase-shift-control-scheme-based TEM with the use of the market available controller IC such as UC3895 is proposed, which realizes phase-shifted control for the FB cell to achieve zero-voltage switching. In order to improve the reliability and efficiency of the FB-boost converter, a three-mode dual-frequency control scheme is proposed, in which the FB-boost converter operates in boost, FB-boost and FB modes in low, medium and high input voltage regions, respectively, and for which the expression of the inductor current ripple is derived in this paper. As the input voltage in the FB-boost mode is close to the output voltage, the inductor current ripple in this mode is much smaller than that in the other modes, and the switching frequency of the boost cell in this mode can be lowered to one-(2N+1)th of the preset switching frequency to reduce the switching loss, and hence, to improve the efficiency. A 250–500 V input, 360 V output, and 6 kW rated power prototype is fabricated to verify the effectiveness of the design and control method. The average efficiency over the input-voltage range is 96.5%, and the highest efficiency attained is 97.2%. [ABSTRACT FROM AUTHOR]

This paper presents a current soft-commutation pulsewidth modulation (PWM) scheme for three-phase current source converter. With the presented PWM scheme, the incoming switch has a positive collector-to-emitter voltage while the outgoing switch has a negative collector-to-emitter voltage during current commutations. Therefore, natural soft commutations for switching transitions are achieved, while current-commutating durations are also lessened. Moreover, some particular advantages can also be obtained such as reduced switching frequency, high dc current utilization ratio, and in-phase transfer between line currents and their references. For more efficient control, this paper then designs logic equations for mapping out the assignments from references to gating signals, allowing a simple implementation using a digital signal processor or a programmable logic device. The theoretical analysis is verified by experimental results. [ABSTRACT FROM AUTHOR]

A matrix converter interfaces with three-phase ac voltage source, which creates three different virtual dc-link voltages. In this paper, a new pulsewidth modulation (PWM) method for the matrix converter is proposed to generally use these three virtual dc-link voltages. By using the two higher line-to-line voltages as the virtual dc-link voltages, the proposed method can create the identical switching sequences to those created by the conventional space vector PWM (SVPWM) method. Moreover, the proposed method is able to select the appropriate virtual dc-link voltage, according to the PWM purpose and/or load condition. In this paper, the virtual dc-link voltages adjacent to the output voltage reference are introduced to reduce output-current switching ripples. The feasibility of the proposed PWM method was verified by a computer simulation and experimental results. The output voltage and current waveforms produced by using the proposed method can be equal or better than those created using the conventional SVPWM method. Moreover, a new switching sequence that reduces output-current switching ripple can be easily adopted within the proposed PWM method. The harmonic characteristics of output current created using the proposed method are markedly improved over those using the conventional PWM method. [ABSTRACT FROM PUBLISHER]

The large number of voltage levels in a modular multilevel converter (MMC) make staircase modulation a feasible alternative, particularly in high-power applications. However, staircase waveforms do not necessarily mean operation of the MMC submodules (SMs) at the fundamental frequency. This paper presents an analysis of SM switching frequencies in staircase-modulated MMCs and their correlation to the modulation index and load phase angle. A carrier-based pulsewidth-modulation (CB-PWM) equivalent technique is also developed. This analysis demonstrates that CB-PWM techniques provide a similar switching frequency with superior harmonic performance and improved voltage balancing characteristics at all modulation indices compared to staircase modulation. The theoretical analysis is verified with extensive simulation results for MMCs with different SMs and experimental results from a laboratory prototype. [ABSTRACT FROM PUBLISHER]

This paper introduces a fault detection and isolation (FDI) method for faulty metal–oxide–semiconductor field-effect transistors in a three-phase pulsewidth-modulated (PWM) voltage source inverter. Short-circuit switch faults are the leading cause of failure in power converters. It is extremely vital to detect them in the early stages to prevent unwanted shutdown and catastrophic failures in motor drives and power generation systems. Against the common FDI methods for power electronic inverters that use phase currents and PWM gate control signals, the proposed method only uses the inverter output voltages. This method analyzes the PWM switching signals in a time-free domain that is called the voltage space. For a healthy inverter, the projection of the state transitions in the voltage space results in a cubic pattern. Each short-circuit switch fault uniquely changes the voltage-space pattern that allows isolating the faulty switch. The fault detection time is only within one PWM carrier period, which is significantly faster than current-based conventional methods. The FDI result does not depend on the load, the PWM switching frequency, and the feedback loop. This method can address the reliability problem of multilevel inverters in renewable electrical generation systems and can dramatically reduce the number of required sensors. [ABSTRACT FROM PUBLISHER]

The high-power voltage source inverters are switched at low frequency to reduce the losses in the inverter. The discontinuous pulsewidth-modulation (PWM) sequences reduce the switching frequency to two-thirds compared to the conventional continuous PWM sequences. At low switching frequency, the output will be rich in harmonics, and synchronization is a must to avoid subharmonics. This paper presents four basic types of synchronized discontinuous PWM (DPWM) sequences that ensure synchronization, three-phase symmetry, and half-wave symmetry. The proposed synchronized DPWM sequences are verified through simulation and experiment on a constant- v/f open-loop induction motor drive. The performance of the proposed DPWM algorithms is studied in the entire modulation region, including the overmodulation region, and is compared with that of the conventional synchronized space vector PWM. A different type of DPWM with low common-mode voltage is suggested for low-modulation region and verified experimentally. [ABSTRACT FROM PUBLISHER]

This paper presents a multilevel inverter that has been conceptualized to reduce component count, particularly for a large number of output levels. It comprises floating input dc sources alternately connected in opposite polarities with one another through power switches. Each input dc level appears in the stepped load voltage either individually or in additive combinations with other input levels. This approach results in reduced number of power switches as compared to classical topologies. The working principle of the proposed topology is demonstrated with the help of a single-phase five-level inverter. The topology is investigated through simulations and validated experimentally on a laboratory prototype. An exhaustive comparison of the proposed topology is made against the classical cascaded H-bridge topology. [ABSTRACT FROM PUBLISHER]

This paper proposes the pulsewidth modulation (PWM) strategy of Z-source inverters (ZSIs) with minimum inductor current ripple. In existing PWM strategy with single-phase shoot-through, the shoot-through time interval is divided into six equal parts, therefore the three phase legs bear the equal shoot-through time interval. In this manner, the allotment and arrangement of the shoot-through state is easy to realize, but the inductor current ripple is not optimized. This causes to use relatively large inductors. In the proposed PWM strategy, the shoot-through time intervals of three phase legs are calculated and rearranged according to the active state and zero state time intervals to achieve the minimum current ripple across the Z-source inductor, while maintaining the same total shoot-through time interval. The principle of the proposed PWM strategy is analyzed in detail, and the comparison of current ripple under the traditional and proposed PWM strategy is given. Simulation and experimental results on the series ZSI are shown to verify the analysis. [ABSTRACT FROM PUBLISHER]

This paper proposes a zero-voltage switching (ZVS) pulsewidth modulation (PWM) dc/dc converter with current double rectifiers to achieve ZVS for all switches under a wide range of load conditions and input voltages. Two three-level PWM circuits sharing the same power switches are adopted in the proposed converter to reduce the voltage stress of each MOSFET at Vin/2 and achieve load current sharing. Thus, the current stress and power rating at the secondary-side components are reduced. The current double rectifiers are used at the secondary side to partially cancel the output ripple current. Thus, the sizes of the magnetic components and output filter capacitance are reduced. Due to the resonant behavior by the resonant inductance and resonant capacitance at the transition interval, all switches are turned on at ZVS. The experimental results based on a 1-kW prototype are provided to verify the operation principle of the proposed converter. [ABSTRACT FROM PUBLISHER]

This paper presents a soft-switching pulsewidth modulation (PWM) nonisolated boost dc–dc converter embedding an edge-resonant switched capacitor (ER-SWC) cell and its interleaved circuit topology. The conceptual boost dc–dc converter treated herein can achieve high-frequency zero-current soft-switching turn-on and zero-voltage soft-switching turn-off operations in the active switches and minimization of a reverse recovering current in the freewheeling diode under discontinuous conduction mode partially including critical conduction mode in the input current. Those advantageous properties enable a wide range of soft-switching operations together with a high-voltage step-up conversion ratio with a reduced current stress. Circuit design guideline based on the soft-switching range is introduced; then, a theoretical analysis is carried out for investigating the step-up voltage conversion ratio. For demonstrating the effectiveness of the ER-SWC soft-switching PWM boost dc–dc converter and its newly developed interleaved topology, laboratory prototypes are evaluated in experiments; then, their performances are discussed from a practical point of view. [ABSTRACT FROM PUBLISHER]

A neutral-point-clamped three-level inverter with small dc-link capacitors is presented in this paper. The inverter requires zero average neutral-point current for stable neutral-point voltage. The small dc-link capacitors may not maintain capacitor voltage balance, even with zero neutral-point current. This may happen due to nonlinearities present in the circuit. This requires a fast control of the neutral-point voltage. A simple carrier-based modulation strategy which allows modeling of the neutral-point voltage dynamics as a continuous function of power drawn from the inverter is proposed. This continuous model shows that the neutral-point current is proportional to the power drawn from the inverter, and it enables the use of a well-established classical control theory for the neutral-point voltage controller design. A simple proportional integral controller is designed for the neutral-point voltage control on the basis of the continuous model. The design method for optimum performance is discussed. The implementation of the proposed modulation strategy and the controller is very simple. The controller is implemented in a 7.5-kW induction machine-based drive with only 14 \mu \F dc-link capacitors. Also, the experimental results show that fast and stable performance of the neutral-point voltage controller are achieved and thus verify the validity of the proposed control approach. [ABSTRACT FROM PUBLISHER]

This paper proposes a new modulation technique that can reduce the current distortion and extend the current reconstruction range for a three-phase inverter using only dc-link sensor. The proposed pulsewidth modulation (PWM) technique is a hybrid method which consists of space vector modulation method and the PWM method without using null switching states. The former provides low current distortion; however, it is with narrower current reconstruction range. In contrast, the latter extends the current reconstruction range at the cost of higher current distortion. For the proposed method, in the measurable region of space vector modulation method, space vector modulation is used to reduce the current distortion. Moreover, as the modulation range is out of the measurable region, the PWM method without using null switching states is applied to extend the current reconstruction range. Furthermore, the current reconstruction limitation using only dc-link sensor is analyzed. The analysis shows that the reduction of PWM switching frequency and acquisition time can extend the current reconstruction range. Comparison of experimental results derived from a field-programmable gate array-based controlled inverter is included. It will be demonstrated that using the proposed hybrid PWM technique, the three-phase current signals of the inverter can be reconstructed even under very low modulation index range while providing low current harmonic distortion of inverter output. [ABSTRACT FROM AUTHOR]

This paper discusses two overmodulation controls, namely, square wave and trapezoidal, in the indirect matrix converter (IMC) for motor drive application. The differences between these two modulations are analyzed based on the output–input voltage transfer ratio (VTR), the efficiency, and the current total harmonic distortions under two load conditions. Moreover, the performance is then improved by implementing four-step commutation methods in the primary side of the IMC. The validity of the proposed methods will be demonstrated through simulation and experimentally. The experimental results show that the VTR can be improved from 0.866 to 0.97 in the square wave modulation and 0.92 for the trapezoidal wave modulation in an induction motor drive system. [ABSTRACT FROM PUBLISHER]

A modified single-phase quasi-Z-source ac-ac converter is proposed in this paper. The proposed converter has the main features in that the output voltage can be bucked or boosted and be both in-phase and out-of-phase with the input voltage. The input voltage and output voltage share the same ground, the size of a converter is reduced, and it operates in a continuous current mode. A safe-commutation strategy for the modified single-phase quasi-Z-source ac-ac converter is used instead of a snubber circuit. The operating principles and a steady-state analysis are presented. A laboratory prototype, tested using a resistive load, a passive load, and a nonlinear load, was constructed that used an input voltage of 70 Vrms /60 Hz in order to verify the performance of the modified single-phase quasi-Z-source ac-ac converter. The experimental results verified that the converter has a lower input current total harmonic distortion, a higher input power factor, and a higher efficiency in comparison to a conventional single-phase Z-source ac-ac converter. In addition, the experimental results show that the use of the safe-commutation strategy is a significant improvement, as it makes it possible to avoid voltage spikes on the switches. [ABSTRACT FROM AUTHOR]

This paper presents a feasibility investigation of a zero-voltage switching (ZVS) pulsewidth modulation (PWM) dc-dc converter with secondary-side phase-shifting power control scheme. The ZVS-PWM dc-dc converter treated here can achieve soft commutation in all the power devices under the wide range of output power variation. By the phase-shifting control that is based on the secondary-side rectifier linked with a high-frequency planar transformer, the effective reduction of idling power in the primary-side inverter as well as snubber-less rectifications in the secondary-side rectifier can be actually attained. The essential experimental data obtained from a 100-kHz/2.5-kW prototype are described herein to validate the soft-switching circuit and control scheme, and then the effectiveness of the dc-dc converter is discussed and evaluated from a practical point of view. [ABSTRACT FROM AUTHOR]

A five-level flying-capacitor (FC)-based active-neutral-point-clamped (ANPC) converter is an arrangement of a three-level ANPC converter and a two-level cell. In this paper, a control strategy is proposed to regulate the voltage across the FCs at their respective reference voltage levels by swapping the switching patterns of the switches based on the polarity of the output current, the polarity of the FC voltage, and the polarity of the fundamental line-to-neutral voltage under selective harmonic elimination pulsewidth modulation. The voltage across the FCs and the dc-link capacitors are simultaneously controlled at their reference voltage levels. The proposed control strategy is applied using power system computer aided design/electromagnetic transients including dc on a static synchronous compensator operating under a power-factor-correction mode to verify its performance. Experimental results are also presented for low and high number of angles per quarter period using a low-power laboratory prototype. [ABSTRACT FROM AUTHOR]

In this paper, a new three-level (3L) converter is presented. It is called 3L Vienna neutral-point-clamped (3L-VNPC) converter and consists of two stacked high-frequency (HF) commutation cells working with a shared power device. The HF cells are connected to a single-phase switched bridge controlled at low frequency. The 3L-VNPC topology is extended to 3L active VNPC (3L-AVNPC) concept, which is generalized for five levels (5L) and N odd voltage levels (N \L). The proposed multilevel converters can be seen as two cascaded voltage stages. The high-voltage stage is specific to the single-phase switched bridge, while the low-voltage (LV) stage corresponds to the stacked HF cells with shared power devices. The new concept AVNPC is a useful and suitable solution for medium-voltage applications, where small modulation index (M) is as crucial as large M. The analyses of the new converters are verified by simulations both for 3L and for 5L topologies, and their features are generalized for N\L. Experimental results for single-phase 3L-AVNPC converter on an LV test bench are also provided to validate the proper operation of the new concept. [ABSTRACT FROM AUTHOR]