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In the semiconductor industry, the testing section has always played an important role. The testing section often requires engineers to judge the defect, which wastes a lot of time and cost. The accurate classification can provide useful information for engineers through neural networks. In this paper, we present a method for wafer map data augmentation and defect classification. Data augmentation is based on CNN encoder-decoder and the classification is based on depthwise separable convolutions. There are two datasets used, one is open dataset WM-811K and the other is built with a Taiwan company. We train two models with mobilenetV1 and V2 for the different datasets. The light-weight deep convolution can reduce model parameters and calculations, which is very efficient for the testing house with large production volumes. On two different data sets, our proposed method can reduce the number of parameters by 30% and 95%, and reduce the amount of calculation by 75% and 25%, respectively. The test accuracy of the first dataset is 93.95%. The second dataset test accuracy is 87.04%. After the data augmentation, accuracy is increased to 97.01% and 95.09%, respectively. [ABSTRACT FROM AUTHOR]

In the semiconductor manufacturing industry the development of single index assessing the equipment health condition is urgent, and thus the dashboard can be used for monitoring thousands of equipment. This paper proposes a novel equipment health index (EHI) framework and a Hotelling T-squared index (HTI) to monitor equipment and support preventive maintenance in real time in the semiconductor manufacturing industry. The EHI framework consists of data preprocessing, statistical process control, analytic hierarchy process, and a comprehensive single index representing the health condition of equipment. It considers different types of the univariate control charts for each status variable identification (SVID), and aggregates the scores corresponding to the control charts throughout the hierarchical structure. The HTI considers the correlation among the selected SVIDs and builds a multivariate index by using Hotelling T-squared statistic. An empirical study of Taiwan’s leading semiconductor assembly manufacturer finds that both the EHI and the HTI supported monitoring thousands of pieces of equipment in real time. In practice, firms can rapidly troubleshoot the root causes of failures by the decomposition of EHI. [ABSTRACT FROM AUTHOR]

Virtual Metrology (VM) is a method to conjecture manufacturing quality of a process tool based on data sensed from the process tool and without physical metrology operations. VM has now been designated by the International SEMATECH Manufacturing Initiative and International Technology Roadmap for Semiconductors as one of the focus areas for the next-generation factory realization roadmap of the semiconductor industry. This paper defines the VM automation levels, proposes the concept of automatic virtual metrology (AVM), and develops an AVM system for automatic and fab-wide VM deployment. The example of automatic VM model refreshing for chemical vapor deposition (CVD) tools is also illustrated in this paper. The AVM system has been successfully deployed in a fifth-generation thin-film-transistor-liquid-crystal-display (TFT-LCD) factory in Chi Mei Optoelectronics (CMO), Taiwan. [ABSTRACT FROM PUBLISHER]

The increasingly important role that technologies play in today's business success is well known. To ensure proper selection and development of the key technologies, a deliberate technology plan is needed. In this paper, a strategic technology planning framework is proposed. A hierarchical decision model and its sensitivity analysis are presented as two major steps of the framework to provide effective technology assessment and to generate technology scenarios. The hierarchical model links an organization's competitive goals and strategies in evaluating the technology alternatives' overall contributions to business success; the sensitivity analysis helps to forecast and implement possible future changes in the economic environment, industry policies, and organization strategies. With the proposed framework, organizations can start to implement their technology plans synoptically and follow up with incremental adaptations as necessary. A case study on Taiwan's semiconductor foundry industry is presented to demonstrate the model in detail. [ABSTRACT FROM AUTHOR]

A novel physical structure, buried solder bumps, is introduced that solves the compliance problems that exist in scaling present area array technologies to ever-higher densities. In this technique, buried bumps provide dc connections between integrated circuits and substrates and ac coupled interconnections provide paths for ac signals across the same interface. This approach requires co-design of packaging and circuits and meets the growing demands for both interconnect density and bandwidth. AC coupled interconnection arrays can be built with pitches for ac signals below 100 micrometer and dab rates of 6 Gb/s per I/O. This paper presents the physical and circuit aspects of this work as well as measured results from capacitively-coupled circuits fabricated in Taiwan semiconductor manufacturing Company (TSMC) 0.35-μm technology. Simulated results from capacitively-coupled circuits in TSMC 0.18 μm are also presented. [ABSTRACT FROM AUTHOR]