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This paper presents a novel seven-level inverter topology for medium-voltage high-power applications. It consists of eight active switches and two inner flying capacitor (FC) units forming a similar structure as in a conventional active neutral-point-clamped (ANPC) inverter. This unique arrangement reduces the number of active and passive components. A simple modulation technique reduces cost and complexity in the control system design without compromising reactive power capability. In addition, compared to major conventional seven-level inverter topologies, such as the neutral point clamped, FC, cascaded H-bridge, and ANPC topologies, the new topology reduces the dc-link voltage requirement by 50%. This recued dc-link voltage makes the new topology appealing for various industrial applications. Experimental results from a 2.2-kVA prototype are presented to support the theoretical analysis presented in this paper. The prototype demonstrates a conversion efficiency of around 97.2% ± 1% for a wide load range. [ABSTRACT FROM AUTHOR]

This paper presents a neutral-point deviation and ripple compensating control method applied to a three-level neutral-point-clamped (NPC) converter. The neutral-point deviation and its harmonic components are analyzed with a focus on the average current flowing through the neutral-point of the dc link. This paper also proposes a control scheme compensating for the neutral-point deviation and dominant harmonic components under generalized unbalanced grid operating conditions. The positive and negative sequence components of the switching functions and ac input currents are employed to accurately explain the behavior of three-level NPC converter. Simulation and experimental results are presented to verify the validity of the proposed method. [ABSTRACT FROM AUTHOR]

A trinary multilevel converter uses a few heterogeneous H-bridge submodules (SMs) to synthesize an output voltage with multiple levels. Two major limitations of this converter are that it needs multiple dc sources and it cannot operate under pulsewidth modulation (PWM). This paper addresses these limitations by adding a low-voltage H-bridge SM to this converter and proposing a new switching algorithm. The resulting PWM-based asymmetric cascaded H-bridge converter uses only one dc source and synthesizes a high-quality output voltage. This improved converter can be a potential choice for real and reactive power support in power system applications. This paper also proposes methods for stability analysis and design of this converter. Experimental case studies evaluate the performance of the proposed converter for both standalone and grid-connected modes of operation. [ABSTRACT FROM AUTHOR]

In this paper, a novel space-vector pulsewidth modulation technique for a five-level active neutral-point clamped (5L-ANPC) inverter is proposed to eliminate the common-mode voltage (CMV). For the 5L-ANPC inverter, which produces a good output voltage performance and lowdv/dt, the total 125 voltage vectors can be generated, among which the proposed scheme employs only 19 voltage vectors producing a zero CMV. Due to the limitation of voltage vectors selected, the dc-link capacitor voltages of the 5L-ANPC inverter cannot be balanced by themselves. Therefore, the capacitor voltages of the inverter should be controlled by choosing the redundant switching states appropriately. The validity of the proposed modulation scheme has been verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

High step-down voltage conversion is necessary to bridge the voltage gap between main power converters and low-voltage auxiliary electronics in power conversion systems. Switched capacitor converters (SCCs) are an attractive candidate as a high step-down converter, but their poor voltage regulation capability may limit their applications. Pulsewidth modulation (PWM) SCCs with adjustable high step-down voltage conversion are proposed in this paper. The proposed PWM SCCs can be derived from traditional SCCs by replacing an energy transfer capacitor with a switched-capacitor-inductor (SCL) cell that comprises inductors, capacitors, and diodes to realize PWM-controllable voltage conversion. The voltage step-down ratio of the proposed PWM SCCs is not only PWM controllable but also adjustable with structures of SCCs and SCL cells. Two representative PWM SCCs were taken as examples to perform the operational analysis. The prototypes of both representative PWM SCCs were built and tested to demonstrate the proposed concept. [ABSTRACT FROM AUTHOR]

This paper investigates an ac–dc–ac multilevel power converter. The studied configuration is composed of two single-phase ac–dc–ac three-leg modules and series-connected H-bridges in the shared part of system. Because the proposed converter has shared legs between the input and output, it is employed in applications with same input and output frequency. Uninterrupted power supply and unified power quality conditioner are application examples for this converter. Such multilevel topology has lower dc-link voltage rating, which, consequently, presents low switch blocking voltages when compared to conventional topologies. System model, a space-vector pulsewidth modulation (PWM) strategy to symmetrical and asymmetrical dc-link voltages, and an overall control strategy to adjust the system variables are presented. A power flux analysis shows the operation zone in which the individual dc-link voltage balancing is possible. PWM and control strategies are developed to reduce the semiconductor total losses, harmonic distortion, and switching stress. Two ac–dc–ac multilevel conventional structures are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper presents the active capacitor voltage-balancing (ACVB) methods based on the dynamic model for a five-level nested neutral-point piloted (NNPP) converter using hybrid carrier modulation. The traditional hybrid carrier modulation provides natural voltage balancing of floating capacitors and dc-link capacitors. First, the natural voltage-balancing ability under steady-state and ideal conditions is theoretically proved. However, there are accumulated errors and deviations of capacitor voltages in practical applications, especially under dynamic conditions. In order to address the accumulated errors and deviations of capacitor voltages, the dynamic models of floating-capacitor voltages and neutral-point voltage are established. Moreover, the ACVB method based on the dynamic model of the neutral-point voltage is proposed by injecting the zero-sequence voltage. And the ACVB method based on the dynamic model of floating-capacitor voltages is proposed by introducing the adjustment variables. The proposed ACVB methods have the advantages of simple formula, definite physical meaning, and high accuracy. Furthermore, the output voltage quality and current quality are evaluated in term of total harmonic distortion and the effect of model parameter mismatch on the proposed ACVB methods is presented. Finally, the comparative simulation and experimental results verify the correctness of the proposed ACVB methods based on the dynamic model under different conditions. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid pulse width modulation-based discontinuous modulation (D-HPWM) strategy with dc-link voltage balancing for a three-level neutral-point-clamped (NPC) traction inverter drive. The results are then compared with continuous-hybrid-PWM (C-HPWM) to check the performance improvement. The HPWM strategy uses both the advantages of carrier- and space-vector-based PWM strategies. The duty cycles are generated using the carrier-based strategy to reduce the computational time and complexity of the system and redundant vector states are used to keep the two dc-link capacitor voltages balanced. As discontinuous PWM (DPWM) reduces the switching losses considerably compared to the continuous PWM, the DPWM strategy is developed in this paper for the HPWM-based strategy. Detailed comparison studies are then carried out in MATLAB/Simulink and PLECS to show the conduction and switching loss distribution with change in modulation index for different power switches. A 54.0-kW surface permanent magnet synchronous machine (PMSM) is used for this simulation studies. Moreover, the total inverter loss and losses in each insulated gate bipolar transistor (IGBT) are also compared. Detailed experimental performance analysis is also carried out with a scaled down prototype of a 6.0-kW surface PMSM, NPC inverter, and real-time emulator DSpace, to show the capacitor voltage deviation with both control strategies. [ABSTRACT FROM PUBLISHER]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

The flying-capacitor modular multilevel converter (FC-MMC) overcomes the low/zero-speed operation issues of conventional MMC-based drive. The FC-MMC injects no common-mode voltage (CMV) to the drive system. However, the pulse width modulator (PWM) introduces switching ripples, which appear as CMV on motor stator windings. To completely get rid of the CMV, an elimination method based on a new modulation scheme is proposed in this paper. The modulation algorithm places the switching pulses end to end for upper and lower arms, respectively. The consistent switching positions between upper and lower arms lead to the complete CMV elimination for FC-MMC-based drive system in entire speed range. Although the proposed method slightly increases the switching frequency as compared to conventional phase-shifted PWM, it is still acceptable in medium-voltage applications. The validation of the proposal is proved by simulations and experiments. [ABSTRACT FROM PUBLISHER]

This paper extends the trans-Z-source concept to ac–ac power conversion and proposes a novel single-phase trans-Z-source ac–ac converter. The proposed converter retains the advantages of its existing Z-source/quasi-Z-source counterparts in which the output voltage can be boosted and in-phase with the input voltage or bucked/boosted and out-of-phase with the input voltage. Meanwhile, a coupled inductor is introduced into the proposed converter, and the turns ratio of the coupled inductor become another control variable beside the duty cycle to obtain extreme voltage gain. Importantly, the input voltage and output voltage share the same ground, and the input current could be continuous, which is a benefit for reducing input current harmonics. Most important of all, the safe-commutation strategy for the proposed converter is deep developed, and analytic expression between the switches state and loop circuit voltage/current condition is derived out. Hence, the current/voltage ripple can be avoided without a loss snubber circuit, which benefits a reduced cost and enhanced reliability. The performance analysis is discussed in consideration of parasitic resistance, and system parameter design is optimized based on theoretic calculation. A laboratory prototype is fabricated, and experiments are performed to verify the validation of the proposed converter. [ABSTRACT FROM PUBLISHER]

The noninverting buck–boost converter has attracted significant attention in the photovoltaic (PV) module integrated application, as it offers high efficiency while maintaining a low cost and a simple topology. When this converter is employed, special care must be taken at the transition between buck and boost operating modes, as a dead-zone in the voltage transfer function can cause abrupt perturbations in the controlled voltage, decreasing the regulation quality and ultimately lowering the power conversion efficiency. In this paper, a new dead-zone compensation technique is proposed with the scope of smoothing the transition between operating modes, eliminating the voltage ripple and improving the regulation performance, while maintaining high efficiency. The converter under analysis is studied together with its gate driving circuit, which is based on a bootstrap capacitor power supply for the high-side switches. The proposed dead-zone compensation technique is deduced by using the principle of maintaining the ideal voltage gain function across the converter operating range. The technique is analyzed, implemented and tested on a purposely built PV module integrated noninverting buck–boost converter. The experiments reveal a sensible improvement of the voltage regulation during mode transition, confirming the effectiveness of the proposed technique and its fitness for the PV application. [ABSTRACT FROM AUTHOR]

Five-level hybrid-clamped (5L-HC) converter is a newly proposed topology which is suitable for high-performance medium-voltage high-power conversions without switches directly connected in series. The critical issue of this converter is that two flying capacitor voltages of each phase and two neutral-point potentials of the dc-link need to be balanced. This paper presents a decoupled voltage balancing method for this 5L-HC converter based on modified phase-shifted pulse width modulation (PS-PWM) and optimal zero-sequence voltage injection. The voltages across the central dc-link capacitor and two flying capacitors are balanced first by adjusting the width of four PWM signals. Second, the relationship between the neutral-point currents and the output phase voltage is studied and the upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection. Both steady-state and dynamic-state simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

Presently, the neutral-point potential offset is an inherent problem for three-level converters on three-phase four-wire active power filters. The conventional three-dimensional space vector pulse width modulation (3-D-SVPWM) strategy is adopted as a normal solution to the problem, but the selection of space vector sectors for four-wire converter is both abstract and complicated in practice. This paper proposes a new PWM strategy accordingly to simplify the selection process and the calculation of duration. Compared to the conventional 3D-SVPWM, the proposed method locates the sector of optimal vector directly with the polarity of three-phase reference voltage. Then, by applying voltage–second balance rule, it can perform a fast calculation of the duration and generate PWM signals to control the switching devices’ on/off. As an approach to correct the imbalance dc-link capacitor voltage, this strategy reconstructs the switching sequence. A portion of state O duration is disassembled into states P and N to suppress the neutral-point potential offset. The proposed strategy is validated with a range of experiments. The results indicate that this simplified PWM strategy can effectively reduce the computational burden, and also the dc-link capacitor voltage is well controlled. [ABSTRACT FROM PUBLISHER]

Dynamic voltage restorer (DVR) technology has become a mature power quality product. In high-power applications, DVR using a multilevel converter is commonly used. However, DVR using a multilevel direct pulse width modulation (PWM) ac–ac converter has not been well studied. This paper presents a new DVR topology using a cascaded multilevel direct PWM ac–ac converter. In the proposed scheme, the unit cell of the multilevel converter consists of a single-phase PWM ac-ac converter using switching cell structure with coupled inductors. Therefore, the multilevel converter can be short- and open-circuited without damaging the switching devices. Neither lossy RC snubber nor a dedicated soft commutation strategy is required in the proposed DVR. This improves the reliability of the DVR system. The output voltage levels of the multilevel converter increase with the number of cascaded unit cells, and a high ac output voltage is obtained by using low-voltage-rating switching devices. Furthermore, a phase-shifted PWM technique is applied to significantly reduce the size of the output filter inductor. A 1-kW prototype of single-phase DVR is developed, and its performance is experimentally verified. Finally, the simulation results are shown for a three-phase DVR system. [ABSTRACT FROM AUTHOR]

In signal injection sensorless drives, the injection voltage cannot be reduced under a certain value. The lower limit of the injection voltage is mainly enforced by the inverter nonlinearity that causes distortion of the injection voltage and degradation of the position estimation performance. After analyzing the inverter nonlinearity during the voltage injection, it is revealed that parasitic capacitances of insulated-gate bipolar transistors have positive effects on inverter output linearity and sensorless control. Based on this analysis, this paper proposes a method to reduce the injection voltage by connecting additional capacitors to the output terminals of the inverter. Simulation and experimental results are provided to verify the effectiveness of the proposed idea. In the experiments, using the capacitor-integrated inverter, it is shown that the injection voltage can be reduced by more than half without degrading the position estimation performance. [ABSTRACT FROM AUTHOR]

The five-level active neutral-point-clamped (5L-ANPC) converter has been widely studied for its excellent performance in high-power medium-voltage applications. This paper analyzes the space vector pulse width modulation (SVPWM) strategy of the 5L-ANPC converter in the virtual coordinate, and presents an optimized control strategy which can balance the neutral point (NP) voltage and avoid the dead-time effects for the first time. In this strategy, on one hand, the 125 space vectors are combined by 96 triangles in the seven-segment vector synthesis method, then the triangles are divided into seven categories which have different characteristics of balancing the NP voltage, and every category has its own principles to choose the vector sequence and compute the vector durations. On the other hand, the dead-time effects of the 5L-ANPC converter are studied in detail and the transitions between different switching states are constrained in the optimized control strategy to avoid the dead-time effects that cannot be compensated by traditional pulse-based dead-time compensation methods. Finally, the optimized SVPWM strategy is experimentally verified in this paper. [ABSTRACT FROM AUTHOR]

In this paper, an immune algorithm (IA) is developed for optimization of the harmonic performance of a three-phase inverter under the space-vector pulsewidth-modulation (SVPWM) control strategy. The presented algorithm employs the immune approach as the search method for finding the best optimal control vectors and action time of the three-phase inverter. As a result, the optimal control vectors and action time are calculated to minimize the objective function of the weighted total harmonic distortion of the output voltage waveforms. In addition, an experimental platform based on DSP and field-programmable gate array is built. This paper provides a detailed performance analysis of the method with comparison to the conventional SVPWM. The simulation and experimental results verify the superiority of the best control sequences generated by IA compared with the existing conventional control strategies. [ABSTRACT FROM PUBLISHER]

A new pulse width modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is developed and presented in this paper. The proposed PWM scheme not only takes advantage of the special properties available in NPC inverters, but also reduces the switching loss of the inverter along with an inherent neutral point (NP) voltage control. Based on a circuit-level decoupling concept, the NPC inverter can be decoupled into two three-level Buck converters in every defined operating section, and thereby the controller design can be simplified. The salient features of the proposed scheme, as compared with the existing carrier-based DPWM strategies, are: 1) its reduced computational processing time, 2) its capability to balance the dc-link voltage without any additional control, and 3) its reduced complexity, e.g., only one carrier wave needed for pulse width modulating. Same as a space-vector modulation, the maximum modulation index, 1.1547, can be attainable by the proposed scheme. Moreover, compared to conventional continuous sinusoidal PWM, using this technique proposed here, the switching losses of the devices can be reduced by one third. In order to explain the operation of this topology properly, the decoupling principle including the driving signal synthesis and the NP potential variation are analyzed in detail in this paper. Finally, the viability and performance of the proposed modulation scheme are shown through simulation and experimental results in a laboratory prototype. [ABSTRACT FROM PUBLISHER]

This paper proposes a unique carrier-based pulse width modulation strategy for a three-level neutral-point-clamped inverter that works satisfactorily and with uniform convergence time over the full power factor (PF) range of the load variation. It has excellent control over capacitor voltages and mitigates low-frequency oscillations in the neutral point for the full PF range. First, an investigation is made to see how the load currents get modulated to generate compensating neutral current causing charging and discharging of dc-link capacitors. It is observed that when an additional modulating voltage signal that is in phase with the corresponding phase current is added in each phase, a neutral current is produced in the right direction which can be used to compensate for any prior unbalance in capacitor voltages. It is demonstrated that the performance of this scheme is insensitive to the load PF variation (full range from zero to unity). It performs satisfactorily throughout the entire linear modulation range and eliminates any undesirable low-frequency harmonic component in the compensating neutral current. The effectiveness of the proposed scheme is verified through simulation and experimental results by varying load PF as well as modulation index with both passive and motor loads. [ABSTRACT FROM PUBLISHER]

Diode-assisted buck–boost voltage-source inverter achieves high voltage gain by introducing a switch-capacitor based high step-up dc–dc circuit between the dc source and inverter bridge. As for the unique structure, various pulse width modulation (PWM) strategies are developed with regard to the chopped intermediate dc-link voltage. In order to maximize voltage gain and increase efficiency, this paper proposes a novel PWM strategy. It regulates the average value of intermediate dc-link voltage in one switching time period ( Ts) the same as the instantaneous maximum value of three-phase line voltage by controlling the front boost circuit. Then, the equivalent switching frequency of power devices in the inverter bridge can be reduced to 1/3fs (fs = 1/Ts). The operating principle and closed-loop controller design are analyzed and verified by simulations and experiments. Compared with existing PWM strategies, the new control strategy demonstrates less power device requirement and higher efficiency in high voltage gain applications. It is a more competitive topology for wide range dc/ac voltage regulation in renewable energy applications. Furthermore, with new control strategy, the dc-side inductor current and capacitor voltage contains six-time line-frequency ripples. To overcome the undesired influence of low frequency ripples, it is also suitable for 400–800 Hz medium frequency aircraft and vessel power supply system. [ABSTRACT FROM PUBLISHER]

The flying-capacitor-based multilevel converter is one of the well-known breeds of the multilevel power converters. This paper proposes a new flying-capacitor-based multilevel converter to minimize the number of flying capacitors (FCs) and power switches. The advantage of the proposed FC-based multilevel converter in comparison with the conventional flying-capacitor multicell converter is that it needs fewer FCs. Also, in comparison with the stacked multicell converter, the proposed multilevel converter requires fewer semiconductor switches. In order to balance the voltage of the FCs in proposed multilevel converter, a new active voltage balancing method which is fully implemented using logic-form equations is presented. The proposed voltage balancing method measures output current and FC voltages to generate switching states to produce the required output voltage level, as well as balance the FCs voltages at their reference values. The output voltage of the proposed multilevel converter controlled with suggested active voltage balancing method can be modulated with any pulse-width-modulation (PWM) method, such as phase-shifted-carrier PWM or level-shifted-carrier PWM. Simulation results and experimental measurements of proposed FC-based multilevel converter are presented to verify the performance of the proposed converter, and its novel switching and modulation strategy, which is based on the active voltage balancing method. [ABSTRACT FROM PUBLISHER]

This paper proposes a new space-vector pulsewidth modulation (SV-PWM) strategy for a three-level neutral point clamped inverter. The presented SV-PWM strategy makes it possible to control the neutral point voltage by optimum choice of switch sequence for any position and length of output voltage vector. The proposed solution takes into consideration the unbalance of the dc-link voltages. It also analyzes the influence of vector sequences on the predicted unbalance of the dc-link voltage. The solution allows selecting optimum vectors and their on-time durations in order to reduce quickly the dc-link voltage unbalance. The calculation of the space vector area proposed in this paper takes into consideration voltage unbalance and its influence on the length and position of vectors. The proposed approach assures properly generating the voltage output vectors, even in the case of the existing large voltage unbalance in the dc-link. The results of the experimental investigation of the proposed modulation strategy are presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper proposes a new circuit topology for a multilevel pulse width modulation (PWM) rectifier. The proposed method forms a new circuit by combining a diode clamp-type topology with a flying capacitor-type topology. The proposed circuit uses only 12 switches, despite the use of a five-level three-phase PWM rectifier. Further, the proposed circuit can obtain good performance, same as a conventional multilevel circuit. This paper describes about the features of the proposed topology; the control strategy and the loss analysis that is estimated by a circuit simulator. In addition, the basic operation of the proposed method is confirmed by simulation and experimental results. The proposed converter achieved total harmonic distortion of 3.4% for the input current and efficiency of 97.4% for a 1 kW class experimental setup. [ABSTRACT FROM AUTHOR]

This paper describes a modified phase-shifted carrier-based pulsewidth-modulation (PSC-PWM) scheme for modular multilevel converters (MMC). In order to reduce the average device switching frequency, a reduced switching-frequency (RSF) voltage balancing algorithm is developed. This paper also proposes a circulating current suppressing controller (CCSC) to minimize the inner circulating current in an MMC. Based on the double line-frequency, negative-sequence rotational frame, the three-phase alternative circulating currents are decomposed into two dc components and are minimized by a pair of proportional integral controllers. Simulation results based on a detailed PSCAD/EMTDC model prove the effectiveness of the modified PSC-PWM method and the RSF voltage-balancing algorithm. The proposed CCSC not only eliminates the inner circulating current but also improves the quality of the converter ac output voltage. A simple loss evaluation demonstrates that the RSF voltage-balancing algorithm and the CCSC reduce the converter power losses. [ABSTRACT FROM AUTHOR]

This paper proposes and evaluates an active voltage-balancing method for stacked multicell converters (SMCs) using phase-shifted pulse width modulation. The method is easy to implement and can be applied to SMCs with any number of levels. The proposed method balances the voltages of the capacitors by modifying the duty cycle of each switch of the SMC using a proportional controller. The direction of the output current and the crossed effect among the duty cycles of the switches is considered and used to improve capacitor voltage balance. The performance of the proposed voltage-balancing method is verified experimentally for different loads, such as linear and nonlinear loads, and under transient conditions. [ABSTRACT FROM PUBLISHER]

A capacitor voltage-balancing method for a nested neutral point clamped (NNPC) inverter is proposed in this paper. The NNPC inverter is a newly developed four-level voltage-source inverter for medium-voltage applications with properties such as operating over a wide range of voltages (2.4–7.2 kV) without the need for connecting power semiconductor in series and high-quality output voltage. The NNPC topology has two flying capacitors in each leg. In order to ensure that the inverter can operate normally and all switching devices share identical voltage stress, the voltage across each capacitor should be controlled and maintained at one-third of dc bus voltage. The proposed capacitor voltage-balancing method takes advantage of redundancy in phase switching states to control and balance flying capacitor voltages. Simple and effective logic tables are developed for the balancing control. The proposed method is easy to implement and needs very few computations. Moreover, the method is suitable for and easy to integrate with different pulse width modulation schemes. The effectiveness and feasibility of the proposed method is verified by simulation and experiment. [ABSTRACT FROM PUBLISHER]

A novel complementary phase disposition pulsewidth modulation method for the modular multilevel converter (MMC) with a limited number of submodules is proposed in this paper. Compared with the previous works, more practical issues have been considered, and the corresponding solutions have been provided. First, a new preset PWM signal mapping sequence and an improved virtual loop mapping (VLM) are used in the modulation. This method not only achieves a favorable capacitor voltage balance in the symmetry system but lowers the switching frequency of MMC's devices. Second, to further reduce the switching frequency, the unbalance margin of capacitor voltages is adopted to achieve the switching between the VLM and the selective VLM (SVLM). Moreover, the system robustness has been improved by considering the situation of symmetry losing, like cell fails; in these cases, the capacitor voltages of the upper and lower arms are balanced through the collaboration of the SVLM and the reconfigurable VLM. Finally, the effectiveness of the proposed method has been verified with simulation and experimental studies. [ABSTRACT FROM AUTHOR]

This paper presents a capacitor voltage balancing control applicable to any multilevel dc–ac converter formed by a single set of series-connected capacitors implementing the dc link and semiconductor devices, such as the diode-clamped topology. The control is defined for any number of dc-link voltage levels and converter legs (for single-phase and multiphase systems), guaranteeing the capacitor voltage control for any modulation index value and load (from idle mode to full power). The associated control loop small-signal transfer function is presented, from which optimum compensator design guidelines are derived. The improvement in control performance is verified through simulation and experiments comparing with a previous balancing control strategy in a four-level three-phase dc–ac conversion system. The satisfactory control performance is also verified through simulation in a four-level five-phase dc–ac conversion system. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel modulation technique and a new balancing control strategy for a single-phase five-level flying-capacitor (FC)-based active-neutral-point-clamped (ANPC) converter. The proposed modulator can control the FC voltage to follow the requested reference value and simultaneously generate the required ac output voltage regardless of the values of the dc capacitor voltages of the converter. By implementing this method, smaller values of the dc-link capacitor and FC can be used even in applications that could experience ripple or transient in the capacitor voltage. In a single-phase five-level ANPC converter applications, where the capacitors can experience pulsation power and dc-link balancing issues, such as grid-connected photovoltaic system, the selection of the reference voltage value for the FC can play an important role to balance the average values of the dc-link capacitor voltage. The proposed new control strategy uses a new reference voltage for the FC to be applied by the new modulator to have an average balanced dc-link voltages as well as an ac output voltage with good power quality. Simulation studies and experimental results demonstrate the effectiveness of the proposed modulation technique and control strategy even with relatively small dc capacitors to produce high-quality output voltage and current waveforms while maintaining an average balanced dc-link voltages. [ABSTRACT FROM PUBLISHER]

Five-level active neutral-point clamped (5L-ANPC) converter is an attractive topology for high-power medium-voltage motor drives. This paper presents a capacitor voltage-balancing method for the 5L-ANPC converter, including the voltage balancing of dc-link capacitors and flying capacitors. In order to ensure that the series-connected or high-voltage switches of the 5L-ANPC converter are operated at fundamental frequency and the other switches are operated at a constant switching frequency, phase-shifted pulse width modulation is used to control this converter. The relationship between the average neutral-point current and zero-sequence voltage is investigated, and an optimum zero-sequence voltage is calculated to regulate the neutral-point potential. The voltage across the flying capacitor is also regulated by adjusting the switching duty cycles of two PWM signals, which varies the operation time of redundant switching states in each switching period. Simulation and experimental results are presented to verify the validity of this method. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) is attractive for medium- and high-power applications because of its high modularity, availability, and power quality. In this paper, the current ripple on the dc link of the three-phase MMC derived from the phase-shifted carrier-based pulse-width modulation scheme is analyzed. A control strategy is proposed for the current ripple elimination. Through the regulation of the phase-shifted angles of the carrier waves in the three phases of the MMC, the current ripple on the dc link of the three-phase MMC can be effectively eliminated. Simulations and experimental studies of the MMC were conducted, and the results confirm the effectiveness of the proposed current ripple elimination control. [ABSTRACT FROM AUTHOR]

This paper proposes a voltage balancing method for a flying capacitor multilevel converter based on the phase-disposition sinusoidal pulsewidth modulation (PD-SPWM). This voltage balancing method uses redundant switching states, which are determined by the minimization of a cost function. The implementation of the PD-SPWM using standard triangular carriers leads to additional switching events that are due to the transitions within the same voltage level, thus increasing the switching frequency of the power devices. Such drawback can be avoided by using sawtooth carrier waveforms. Another characteristic of the proposed voltage balancing method is that it does not require the tuning of parameters to achieve optimal performance. Simulation and experimental results confirm the robustness of the proposed method operating with different loads and transient conditions. [ABSTRACT FROM PUBLISHER]

In this paper, a generalized switching technique for cascaded H -bridge (CHB) converters is proposed. To take advantage of both low- and high-frequency modulation techniques, a hybrid modulation method is utilized. The proposed technique employs the low-frequency switching for voltage balancing of the dc-link capacitors, and the high-frequency sinusoidal pulse-width modulation switching for shaping the input ac current. Using the proposed technique, the stable operating region of CHB converters is extended. The proposed technique is capable of maintaining the dc voltages balanced even under critical operating conditions in which the load of one H-bridge cell is removed. The validity and effectiveness of the proposed method is confirmed by several simulation and experimental tests on a seven-level CHB rectifier. [ABSTRACT FROM AUTHOR]

Multilevel flying capacitor (FC) converters provide natural capacitor voltage balance under phase-shifted pulse width modulation (PS-PWM). However, natural balancing may not be robust enough to maintain the voltages at the reference values, especially under certain transient conditions. Furthermore, natural balancing dynamics depend on the load and it may be very slow in some practical applications. Therefore, a more robust balancing mechanism of maintaining the FC voltages at the desired values is required. This paper proposes a new closed-loop voltage-balancing method for the multilevel FC converters using PS-PWM. The proposed method balances the voltages of the FCs by modifying the duty cycle of each switch of the FC converter using a proportional controller. The crossed effect between FC currents and duty cycles is considered and is used for optimal FC voltage balancing. Simulation and experimental results verify that the proposed voltage-balancing method is very robust to different operating conditions, such as load transients, linear/nonlinear and unbalanced loads. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) is attractive for medium- or high-power applications because of the advantages of its high modularity, availability, and high power quality. The voltage balancing of the floating capacitors in the cascaded submodules of the MMC is a key issue. In this paper, a voltage-balancing control method is proposed. This method uses the phase-shifted carrier-based pulsewidth modulation scheme to control high-frequency current components for capacitor voltage balancing in the MMC without measuring the arm currents. Simulations and experimental studies of the MMC were conducted, and the results confirm the effectiveness of the proposed capacitor voltage-balancing control method. [ABSTRACT FROM AUTHOR]

It is important to improve the overall efficiency of a photovoltaic (PV) inverter when it is connected to the grid. Fundamentally, the conversion efficiency from dc to ac power of an inverter is important. However, in the presence of partial shading, maximum power point tracking (MPPT) on PV modules is more important than the conversion efficiency. In this paper, a new control method for a three-level inverter is proposed. With the proposed method, each dc-link voltage of the three-level inverter can be asymmetrically regulated. When PV modules are split into two and each split module is connected to the respective dc-link capacitors of the inverter, the asymmetric control can be helpful because separate MPPTs are possible. The effectiveness of the proposed method was examined through experiments with a T-type three-level inverter, where each dc-link capacitor was supplied by a PV simulator emulating two separate PV modules under different shading conditions. [ABSTRACT FROM AUTHOR]

The five-level active neutral-point (NP)-clamped (ANPC) converter is a newly emerging topology which can overcome the drawbacks of traditional NP-clamped and flying-capacitor multilevel converters. This paper presents a comprehensive theoretical analysis of the NP potential balancing issue and demonstrates that the NP potential can be naturally balanced under ideal and steady conditions. An NP potential balancing method based on zero-sequence voltage injection is presented. By calculating the average NP currents of all key zero-sequence voltages, the most appropriate zero-sequence voltage is selected to generate the demanded NP current, which can also limit the switching frequency of the series-connected insulated-gate bipolar transistors to the fundamental frequency. A three-phase five-level ANPC inverter prototype is built up, and both steady and dynamic experimental results are presented to verify the validity of this method. [ABSTRACT FROM PUBLISHER]

An auxiliary capacitor-based balancing approach is adopted in this paper to equalize the dc-link capacitor voltages of a diode-clamped multilevel converter (DCMC). Four balancing circuits, including the generalized, one-level-capacitor, one-capacitor, and simplified one-capacitor-based configurations are discussed for a five-level DCMC system. These configurations are different in connection of the auxiliary circuits and numbers of the capacitors and switches, but they work on the same principle called ping-pong operation by utilizing the auxiliary capacitor as an equalizer between the capacitors of different voltages. The unbalance phenomenon, ping-pong principle, circuit configurations, and their switching schemes are analyzed, respectively. The superiorities of the proposed approach include balancing operation regardless of load power factor and modulation index, control simplicity, and independence from main circuits when compared to the traditional approaches. Simulations and experimental results verified the performances using the proposed balancing circuits and control strategies. [ABSTRACT FROM AUTHOR]

Single-phase three-level neutral point clamped (NPC) converters are widely applied in high-speed railway electrical traction drive systems. A significant problem related to the single-phase three-level NPC converters is the fluctuation of the neutral-point voltage. In this paper, a capacitor voltage balancing technique is proposed that injects an offset voltage into the sinusoidal modulating signals of the conventional carrier-based pulsewidth modulation (CBPWM) method. Furthermore, when the injected offset voltage is maximized, it cannot only balance the dc-link capacitors voltages, but also reduce switching losses. Theoretical analysis has shown that both methods can control the neutral point voltage effectively, but the neutral point voltage controller in the CBPWM with maximum offset voltage injection (CBPWM-MOVI) has a faster dynamic response. It was observed that the high-order harmonics frequencies of the line current are centered around the twice switching frequency in the CBPWM with the offset voltage injection (CBPWM-OVI) but are centered around the switching frequency in the CBPWM-MOVI. And also, the CBPWM-MOVI has switching commutations number at least 25% below that of the CBPWM-OVI in one modulating signal period. The performances of the two strategies were verified by simulation and experimental tests. [ABSTRACT FROM AUTHOR]

This paper presents an improved full-bridge three-level (IFBTL) dc/dc converter for a wind turbine in a dc grid by inserting a passive filter into the dc/dc converter to improve the performance of the converter. The passive filter can effectively reduce the voltage stress of the medium frequency transformer in the IFBTL dc/dc converter. A modulation strategy, including two operation modes, is proposed for the IFBTL dc/dc converter. Then, a voltage balancing control strategy is proposed for the IFBTL dc/dc converter. Furthermore, the control of the wind turbine based on the IFBTL dc/dc converter in a dc-grid system is presented. Finally, a small-scale IFBTL dc/dc converter prototype was built and tested in the laboratory, and the results verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

A multilevel H-bridge StatCom inherently contains redundancy in the available switching states. This paper develops a variation on the typical model predictive control scheme which is able to exploit this redundancy to simultaneously balance the H-bridge capacitor voltages, provide excellent current reference tracking, and minimize converter switching losses. The scheme consists of a dead-beat current controller that has been integrated with heuristic models of the voltage balancing and switching loss characteristics. The integration of a pulsewidth modulation scheme is also described. Simulation and experimental results are presented that confirm the correct operation of the control and modulation strategies. Comparison with traditional control and modulation schemes is provided in terms of the key performance indicators associated with multilevel H-bridge StatComs. [ABSTRACT FROM AUTHOR]

A five-level flying-capacitor (FC)-based active-neutral-point-clamped (ANPC) converter is an arrangement of a three-level ANPC converter and a two-level cell. In this paper, a control strategy is proposed to regulate the voltage across the FCs at their respective reference voltage levels by swapping the switching patterns of the switches based on the polarity of the output current, the polarity of the FC voltage, and the polarity of the fundamental line-to-neutral voltage under selective harmonic elimination pulsewidth modulation. The voltage across the FCs and the dc-link capacitors are simultaneously controlled at their reference voltage levels. The proposed control strategy is applied using power system computer aided design/electromagnetic transients including dc on a static synchronous compensator operating under a power-factor-correction mode to verify its performance. Experimental results are also presented for low and high number of angles per quarter period using a low-power laboratory prototype. [ABSTRACT FROM AUTHOR]

With regard to a five-level inverter comprising flying-capacitor asymmetric H-bridge, the impact on the capacitor voltage under conventional modulation approach is analyzed. Since it is sensitive to the fundamental period and the load current, it may introduce undesired low-order harmonics into the output voltage and may even break down the power switches due to the considerable fluctuation of the flying-capacitor voltage. Thus, this paper proposes a novel pulsewidth-modulation scheme with the positive and negative cross carriers, which controls the flying-capacitor voltage by utilizing the redundant switching states of the output voltages. Three modes of precharging the flying capacitor without extra equipments are presented. Moreover, the capacitance of the flying capacitor and the switching frequency of the power switches can be chosen according to the allowable fluctuation of the flying-capacitor voltage and the load current. In order to remove the overlapping of the level layers, the optimization of the line-to-line voltage waveform is proposed to synthesize the reference vector with the “nearest three-vector” approach. The theory is supported by the experimental results from the prototype. [ABSTRACT FROM AUTHOR]

Controller design for six-switch pulse width-modulated (PWM) voltage source rectifiers (VSRs) is often accomplished in the rotating d-q frame coordinates in order to achieve a high-performance control. In contrast, the development of a d-q frame controller for a four-switch PWM VSR is rarely reported in the literature. In this regard, this paper introduces a control design approach in rotating d-q frame for the four-switch PWM VSRs. For this purpose, a mathematical model of the four-switch PWM VSR in rotating d-q frame is first derived. Its success is relied on performing a so-called “reduced Park Transformation” on switching functions. The derived model shares much structural property with that of a six-switch VSR. Then, two d-q frame current controller designs, input–output feedback linearization (IOFL) and linear proportional-plus-integral (LPI) control, are performed based on the derived model as application examples. Their effectiveness is verified via computer simulation and hardware experiment. Responses of an LPI a-b-c frame controller originated from the six-switch VSR are also documented for comparative study. Test results evidence the superiority of the d-q frame controllers. [ABSTRACT FROM AUTHOR]

This paper presents a neutral point voltage control strategy for the three-level active neutral point clamped (ANPC) converter using selective harmonic elimination pulsewidth modulation (SHE-PWM). The control strategy introduces a small change in the switching angles, which varies the duty cycle of the zero-level switching state, controls the neutral point current and, therefore, the neutral point voltage. The decision to vary a given switching angle takes into account the polarity of the output currents and the voltage across the lower dc-link capacitor. The effectiveness of the proposed strategy is verified through extensive simulation studies and experimentally validated using a low power laboratory prototype. [ABSTRACT FROM AUTHOR]