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It is important to improve the overall efficiency of a photovoltaic (PV) inverter when it is connected to the grid. Fundamentally, the conversion efficiency from dc to ac power of an inverter is important. However, in the presence of partial shading, maximum power point tracking (MPPT) on PV modules is more important than the conversion efficiency. In this paper, a new control method for a three-level inverter is proposed. With the proposed method, each dc-link voltage of the three-level inverter can be asymmetrically regulated. When PV modules are split into two and each split module is connected to the respective dc-link capacitors of the inverter, the asymmetric control can be helpful because separate MPPTs are possible. The effectiveness of the proposed method was examined through experiments with a T-type three-level inverter, where each dc-link capacitor was supplied by a PV simulator emulating two separate PV modules under different shading conditions. [ABSTRACT FROM AUTHOR]

In high current applications, paralleling three-phase voltage sourced inverters represents a modular solution for improving the system power conversion quality. Single-phase output reactors are often inserted between the output terminals of the two inverters that supply the same phase output. One function of these inductors is to limit circulating currents between the two inverters. These currents are produced by common-mode voltage differences between the three-phase output terminals of the two inverters. Since standard interleaved pulse width modulation (PWM) techniques naturally produce high-frequency common-mode voltage differences between parallel connected inverters, this paper describes a modified discontinuous PWM scheme that eliminates these voltage differences. As a result, a three-phase parallel inverter system can be operated using a single three-limb coupled inductor, significantly improving the system power conversion density as a result. An experimental 3 kW prototype system is used to compare the operation of the resultant inverter against one using separate single-phase coupled inductors. [ABSTRACT FROM PUBLISHER]

The five-level active neutral-point (NP)-clamped (ANPC) converter is a newly emerging topology which can overcome the drawbacks of traditional NP-clamped and flying-capacitor multilevel converters. This paper presents a comprehensive theoretical analysis of the NP potential balancing issue and demonstrates that the NP potential can be naturally balanced under ideal and steady conditions. An NP potential balancing method based on zero-sequence voltage injection is presented. By calculating the average NP currents of all key zero-sequence voltages, the most appropriate zero-sequence voltage is selected to generate the demanded NP current, which can also limit the switching frequency of the series-connected insulated-gate bipolar transistors to the fundamental frequency. A three-phase five-level ANPC inverter prototype is built up, and both steady and dynamic experimental results are presented to verify the validity of this method. [ABSTRACT FROM PUBLISHER]

The three-phase four-leg inverter is very suitable for the high-power uninterruptible power supply application, and the load neutral point voltage (LNPV) should meet the requirement. In this paper, two factors influencing the LNPV were revealed first, which are the switching states and the ratio of the neutral inductance to the phase inductance (k). Then, the 16 switching states can be classified into four groups, and the ones in the first and the second group come to the minimum amplitude of LNPV with a specific ratio k respectively. Third, three methods to mitigate the LNPV were proposed based on the analysis of LNPV. In the first method, switching states in the first group are just utilized, and the LNPV can be eliminated with the ratio k of unity. In the second method, the switching states in the fourth class are avoided, and the LNPV can be reduced. Common mode filter is used in the third method and the LNPV can be mitigated effectively with the ratio k of unity. Furthermore, the power losses in the first and the second method were estimated and were compared with the original situation. Finally, the proposed methods were verified by simulation and experimental results. [ABSTRACT FROM PUBLISHER]

A neutral-point-clamped three-level inverter with small dc-link capacitors is presented in this paper. The inverter requires zero average neutral-point current for stable neutral-point voltage. The small dc-link capacitors may not maintain capacitor voltage balance, even with zero neutral-point current. This may happen due to nonlinearities present in the circuit. This requires a fast control of the neutral-point voltage. A simple carrier-based modulation strategy which allows modeling of the neutral-point voltage dynamics as a continuous function of power drawn from the inverter is proposed. This continuous model shows that the neutral-point current is proportional to the power drawn from the inverter, and it enables the use of a well-established classical control theory for the neutral-point voltage controller design. A simple proportional integral controller is designed for the neutral-point voltage control on the basis of the continuous model. The design method for optimum performance is discussed. The implementation of the proposed modulation strategy and the controller is very simple. The controller is implemented in a 7.5-kW induction machine-based drive with only 14 \mu \F dc-link capacitors. Also, the experimental results show that fast and stable performance of the neutral-point voltage controller are achieved and thus verify the validity of the proposed control approach. [ABSTRACT FROM PUBLISHER]

This paper proposes a new modulation technique that can reduce the current distortion and extend the current reconstruction range for a three-phase inverter using only dc-link sensor. The proposed pulsewidth modulation (PWM) technique is a hybrid method which consists of space vector modulation method and the PWM method without using null switching states. The former provides low current distortion; however, it is with narrower current reconstruction range. In contrast, the latter extends the current reconstruction range at the cost of higher current distortion. For the proposed method, in the measurable region of space vector modulation method, space vector modulation is used to reduce the current distortion. Moreover, as the modulation range is out of the measurable region, the PWM method without using null switching states is applied to extend the current reconstruction range. Furthermore, the current reconstruction limitation using only dc-link sensor is analyzed. The analysis shows that the reduction of PWM switching frequency and acquisition time can extend the current reconstruction range. Comparison of experimental results derived from a field-programmable gate array-based controlled inverter is included. It will be demonstrated that using the proposed hybrid PWM technique, the three-phase current signals of the inverter can be reconstructed even under very low modulation index range while providing low current harmonic distortion of inverter output. [ABSTRACT FROM AUTHOR]

This paper presents a novel modulation strategy for a seven-phase three-level inverter, aimed at variable-speed drive applications. Developed space vector pulsewidth modulation (SVPWM) strategy is based on vector space decomposition (VSD) approach and an analysis of multidimensional space vector projections in mutually orthogonal planes. The algorithm represents an extension of a recently developed five-phase three-level SVPWM algorithm and is considerably more complex, due to the existence of three mutually orthogonal planes in a seven-phase system. The difficulties of generalization of space vector strategies, which stem from the nature of the multiphase systems, are highlighted. Increasing the number of phases from five to seven increases the number of switching states from 3 ^5 = 243 to 3^7 = 2187 and the number of orthogonal planes from two to three. This considerably affects the complexity of the offline calculations. However, the final implementation of the algorithm is simple. Developed SVPWM algorithm is compared to an equivalent carrier-based strategy and it is shown that they yield identical performance. The complexity of the algorithms for real-time implementation is compared. Simulation and experimental results, obtained using neutral-point clamped inverter, verify the theoretical developments. [ABSTRACT FROM AUTHOR]

This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n ± 1 (n = odd ) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation. [ABSTRACT FROM AUTHOR]

The advancement in power electronics has made the use of any number of phases in ac machines possible since with the inverter, any number of phase voltages can be realized as long as the corresponding inverter exists. To supply multiphase drives requires multiphase voltage source inverters (VSIs) whose output voltages depend very much on the methods of generating the pulses to turn on and turn off the inverter devices appropriately. This paper presents an analytical technique for the determination of the expressions for the modulation signals used in the carrier-based sinusoidal and generalized discontinuous pulse width modulation schemes for two-level, five-phase voltage source converters. These expressions can be used for both balanced and unbalanced phase voltages generated by any two-level multiphase inverter, in generating the required reference signals appropriately. An example of a five-phase VSI is presented to illustrate the strategy. Simulation and experimental results are presented in which a close examination shows that both results are similar for the balanced and unbalanced load voltage cases. [ABSTRACT FROM AUTHOR]

This paper proposes a smooth transition control strategy for voltage-source inverters between standalone (SA) and grid-connected (GC) modes of operation. In the GC mode, the amount of power exchanged with the utility grid is controlled by regulating the phase currents. In the SA mode, the load voltage is regulated by the inverter with its phase dictated by the inverter control. The transition between SA and GC operations that will ensure continuous power delivery to the load requires continuation in the phase of the system voltage. The proportional–integral, trapezoidal, sinusoidal, and staircase frequency variation techniques have been analyzed to find the best approach for minimizing the total harmonic distortion (THD). A smooth frequency variation technique has been developed, which provides lower THD on the voltage waveforms compared with the other techniques. The new algorithm has been implemented on a 5-kW single-phase utility interactive inverter having the SA operation capability. The simulation and experimental results show that the proposed technique provides seamless transition between the inverter modes of operation with minimal distortion at the inverter output voltage. [ABSTRACT FROM PUBLISHER]

Operating a dual three-level inverter system from a single dc link circuit is an economic solution for generating five-level output voltage waveforms and to double the output power compared to a single three-level inverter. Such an inverter system is used for feeding a drive motor with open stator windings. A mechanism is then required to reduce the common-mode voltage components of the motor voltages. This paper describes an offline optimization method that minimizes both the harmonic distortion of the motor currents and the common-mode voltage components. The optimization permits reduction of the switching frequency to a very low value of 200 Hz without compromising the harmonic distortion. High performance operation of the drive system at low switching frequency is experimentally demonstrated. [ABSTRACT FROM PUBLISHER]

In this paper, an improved pulse width modulation (PWM) method for chopper-cell (or half-bridge)based modular multilevel converters (MMCs) is proposed. This method can generate an output voltage with maximally 2N+1 (where N is the number of submodules in the upper or lower arm of MMC) levels, which is as great as that of the carrier-phase-shifted PWM (CPSPWM) method. However, no phase-shifted carrier is needed. Compared with the existing submodule unified pulse width modulated (SUPWM) method, the level number of the output voltage is almost doubled and the height of the step in the staircase voltage is reduced by 50%. Meanwhile, the equivalent switching frequency in the output voltage is twice that of the conventional SUPWM method. All these features lead to much reduced harmonic content in the output voltage. What is more, the voltages of the submodule capacitors can be well balanced without any close-loop voltage balancing controllers which are mandatory in the CPSPWM schemes. Simulation and experimental results on a MMC-based inverter show validity of the proposed method. [ABSTRACT FROM AUTHOR]

A six-switch three-phase inverter is widely used in a high-power grid-connected system. However, the antiparallel diodes in the topology operate in the hard-switching state under the traditional control method causing severe switch loss and high electromagnetic interference problems. In order to solve the problem, this paper proposes a topology of the traditional six-switch three-phase inverter but with an additional switch and gave a new space vector modulation (SVM) scheme. In this way, the inverter can realize zero-voltage switching (ZVS) operation in all switching devices and suppress the reverse recovery current in all antiparallel diodes very well. And all the switches can operate at a fixed frequency with the new SVM scheme and have the same voltage stress as the dc-link voltage. In grid-connected application, the inverter can achieve ZVS in all the switches under the load with unity power factor or less. The aforementioned theory is verified in a 30-kW inverter prototype. [ABSTRACT FROM AUTHOR]

Multilevel inverters have been widely accepted for high-power high-voltage applications. Their performance is highly superior to that of conventional two-level inverters due to reduced harmonic distortion, lower electromagnetic interference, and higher dc link voltages. However, it has some disadvantages such as increased number of components, complex pulsewidth modulation control method, and voltage-balancing problem. In this paper, a new topology with a reversing-voltage component is proposed to improve the multilevel performance by compensating the disadvantages mentioned. This topology requires fewer components compared to existing inverters (particularly in higher levels) and requires fewer carrier signals and gate drives. Therefore, the overall cost and complexity are greatly reduced particularly for higher output voltage levels. Finally, a prototype of the seven-level proposed topology is built and tested to show the performance of the inverter by experimental results. [ABSTRACT FROM PUBLISHER]

In this paper, a novel single-phase five-level inverter is proposed using coupled inductors. This inverter can output five-level voltage with only one dc source. No split of the dc voltage capacitor is needed, totally avoiding the voltage balancing problem in conventional multilevel inverters. The level of the output voltage is only half of the dc-link voltage in all conditions, leading to much reduced dv/dt . This inverter is based on the widely used three-arm power module and the voltage stresses on all the power switches are the same, making it very easy to construct. Operation mechanism of this inverter is analyzed and the possible switching patterns are investigated. Based on these analyses, a novel optimized modulation scheme is presented. With this modulation method, no dc components exist in the inductor currents, which is very helpful for minimization of the inductors. Simulation and experimental results show the validity of the proposed inverter together with the optimized modulation scheme. [ABSTRACT FROM AUTHOR]

Sliding mode control (SMC) is recognized as robust controller with a high stability in a wide range of operating conditions, although it suffers from chattering problem. In addition, it cannot be directly applied to multiswitches power converters. In this paper, a high performance and fixed switching frequency sliding mode controller is proposed for a single-phase unipolar inverter. The chattering problem of SMC is eliminated by smoothing the control law in a narrow boundary layer, and a pulsewidth modulator produces the fixed frequency switching law for the inverter. The smoothing procedure is based on limitation of pulsewidth modulator. Although the smoothed control law limits the performance of SMC, regulation and dynamic response of the inverter output voltage are in an acceptable superior range. The performance of the proposed controller is verified by both simulation and experiments on a prototype 6-kVA inverter. The experimental results show that the total harmonic distortion of the output voltage is less than 1.1% and 1.7% at maximum linear and nonlinear load, respectively. Furthermore, the output dynamic performance of the inverter strictly conforms the standard IEC62040-3. Moreover, the measured efficiency of the inverter in the worst condition is better than 95.5%. [ABSTRACT FROM AUTHOR]

This paper proposes a three-phase current reconstruction technique with an online current offset compensation function for three-phase inverter applications utilizing only a single current sensor. In the proposed current sensing method, a phase current and a branch current are simultaneously measured twice in a switching period by using a single current sensor. After that, the current reconstruction algorithm is applied to obtain the three-phase current information. Compared to previous single current sensor strategies, in the proposed method, the sensor output is regularly sampled, and the dead zone is located near the boundary of the voltage vector space instead of near the origin and the borders of each sector. This boundary-neighbored dead zone makes the proposed method more attractive in extremely low modulation index cases because it avoids periodical dead zones which have been an issue in the existing methods. Moreover, the online compensation method for a current measurement offset makes it possible to achieve purely balanced three-phase current control without an offset component. The effectiveness of the proposed method has been verified through simulations and experiments by measuring and reconstructing three-phase currents under various conditions. [ABSTRACT FROM PUBLISHER]

This paper presents a new type of three-phase voltage source inverter (VSI), called three-phase dual-buck inverter. The proposed inverter does not need dead time, and thus avoids the shoot-through problems of traditional VSIs, and leads to greatly enhanced system reliability. Though it is still a hard-switching inverter, the topology allows the use of power MOSFETs as the active devices instead of IGBTs typically employed by traditional hard-switching VSIs. As a result, the inverter has the benefit of lower switching loss, and it can be designed at higher switching frequency to reduce current ripple and the size of passive components. A unified pulsewidth modulation (PWM) is introduced to reduce computational burden in real-time implementation. Different PWM methods were applied to a three-phase dual-buck inverter, including sinusoidal PWM (SPWM), space vector PWM (SVPWM) and discontinuous space vector PWM (DSVPWM). A 2.5 kW prototype of a three-phase dual-buck inverter and its control system has been designed and tested under different dc bus voltage and modulation index conditions to verify the feasibility of the circuit, the effectiveness of the controller, and to compare the features of different PWMs. Efficiency measurement of different PWMs has been conducted, and the inverter sees peak efficiency of 98.8% with DSVPWM. [ABSTRACT FROM AUTHOR]

This paper proposes a current-error space-vector-based hysteresis controller with online computation of boundary for two-level inverter-fed induction motor (IM) drives. The proposed hysteresis controller has got all advantages of conventional current-error space-vector-based hysteresis controllers like quick transient response, simplicity, adjacent voltage vector switching, etc. Major advantage of the proposed controller-based voltage-source-inverters-fed drive is that phase voltage frequency spectrum produced is exactly similar to that of a constant switching frequency space-vector pulsewidth modulated (SVPWM) inverter. In this proposed hysteresis controller, stator voltages along α- and β-axes are estimated during zero and active voltage vector periods using current errors along α- and β-axes and steady-state model of IM. Online computation of hysteresis boundary is carried out using estimated stator voltages in the proposed hysteresis controller. The proposed scheme is simple and capable of taking inverter upto six-step-mode operation, if demanded by drive system. The proposed hysteresis-controller-based inverter-fed drive scheme is experimentally verified. The steady state and transient performance of the proposed scheme is extensively tested. The experimental results are giving constant frequency spectrum for phase voltage similar to that of constant frequency SVPWM inverter-fed drive. [ABSTRACT FROM AUTHOR]

Bitstream-based control, which uses one-bit-wide signals to control power electronics applications, is a new approach for controller design. Bit-Stream signals can be directly applied to control electronic devices, but the high-frequency nature of bitstream signals can lead to excessive switching losses. Thus, it is essential to downsample bitstream signals to reduce switching losses to acceptable levels. This paper presents a novel modulator, which downsamples high-frequency bitstreams to low-frequency switching signals that are suitable for driving two-level half-bridge or three-level full-bridge inverters. Methods for compensating for switch dead time and balancing switching losses of the inverter legs are presented, and the performance of the proposed modulators are compared to the standard pulse width modulation strategies. Simulation and experimental results of a 2-kW single-phase inverter show that the proposed bitstream modulators consume fewer logic resources, produce spread-spectrum output currents, and can deliver lower total harmonic distortion than similar fixed-frequency pulse width modulators. [ABSTRACT FROM AUTHOR]

A three-level inverter produces six active vectors, each of normalized magnitudes 1, 0.866, and 0.5, besides a zero vector. The vectors of relative length 0.5 are termed pivot vectors. The three nearest voltage vectors are usually used to synthesize the reference vector. In most continuous pulsewidth-modulation (PWM) schemes, the switching sequence begins from a pivot vector and ends with the same pivot vector. Thus, the pivot vector is applied twice in a subcycle or half-carrier cycle. This paper proposes and investigates alternative switching sequences, which use the pivot vector only once but employ one of the other two vectors twice within the subcycle. The total harmonic distortion (THD) in the fundamental line current pertaining to these novel sequences is studied theoretically as well as experimentally over the whole range of modulation. Compared with centered space vector PWM, two of the proposed sequences lead to reduced THD at high modulation indices at a given average switching frequency. [ABSTRACT FROM PUBLISHER]

This paper extends the Z-source concept to matrix converters and explores a family of Z-source matrix converters. Their principles and characteristics are analyzed, and a simplified voltage-fed Z-source matrix converter is used as an example to demonstrate its operation, voltage gain versus modulation index, PWM method, boost control, and implementation of the control. Both simulation and experimental results verify operation of the proposed Z-source matrix converter, analytical results, and control method. The Z-source converters can achieve buck and boost operation with reduced number of switches needed, therefore achieving low cost, high efficiency, and reliability, compared to the traditional matrix converters. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) is responsible for overvoltage stress to the winding insulation and bearing damage of an ac motor. High dv/dt of CMV raises leakage currents, which can cause serious problems such as motor damage and electromagnetic noise to the equipment installed near the converter. This paper proposes two modulation strategies for indirect matrix converters that substantially eliminate CMV. The first method is developed by using the suitable couple of nonzero space vectors instead of zero space vectors in the inverter stage. The maximum voltage transfer ratio of this method is unaffected and remains 0.866. The second one, which is useful for low-voltage operation, is approached by choosing the medium and the lowest positive line-to-line input voltages in the rectifier stage to generate the dc-link voltage and by placing suitable zero space vectors in the inverter stage. In the second method, the maximum voltage transfer ratio is 0.5. Both methods can mitigate the peak value to 42%. In addition, while the first method provides the same performance to the conventional method, the second method can reduce significantly the harmonic components of line-to-line output voltage. Simulation and experimental results are shown to verify the effectiveness of the proposed methods. [ABSTRACT FROM AUTHOR]

This paper presents a feasibility investigation of a zero-voltage switching (ZVS) pulsewidth modulation (PWM) dc-dc converter with secondary-side phase-shifting power control scheme. The ZVS-PWM dc-dc converter treated here can achieve soft commutation in all the power devices under the wide range of output power variation. By the phase-shifting control that is based on the secondary-side rectifier linked with a high-frequency planar transformer, the effective reduction of idling power in the primary-side inverter as well as snubber-less rectifications in the secondary-side rectifier can be actually attained. The essential experimental data obtained from a 100-kHz/2.5-kW prototype are described herein to validate the soft-switching circuit and control scheme, and then the effectiveness of the dc-dc converter is discussed and evaluated from a practical point of view. [ABSTRACT FROM AUTHOR]

This paper presents first an overview of the well-known voltage and current dc-link converter topologies used to implement a three-phase PWM ac–ac converter system. Starting from the voltage source inverter and the current source rectifier, the basics of space vector modulation are summarized. Based on that, the topology of the indirect matrix converter (IMC) and its modulation are gradually developed from a voltage dc-link back-to-back converter by omitting the dc-link capacitor. In the next step, the topology of the conventional (direct) matrix converter (CMC) is introduced, and the relationship between the IMC and the CMCs is discussed in a figurative manner by investigating the switching states. Subsequently, three-phase ac–ac buck-type chopper circuits are considered as a special case of matrix converters (MCs), and a summary of extended MC topologies is provided, including three-level and hybrid MCs. Therewith, a common knowledge basis of the individual converter topologies is established. [ABSTRACT FROM PUBLISHER]

Instead of directly sampling the phase currents, a technique that adopts a single current sensor in the dc link to reconstruct three-phase currents has arisen. Through this approach, the cost of servo systems can be reduced and the reliability can be improved. However, the duration of an effective vector may be so short that the phase current cannot be measured reliably by the conventional space-vector pulsewidth modulation (PWM) algorithm. In this paper, a new phase-current reconstruction method, switching-state phase shift (SSPS), is proposed based on the PWM pattern modification. The modification is performed by applying phase shifts to the switching-state waveforms of the inverter. The algorithm can realize high-quality reconstruction to the phase current with less impacts on the output current ripples and switching losses. Moreover, it can maximize the linear-modulation region by saturation handling. Measurements on the permanent-magnet synchronous motor servo drives show that the SSPS can offer an attractive performance during both steady-state and dynamic operations in the phase-current reconstruction and regulation. [ABSTRACT FROM PUBLISHER]

In this paper, two space-vector-based pulsewidth modulation (PWM) (SVPWM) strategies named equal- and proportional-duty SVPWMs are described, which are used to synthesize a four-level waveform from an open-end winding configuration of an induction motor. Two isolated dc-link voltages, which are in the ratio of 2 : 1, are employed to achieve this objective. Both of these PWM strategies achieve the avoidance of overcharging of the dc-link capacitor of an inverter operating with lower dc-link voltage by its counterpart with higher dc-link voltage. Implementation of these PWM strategies requires only the instantaneous three-phase reference voltages, eliminating the need of sector identification or lookup tables. The numbers of samples per cycle for individual inverters are selected in such a way that the quarter-wave, half-wave, and three-phase symmetries are achieved for the dual-inverter drive despite unequal dc-link voltages for the constituent inverters. It is also shown that one of the two PWM techniques, called the proportional-duty SVPWM, results in a better spectral performance and lower switching power loss in the overall dual-inverter system compared to the equal-duty SVPWM. [ABSTRACT FROM PUBLISHER]

This paper presents a comprehensive analytical investigation of the four-switch three-phase (B4) voltage source inverter. The double Fourier integral analysis is used as an analytical approach to determine the phase-leg switched voltage spectrum under condition of natural sampling. The performance of two proposed switching sequences are subsequently evaluated when the harmonic copper losses are chosen as performance criterion. For a clear identification of dc-link voltage, the spectrum of dc-link current is characterized by convolution of switching function spectrum and corresponding phase current spectrum, in which fundamental component appears causing offset and fluctuation in dc-link two-capacitor voltages. The offset can be suppressed by certain switching states, whereas the effect of fluctuation must be neutralized through analytical compensation for modulating waveforms. Otherwise, symmetry of three-phase output currents and reliable operation of the system will not be retained. Finally, the analytically calculated spectrum of output voltage and dc-link current are demonstrated by comparing with those obtained by fast Fourier transform (FFT) analysis of simulated waveforms in MATLAB/SIMULINK. The capacitor voltage offset suppression and fluctuation effect neutralization are carried out by simulations and experiments, in which the results confirm the validity of the analytical investigation. [ABSTRACT FROM AUTHOR]

In medium-/high-power inverters, optimal pulse-width modulation (OPWM) is often used to reduce the switching frequency and at the same time, realize selective harmonic elimination (SHE). For both two-level and multilevel inverters, most selective harmonic elimination (SHE) studies are based on solving multiple variable high-order nonlinear equations. Furthermore, for multilevel inverters, SHE has been often studied based on the assumption of balanced dc levels and single switching per level. In this paper, the authors further developed harmonics injection and equal area criteria-based four-equation method to realize OPWM for two-level inverters and multilevel inverters with unbalanced dc sources. For the cases, where only small number of voltage levels are available, weight oriented junction point distribution is utilized to enhance the performance of the four-equation method. A case study of multilevel inverter at low-modulation index is used as an example. Compared with existing methods, the proposed method does not involve complex equation groups and is much easier to be utilized in the case of large number of switching angles, or multiple switching angles per voltage level in multilevel inverters. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to analyze carrier-based discontinuous pulse width modulation (DPWM) method for multilevel inverters. The separation of the offset into the main and additional components shows the use for analyzing PWM control characteristics of multilevel inverters. The results are then applied to propose a novel minimized loss DPWM method by varying the offset depending on peak values of three-phase load currents. As results of avoiding commutations at high currents, the switching loss can be reduced. The proposed method is theoretically analyzed and verified by experimental results. [ABSTRACT FROM AUTHOR]

This paper presents direct digital technique-generalized discontinuous pulse width modulation (PWM)—a new implementation method for an optimal discontinuous PWM (DPWM) in terms of switching losses of the inverter on an embedded system. At each sampling period, an optimal choice is done in order to clamp one of the three half-bridges. Its advantages compared to classic ones (DPWM) are as follows: needless to know the load power factor, operational under steady-state and dynamic operating conditions, and low computation time. The proposed algorithm is then verified by simulation. Experimental results, based on a resistance–inductance load and a starter-generator application, are provided to show its effectiveness. [ABSTRACT FROM AUTHOR]

With regard to a five-level inverter comprising flying-capacitor asymmetric H-bridge, the impact on the capacitor voltage under conventional modulation approach is analyzed. Since it is sensitive to the fundamental period and the load current, it may introduce undesired low-order harmonics into the output voltage and may even break down the power switches due to the considerable fluctuation of the flying-capacitor voltage. Thus, this paper proposes a novel pulsewidth-modulation scheme with the positive and negative cross carriers, which controls the flying-capacitor voltage by utilizing the redundant switching states of the output voltages. Three modes of precharging the flying capacitor without extra equipments are presented. Moreover, the capacitance of the flying capacitor and the switching frequency of the power switches can be chosen according to the allowable fluctuation of the flying-capacitor voltage and the load current. In order to remove the overlapping of the level layers, the optimization of the line-to-line voltage waveform is proposed to synthesize the reference vector with the “nearest three-vector” approach. The theory is supported by the experimental results from the prototype. [ABSTRACT FROM AUTHOR]

Multilevel inverters introduce harmonics to the network besides their remarkable advantages. Total harmonic distortion (THD) is one of the most important indexes to evaluate the harmonic contents of waveforms. The conventional method of line-voltage THD calculation gives approximate answers, because high-order harmonics are ignored. In this paper, an analytical algebraic method based on formulating the line-voltage THD of multilevel inverters with unequal dc sources is presented. This method, which is general and applicable to each number of switching angles, is implemented to a five-level inverter with staircase waveform as a case study. The implementing process of this method can be easily repeated for each number of levels. The accuracy of the proposed method is illustrated in comparison with the approximate method. Some advantages of the extracted formulas of line-voltage THD are simplicity and rapidity in calculations, considering all harmonics and the possibility of finding optimal switching angles analytically. Experimental results are presented to validate the theory. [ABSTRACT FROM PUBLISHER]

AC-fed railway traction drives suffer from pulsating input power because of the single-phase pulse width modulation rectifier at the front end. An LC filter is often needed at the dc link to absorb the pulsating power. However, this greatly reduces the power density. An effective way to get rid of this clumsy filter is to compensate pulse width calculation of the traction inverter so that it does not produce harmful subharmonics (beat components) in the output voltage/current even with a fluctuating dc link. For limited switching frequency at high power level, it is difficult for conventional feed-forward compensation methods to achieve good results. A repetitive dc link voltage predictor is proposed in this paper to improve the compensation performance. It capitalizes on the repetitiveness of the dc link ripple and can predict the average value of the dc link voltage in the next switching period. An area-equalization-based algorithm is then used to calculate the required pulse width. Experiments show that compared with conventional methods, the proposed one can reduce the steady-state beat current by six to seven times. The dynamic beat current during load transients is also negligible when dynamic drop of the dc link voltage is kept below 10%. [ABSTRACT FROM AUTHOR]

The novel multilevel circuit topologies are proposed in this paper. They are called multilevel circuit topologies based on switched-capacitor and diode-clamped converters (MCT-BSD). The topology structure and the operation principle, including the working states’ transitions of the diode-clamped part, the voltages balancing mechanism of the dc link capacitors, and the pulse width modulated carrier control strategy are given. The switched-capacitor circuits contribute not only to balancing the voltages of capacitors but also to boosting the output voltage with a certain input dc voltage. The validity of the MCT-BSD is verified by simulations and experiments. The results show that balancing the voltages of capacitors, boosting the output voltages, and operating under the three-phase condition are all realized effectively in the MCT-BSD. The simulations also show the generalization of the MCT-BSD for n-level topologies. [ABSTRACT FROM AUTHOR]

This paper demonstrates improved performance of a three-phase voltage source inverter (VSI) when digital multisampled space vector modulation is used. The modulator and the inverter controller are implemented entirely using a field-programmable gate array platform, thus achieving increased bandwidth with respect to a typical digital signal processor or microprocessor-based controller. Increased controller bandwidth results in lower output voltage harmonic distortion in the frequency range above the fundamental and below the switching frequency. Experimental validation is presented together with the analysis carried out using a state space model of a VSI with an output LC filter. [ABSTRACT FROM AUTHOR]

The operation of switch-mode converters results in electromagnetic noise propagating throughout the power electronic system. Pulsewidth modulation (PWM) strategies with fixed switching frequency generate harmonics in the spectra of converter voltages and currents. Random PWM techniques allow the elimination of the harmonics, resulting in a continuous spectrum of noise, i.e., a spectrum retaining all frequency components. As a next step in advanced spectral shaping, a method presented in this paper produces spectral nulls at selected frequencies. This allows the carving of communication channels in the noise and the removal of spectral power at frequencies potentially harmful for the system. The theoretical analysis, computer simulations, implementation details, and experimental results are presented. [ABSTRACT FROM AUTHOR]

This paper proposes a single-phase seven-level inverter for grid-connected photovoltaic systems, with a novel pulsewidth-modulated (PWM) control scheme. Three reference signals that are identical to each other with an offset that is equivalent to the amplitude of the triangular carrier signal were used to generate the PWM signals. The inverter is capable of producing seven levels of output-voltage levels (Vdc, 2Vdc/3, Vdc/3, 0, -Vdc, -2Vdc/3, -Vdc/3) from the dc supply voltage. A digital proportional–integral current-control algorithm was implemented in a TMS320F2812 DSP to keep the current injected into the grid sinusoidal. The proposed system was verified through simulation and implemented in a prototype. [ABSTRACT FROM AUTHOR]

Motivated by the method to analyze the impact of dead time in hard-switching converters, this paper, for the first time, analyzes the impact of zero-voltage notches on the outputs of soft-switching pulsewidth modulation (PWM) converters. It proves that the output distortion of soft-switching converters due to their deviation voltage is independent of the direction of their output current. Hence, their compensation strategies require no sensor to detect the current's direction, which is required by dead-time compensation methods in hard-switching converters. A simple yet effective compensation algorithm is presented for soft-switching converters. The analysis result and effectiveness of the proposed algorithm are experimentally verified via a three-phase inverter that represents an important class of converters. [ABSTRACT FROM AUTHOR]

The flying capacitor multicell inverter (FCMI) possesses natural balancing property. With the phase-shifted carrier-based scheme, natural balancing can be achieved in a straightforward manner. However, to achieve natural balancing with the harmonically optimal phase-disposition (PD) carrier-based scheme, the conventional approaches require (n − 1) × (n − 1) trapezoidal carrier signals for an n-level inverter, which is ( n − 1) × (n − 2) times more than that in the standard PD scheme. This paper proposes two improved natural balancing strategies for FCMI under PD scheme, which use the same (n − 1) carrier signals as used in the standard PD scheme. In the first scheme, the on-line detections are performed of (i) the band in which the modulation signal is located, (ii) corresponding period number of the carrier, and (iii) rising or falling half cycle of the carrier waveform to generate the switching signals based on certain rules. In the second strategy, the output voltage level selection is first processed and the switching signals are then generated according to a rule based on preferential cell selection algorithm. These methods are easy to use and can be simply implemented as compared to the other available methods. Simulation and experimental results are presented for a five-level inverter to verify these proposed schemes. [ABSTRACT FROM AUTHOR]

Control and modulation schemes for ac electrical drives synthesize switched three-phase voltage waveforms that control the electrical machine. Particularly in medium-voltage applications, the aim is to minimize both the switching losses in the inverter and the harmonic distortions of the stator currents and the torque. For a given modulation scheme, lower switching losses usually imply higher distortion factors and vice versa. This tradeoff can be described by a hyperbolic function, as shown in this paper for pulsewidth modulation (PWM). A number of predictive control concepts are rapidly emerging. Their characteristic hyperbolic tradeoff functions are derived, compared with each other, and benchmarked with respect to PWM and offline optimized pulse patterns (OPPs). It is shown that predictive schemes with long prediction horizons shift the performance tradeoff curve toward the origin, thus lowering both the switching losses and the harmonic distortions. As a result, at steady-state operating conditions, these predictive schemes achieve a performance similar to OPPs, while providing a superior dynamic performance during transients. [ABSTRACT FROM AUTHOR]

Unipolar sinusoidal pulsewidth modulation (SPWM) full-bridge inverter brings high-frequency common-mode voltage, which restricts its application in transformerless photovoltaic grid-connected inverters. In order to solve this problem, an optimized full-bridge structure with two additional switches and a capacitor divider is proposed in this paper, which guarantees that a freewheeling path is clamped to half input voltage in the freewheeling period. Sequentially, the high-frequency common-mode voltage has been avoided in the unipolar SPWM full-bridge inverter, and the output current flows through only three switches in the power processing period. In addition, a clamping branch makes the voltage stress of the added switches be equal to half input voltage. The operation and clamping modes are analyzed, and the total losses of power device of several existing topologies and proposed topology are fairly calculated. Finally, the common-mode performance of these topologies is compared by a universal prototype inverter rated at 1 kW. [ABSTRACT FROM AUTHOR]

This paper presents a set of novel soft-switching techniques to increase the power conversion efficiency in fuel cell (FC) systems using a full-bridge topology. For this purpose, a special right-aligned modulation sequence is developed to minimize conduction losses while maintaining soft-switching characteristics in the MOSFETs. Traditional auxiliary elements in the primary, such as series inductors that are impractical for realizing due to the extreme input current, are avoided and reflected to the output of the rectifier to minimize circulating current and generate soft transitions in the output diodes. As a result, the proposed combined techniques successfully reduce conduction losses, minimize reverse-recovery losses in the output rectifiers, minimize transformer ringing, and ensure low stress in all the switches. The high efficiency is maintained in the entire range of loading conditions (0%–100%) while taking into consideration remarkable challenges associated with FC power conversion: high input current, low voltage and poor regulation, and wide range of loading conditions. A detailed analysis of the techniques for efficiency gains are presented and a phase-shift zero-voltage switching topology is employed as a reference topology to highlight the mechanisms for performance enhancement and the advantages in the use of the special modulation. Experimental results of a 1-kW power converter are presented to validate the efficiency gains, illustrate the benefits of the special modulation, and demonstrate the soft-switching transitions. [ABSTRACT FROM PUBLISHER]

In this paper, a passive lossless snubber circuit for pulse width modulation (PWM) inverters is proposed to achieve soft-switching purpose without extra switch or additional control circuitry. This passive lossless soft-switching snubber employs an inductor/capacitor snubber structure for each switching device in an inverter to achieve passive zero-current turn ON and zero-voltage turn OFF. Furthermore, inductors coupled closely on a single core are used to losslessly recover snubber energy to the input in the proposed snubber. In addition, freewheeling of output phase current of inverters can be realized via energy storage components of the snubber during the dead time to reduce the effect of dead time. The distortion ratio of the output phase current in low output frequency is also reduced. All components in the snubber circuit are passive, and thus have a better price/performance ratio than their active counterparts. The proposed snubber has been incorporated into a 14-kW PWM inverter. Experimental results are given to demonstrate the validity and features of the snubber. [ABSTRACT FROM PUBLISHER]

This paper presents a three-stage 18-level inverter design with a novel control method. The inverter consists of a series-connected main high-voltage, medium-voltage, and low-voltage stages. The high-voltage stage is made of a three-phase, six-switch conventional inverter. The medium- and low-voltage stages are made of three-level inverters constructed by H-bridge units. The proposed control strategy assumes a reference-input voltage vector and aims to operate the inverter in one state per sampling time to produce the nearest vector to that reference. The control concept is based on representing the reference voltage in 60^\circ-spaced two-axis coordinate system. In this system, the inverter vectors’ dimensions are integer multiples of the inverter's dc voltage, and the expression of the inverter's vectors in terms of its switching variables is straightforward. Consequently, the switching signals can be obtained by simple fixed-point calculations. The approach of the proposed control strategy has been presented, the transformed inverter vectors and their relation to the switching variables have been defined, and the implementation process has been described. The test results verify the effectiveness of the proposed strategy in terms of computational efficiency as well as the capability of the inverter to produce very low distorted voltage with low-switching losses. [ABSTRACT FROM PUBLISHER]

Half-cycle symmetry selective-harmonic-elimination pulsewidth-modulation (SHE-PWM) problems may have a large number of valid solutions, which are beneficial to the optimization design. This paper proposes a novel generalized formulation of half-cycle symmetry SHE-PWM problems for multilevel inverters. The advantages of the proposed formulation include simplicity in format, flexibility in PWMwaveforms, and a broad solution space. A method to obtain initial values for the SHE-PWM equations according to the reference modulation index M and the initial phase angle of output fundamental voltage is proposed and investigated thoroughly. Take a five-level inverter with M = 0.75 as an example; six sets of solutions for two typical initial phase angles of 0°? and 90°? are presented. Simulations and experiments are carried out. It is demonstrated that the experimental results agree well with simulated ones, which proves the validity and practicability of the new method proposed. [ABSTRACT FROM AUTHOR]

Presents a comments on the paper, "Nearest and non-nearest three vector modulations of NPCI using two-level space vector diagram - a novel approach," (Babu, N. and Agarwal, P.), IEEE Trans. Ind. Electron., vol. 60, no. 5, pp. 1999-2009, 2013. [ABSTRACT FROM AUTHOR]

This paper describes the design of a compact and highly repetitive pulsed power modulator based on semiconductor switches. Output specifications of the proposed modulator are as follows: variable output pulse voltage, 1-10 kV; width, 1-10 μs; pulse repetition rate (PRR), 1-50,000 pps; and average output power, 10 kW. The proposed solid-state pulsed power modulator has two main parts: an IGBT stack that hasa gate drive circuit for the pulse output with a variable pulse width and repetition rate, and a capacitor charger that has a controllable output voltage. To connect all the storage capacitors in a series for high voltage pulses, a simple and reliable IGBT stack structure was proposed based on the Marx generator. In addition, the gate driver circuit, which supplies power and signals to all the IGBTs simultaneously, was introduced. This providesa superior protection function against the arc and the short. To charge the storage capacitors, a novel 10 kW (10 kV, 1 A) high voltage capacitor charger with the combined advantageof a series-loaded resonant converter and a ZVS (zero-voltage-switching) full-bridge pulse width modulation (PWM) converter was proposed and designed especially for the solid-state pulsed power modulator. Theexperiment results verified that the proposed scheme and structure can be used effectively for a high voltage pulsed power modulator that requires variable voltage, repetition rate, and pulse width, depending on the process of the applications. [ABSTRACT FROM AUTHOR]