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This paper presents an innovative cross-coupled differential drive rectifier for dual-band Radio frequency identification (RFID) tags. A self-compensating rectifier with enhanced power-conversion efficiency (PCE) at low and high RF power is proposed. The proposed rectifier utilizes a self-compensating circuit, the extra two cross-couple transistors, to increase the gate voltage of transistors to control the conduction of the rectifying transistors. In order to adapt high frequency (HF) and ultrahigh frequency (UHF) rectification, the matching circuit is designed with parasitic cancellation technology. Moreover, the cascading power management circuits are added to generate a stable output voltage. The multi-standard rectifier is designed and simulated in 0. 1 8 μ m CMOS process. The simulated result shows that the proposed three-stage rectifier achieves a PCE 74% (at 5 0 0 k Ω load) when receiving a 915 MHz signal with average power of − 2 5 dBm. Moreover, the maximum efficiency achieves 56% at HF 13.56 MHz, and the final output voltage can be stabilized at a specific voltage of 1.052 V. [ABSTRACT FROM AUTHOR]

This paper presents a low-ripple and high-efficiency buck–boost DC–DC converter with delta-sigma modulator controller that converts 1.8 V to 1.2 V and 3.3 V. A current and voltage closed-loop controller has been designed to achieve better performance simultaneously such as lower settling-time, steady-state error and over shoot and under shoot. The converter is started in the current controller mode initially, when the output voltage approaches the desired value, the power stage is controlled with the voltage controller mode. PI compensator and a third-order delta-sigma modulator are utilized in the voltage mode. Also, the closed-loop stability of the designed converter has been analyzed with Lyapunov method using converter nonlinear model. This work has been simulated in MATLAB-SIMULINK environment. The performance results show that the maximum efficiency of the closed-loop DC–DC converter is 90% at 5 MHz switching frequency, and the output voltage ripple is 0.5% and 0.6% for the buck and boost modes, respectively. Also, the simulation results demonstrate the closed-loop stability of the converter in the presence of 10% load variation. [ABSTRACT FROM AUTHOR]

Locally-active memristors blessed with an edge-of-chaos domain, which can be destabilized for generating action potentials, are natural candidates for emulating biological neurons. Pinpointing the edge-of-chaos domain, where neuromorphic behaviors may occur, is important for studying neuromorphic dynamics of memristors. This paper proposes a short-cut method for locating the edge-of-chaos domains in two kinds of generic memristors, and in several typical memristive 1-port circuits using only the Jacobian matrix in terms of their equations. Taking the Chua Corsage Memristor (CCM) and several CCM-based memristive 1-port circuits as examples, we verify the proposed new methods, and calculates their edge-of-chaos domains. Also, we carry out a complete classification of all the parameter regions of the CCM and several CCM-based memristive 1-port circuits, namely the locally-passive, locally-active but unstable, and edge-of-chaos domains, under both voltage and frequency control. Near the calculated edge-of-chaos domain, we uncover some new neuromorphic behaviors. To confirm the physical interpretations and predictions of the edge-of-chaos theorem, this paper presents an inexpensive electronic circuit realization of the complete set of equations defining the CCM using only off-the-shelf circuit components. When this poor-man's memristor is connected to various linear passive R, L, C circuits, and a battery, the resulting circuit can be tuned to generate action potentials, and a garden variety of neuromorphic phenomena, including chaos. But the highlight of this paper is reserved for the CCM itself where the world's first oscilloscope picture of a contiguous self-intersecting triple-branch DC V–I curve of the CCM is displayed in real time. [ABSTRACT FROM AUTHOR]

Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ( g m ) is the main dominant source of frequency and gain ( K VCO ) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates ≈ 3 times variation in K VCO across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5 GHz is developed in 65 nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum K VCO variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4 mW power from 1 V power supply. [ABSTRACT FROM AUTHOR]

The realization of capacitance multiplier using the versatile active building block, namely voltage differencing differential difference amplifier (VDDDA) is presented in this paper. The realized capacitance multiplier is very simple consisting of one VDDDA, one MOS resistor ( R M) and one grounded capacitor which is attractive for integration. The multiplication factor (KC) of the realized circuit can be electronically controlled via the bias current ( I B) and control voltage ( V C) without the need of any matching condition of active and passive element. Moreover, the multiplication factor can be adjusted to be more or less than one. The performances of the presented capacitance multiplier are verified through Pspice simulation using CMOS VDDDA in 0.18 μ m TSMC technology with ± 0. 9 V power supplies. The multiplication factor is designed to be K C = 2 by choosing V C = 0. 8 5 V, I B = 5 0 μ A and C = 3 0 pF. The simulated multiplication factor is around 1.98. The simulated operational frequency range is around three decades (6.16 kHz–8.91 MHz). The performances of the proposed circuit are also verified by the experiment using VDDDA implemented from the commercial ICs, AD830 and LM13700 with ± 5 V power supplies. The experiment is conducted under the same multiplication factor ( K C = 2) as the simulation by choosing R M = 0. 2 7 k Ω (1% passive resistor), I B = 9 6. 2 μ A and C = 1 nF. The experimental multiplication factor is around 2.06. The experimental operational frequency range is around three decades (1 kHz–1.25 MHz). By adjusting the bias current from 17.67 μ A to 400 μ A, the experimental multiplication factor is controllable from 11.47 to 0.48. The percent deviation of the theoretical and experimental multiplication factor is lower than 5% when the value of bias current is greater than 39 μ A. These deviations stem from the effect of the parasitic capacitance and resistance in VDDDA. Moreover, the application example of the presented capacitance multiplier as the sinusoidal oscillator is presented. The performances of the presented oscillator verified via the experiment are well consistent with theoretical anticipation. [ABSTRACT FROM AUTHOR]

This paper presents the design of a Chirp Spread Spectrum (CSS), ultra-wideband (UWB), pulse generator (PG) and device mismatch impact on its performance. The proposed CSS-PG is built using a differential ring oscillator (RO) controlled by a ramp generator, allowing varying linearly the pulse frequency with time over the CSS pulse duration. Device mismatches and random variations during integrated circuit manufacturing are the most critical imperfections in high precision differential UWB voltage controlled RO circuit. These mismatches lead to behavioral variations of the PG. The proposed CSS-UWB-PG is designed and analyzed using CMOS 0.18 μ m technology. The CSS-PG presents an output swing of 266 mV Vpp for 20 nsec and consumes 1.72 mW for a PRF of 10 MHz. The simulated PSD covers the UWB low band from 3 GHz to 5 GHz and complies with the FCC regulations. For V th mismatch, the simulation results show a maximum relative accuracy on oscillation frequency and phase noise of 3.43% and 6.9%, respectively. Monte Carlo and process simulation are performed to study the impact of the random parameter variation on this CSS-PG. Theses simulations show the robustness of the proposed design as the PG PSD is still inside the FCC-UWB mask and its bandwidth is greater than 500 MHz. [ABSTRACT FROM AUTHOR]

High-brightness light-emitting diode (LED) lamps have attracted much attention because of their high efficiency, simple structure, energy conservation and environmental protection aspects, and long lifetime. Thus, an LED driver must have a long lifespan, high density, and compact space. However, conventional LED power supplies use an electrolytic capacitor as the storage capacitor in the holdup time, which has a short lifespan and occupies large space. In this paper, a novel synchronous current-doubler rectifier (SCDR) method is proposed as an LED driver. The reasonably designed circuit is used to control the output voltage ripple in the normal range without adding a complicated control circuit. The proposed topology is designed using few components, has no electrolytic capacitor, and has a low cost for high-output current LED driver applications. Circuit operating principles and detailed theoretical analysis are provided in this paper. A 200-W prototype has been established and tested, and the experimental results are presented to highlight the merits of the proposed circuit. [ABSTRACT FROM AUTHOR]

This paper proposes a control scheme that enhances both the power quality and voltage synchronization of the Self-Excited Induction Generator (SEIG) driven by a wind turbine supplying power to a remote region. A reactive power constraint of SEIG under load disturbances is balanced by a modified Second-Order Generalized Integrator (SOGI) with Fuzzy Logical Controller (FLC) controlled Quasi-Impedance (QZ) source network-based Static Compensator (STATCOM). The combination of STATCOM and the photovoltaic system, battery and flywheel enhances the active power potential of conventional STATCOMs by means of a hybridized STATCOM system. This system is intended for the optimum use of energy generated from renewable energy sources by physical energy storage systems such as flywheels and batteries. This tends to compensate for the deviation of both active and reactive power and hence increase in active power, reliability and system stability. For analyzing device behavior, the dynamic hybrid STATCOM model with FLC dependent ESOGI has been developed. In standalone operation, simulated and experimental findings indicate the increased capability and system efficiency under variable load conditions. [ABSTRACT FROM AUTHOR]

The paper presents a two-phase interleaved boost converter (IBC) providing higher step-up conversion ratio compared to the conventional IBC. The circuit consists of a crossly connected diode-capacitor cell which provides the extra boost up. The two identical capacitors of the cell are charged in parallel and discharged in series providing high voltage gain at considerably low duty ratio. Switching operations, ripple and average currents through inductors are analyzed in continuous conduction mode (CCM). Ripple in input current is also improved. The voltage stress across the semiconductor devices is less in the proposed converter. Also, boundary load condition is derived. Small-signal modeling is carried out and a control circuit is enabled in the voltage mode control framework. Power losses are analyzed and 96.53 % efficiency is achieved. Finally, the proposed converter is designed and implemented, and experimental results are provided. [ABSTRACT FROM AUTHOR]

Renewable energy sources and storage devices are combined as a hybrid energy system to provide reliable electricity to the load. Naturally, such sources have distinct voltage–current characteristics. In this paper, a dual input positive output voltage DC–DC converter is used as power electronic interface for integration of the above nature of sources. Different modes of operation of the above converter such as buck, boost and buck–boost are discussed with necessary circuit and equations. A detailed current and voltage stress analysis of various switching devices available in the converter is also discussed. This analysis helps to select the switching devices in an optimized and cost-effective manner. The effect of equivalent series resistance of such storage elements on the output voltage is investigated in detail. The MATLAB simulation of the power converter is carried out, and a prototype of the converter is also fabricated. A power control strategy is proposed for the power converter with the objective of voltage regulation during the load side and source side disturbances. Different experimental analyses of the fabricated converter in the laboratory environment have been conducted, and the test results are presented in this paper. [ABSTRACT FROM AUTHOR]

A cap-less voltage spike detection and correction circuit for flipped voltage follower (FVF)-based low dropout regulator (LDO) is proposed in this paper. The transients in the output voltage are controlled by the pull-up currents I UP1 and I UP2 and pull-down currents I DN1 and I DN2 . These currents are dynamic current sources which are activated only during transient period and noise contributed by these current sources at steady state is zero. These currents increase/decrease based on the intermediate FVF node voltage V X . The proposed circuit detects the output voltage via V X and controls the power MOSFET gate and output capacitances by changing the pull-up and pull-down currents whenever the load changes. The proposed circuit consumes small additional bias current in the steady state and achieves less settling time and output spike voltage. This LDO is simulated using 180 nm technology and the simulation result shows that the LDO has good load transient response with 190 ns settling time and 170 mV voltage spike over 1 mA to 100 mA load current range. [ABSTRACT FROM AUTHOR]

This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has six transistors (6T), two p-type MOS-FET and four n-type MOS-FET. By using the SWSFET, the size and the number of transistors are reduced and all of transistors are n-channel SWS-FET. This paper proposes two different models of the SWS-FET SRAM circuits with three transistors (3T) and four transistors (4T) also addresses the stability of the proposed SWS-FET SRAM circuits by using the N-curve analysis. The proposed models are based on integration between Berkeley Shortchannel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level. [ABSTRACT FROM AUTHOR]

In this paper, the design of a fuzzy rule-based MDPSM controlled buck converter is analyzed. Power factor improvement and harmonic minimization for the buck converter connected through the variable load with a fuzzy rule are discussed and simulated. The MDPSM controlled converter is supplied with 230 V and reaches 15 V as output. The converter output, always connected with nonlinear loads, causes less power factor with more harmonics and gives less power quality. Active PFC with a fuzzy-based voltage controlled power factor controller is designed to reduce total harmonics and to raise the power factor value equal to unity. The fuzzy-based MDPSM controller was designed using MATLAB Simulink. Controller output waveforms are examined and analyzed with other controller performances. The converter is rated with 2 mA, 0.5 mH and 212 μ F values with output power 48 W. The converter is tested for different resistive loads and inductive loads. [ABSTRACT FROM AUTHOR]

In this paper, an effective scheme of on-load startup with reduced current has been proposed for BLDC motor and the steady as well as dynamic performance in all four quadrants was verified. Hysteresis band-limited back EMF noise provides the starting pulses, the frequency of which depends on the threshold factor in speed proportional threshold. Scheme is quite fast, comparatively to the state-of-the art schemes of startup and less complex than time-consuming initial position detection (IPD) algorithm. Second-order least P th-norm infinite impulse response (IIR) digital low pass filter realized in MATLAB/Simulink has been used for extraction of line-to line back EMF from line-to-line terminal voltages measured with two voltage sensors. Proposed filter has wide flexibility of online variation of cut-off frequency, gain and phase without any circuit-based modification due to variability of filter coefficients. This enables the smooth filtering with minimized phase delay in low speed range irrespective of any duty cycle and PWM frequency. Linear compensation of phase error or phase advancement for desired current profile can easily be achieved by the varying the threshold factor. In this experiment, the threshold factor of 1/1460 has been found most suitable for smooth sensorless startup without jerk, vibration and reverse rotation, as the motor operates in advanced mode with this value. First, the performance of Hall sensor-based drive was studied using open loop variable duty cycle speed control. The controller was designed in MATLAB/Simulink platform and implemented using TMS320F28069M DSP control stick with Code composer Studio V5. Later on, a complete controller for proposed sensorless scheme was developed in MATLAB/Simulink environment and was implemented using NI-PCI6221 Controller installed in PC. The proposed sensorless drive has been found capable of operating at very low speed of 50 rpm in voltage control mode and 85 rpm in current chopping PWM mode. Approximately 85 ms less time was taken by sensorless drive to reach the same speed when compared with Hall-based control for identical loading. Also less overshoots during startup was observed. Overlap time of 0.05 ms between phase currents has been achieved during commutation period. [ABSTRACT FROM AUTHOR]

This paper presents a low power temperature compensated CMOS ring oscillator for biomedical applications across a wide temperature range. The proposed circuit deploys an IPTAT (inversely proportional to absolute temperature) bias current by generating an adaptive control voltage in each stage of the oscillator to compensate the overall oscillator's temperature coefficient (TC). Simulations using TSMC 0.18 μ m CMOS technology show that this configuration can achieve a frequency variation less than 0.25%, leading to an average frequency drift of 20.83 ppm/∘C. Monte Carlo simulations have also been performed and demonstrate a 3 σ deviation of about 2.15%. The power dissipated by the proposed circuit is only 8.48 mW at 25∘C. [ABSTRACT FROM AUTHOR]

This paper describes a low-voltage bulk-driven differential CMOS Schmitt trigger with tunable hysteresis for use in noise removal applications. The hysteresis of the proposed Schmitt trigger is designed based on a regenerative current feedback and its width is adjustable by two control voltages. The center of the hysteresis can also be adjusted by either the control voltages or input common-mode voltage. The principle operation of the proposed circuit is discussed, its main formulas are derived and its performance is verified by Cadence post-layout simulations. Designed in the TSMC 0.18 μ m standard CMOS process, the circuit consumes 3 9 × 1 7. 5 μ m2 of silicon area. Post-layout simulation results indicate that the hysteresis width of the Schmitt trigger can be adjusted from 170 to 270 mV and the ratio of the hysteresis width variation to supply voltage is 11.11%. Operated with 0.8 V supply voltage, the power consumption of the circuit ranges from 0.48 to 1.12 mW. [ABSTRACT FROM AUTHOR]

This paper presents a fault-tolerant Voltage Source Converter (VSC) for Field Oriented Control (FOC) of a stand-alone Doubly Fed Induction Generator (DFIG) connected to a DC load. In the proposed topology, the stator of the DFIG is connected to a DC load through a diode rectifier, while the rotor is connected to the DC load through a VSC. This topology allows the integration of DFIG in the hybrid system with other sources of production and storage, such as photovoltaic system, connected to the same DC bus. The fault-tolerant VSC consists in incorporating a fourth leg to replace the faulted leg. A fault detection scheme for switch device open-circuit faults is proposed in this study. The novelty of this method consists in analyzing the rotor currents within normal and faulty operating modes. Simulation results are presented for a 3.7kW DFIG-DC system with single open-circuit faults that validate the methods presented in this study. The effectiveness of the proposed fault detection method has been validated experimentally by using dSpace DS1104 control board based on TMS320F240 real time Digital Signal Processor (DSP). [ABSTRACT FROM AUTHOR]

This paper presents first-order voltage-mode filters using a single current conveyor with an additional X-stage, and passive elements. The new circuits have multifunction capability, and also realize low-shelf, high-shelf and band-shelf functions. The study is carried out on the effects of non-idealities, parasitic elements, and loading on the performance of proposed circuits. Active and passive sensitivities are also analyzed. The active element, extra-X current conveyor used for designing new circuits is simpler than most of the one active element and two passive elements’ based circuits. Detailed comparisons are carried out with relevant available works, and the new circuits are found to be more compact and exhibit higher frequency performances. The simulation results using 0.25μm CMOS parameters with ±1.25V power-supply are shown to verify the proposed circuits. The proposed circuits are also verified through simulations. Experimental support is given using AD-844 ICs to strengthen the validity of the proposed circuits. [ABSTRACT FROM AUTHOR]

In this paper, the excitation controller for a synchronous generator (SG) with an exciter is presented, based on novel stabilization feedback actions comprising the SG rotor current and rotor voltage measurements. The novel stabilizing feedback actions are used to compensate the dynamic lag introduced by the exciter machine, and to improve the overall excitation system's dynamic performance without employing differential control actions. Namely, by avoiding differential control actions, an improved level of performance can be achieved without compromising the control system's sensitivity in relation to the measurement noise. Also, compared with the existing solutions based on a different set of stabilizing feedback signals, the controlling structure proposed in this paper enables a more stable and faster dynamic response, which is illustrated in the paper by means of the system frequency response analysis. The performance of the proposed solution is verified through the set of simulation and experimental runs presented in the paper. While the controller design is based on a simplified generator model, the simulations are carried out using the full order generator and exciter models. The experimental tests were carried out on a 300 MW thermal power plant aggregate with an AC exciter. [ABSTRACT FROM AUTHOR]

This paper presents the design of C-CNTFET oscillator's arrays for infrared 'IR' technology. These arrays are contained by both of the LC-tank and the voltage control 'coupled N- and P-type C-CNTFET LC-tank' oscillators. In this paper, the analysis of the impact of CNT diameter variations and the nonlinear capacitances (CGD and CGS) were introduced, especially on propagation time, oscillation frequency and power consumption. The C-CNTFET inverter, ring oscillator, LC-tank and coupled N- and P-type C-CNTFET LC-tank oscillator structures were designed and their speeding and performances have been investigated with the proposed n-type of C-CNTFET model supplied by a 0.5 V power voltage. Simulation results show that the n- and p-types LC-tank oscillator circuit designs achieved an approximately equal oscillation frequency, response time and power consumption. Whereas the coupled N- and P-type C-CNTFET LC-tank oscillator has the lowest power consumption equal to 0.13 μW, the highest oscillation frequency (10.08 THz) and the fastest response time (1.81 ps). [ABSTRACT FROM AUTHOR]

This paper presents a reduced control set model predictive control (RCSMPC) method for three-phase T-type neutral-point-clamped (NPC) inverter. The whole control set (WCS) consists of all the 27 switching states of T-type NPC inverter. The reduced control set (RCS) with 19 switching states is formed from WCS by excluding the switching states with common mode voltage (CMV) value higher than one-sixth of input DC voltage . With RCS, single-objective model predictive current control method can restrict the CMV peak value to . To further reduce the CMV below this threshold, a cost function with the weighted sum of two control targets is formulated in the RCSMPC method. The two control targets of RCSMPC method are CMV mitigation and load current control. The weight for CMV is called bias factor. The RCSMPC method is computationally efficient, as the number of switching states is less than that of WCSMPC. To further reduce the computational burden, CMV values corresponding to all the switching states are calculated offline and stored in memory. Robustness of both the methods is investigated with parameter deviations at different bias factors and reference currents. The proposed method is validated using simulation and experimental results and compared with the existing methods. [ABSTRACT FROM AUTHOR]

The SrBaTiO3 (SBT) memristor is prepared using the monolayer SrBaTiO3 nano-film structure. In order to apply it into the nonlinear circuit design, the SBT memristor is modeled in the paper. The voltage-controlled physical model of the SBT memristor is established based on its working mechanism. Due to the difficulty in determining the accurate parameters of the voltage-controlled physical model, a flux-controlled mathematical model of the SBT memristor is proposed, and its equivalence relation with the voltage-controlled physical model is proved. Moreover, the parameters of the flux-controlled mathematical model are determined by means of the quadratic polynomial interpolation method using the experimentally measured voltage and current data of the SBT memristor. The simulated - characteristic curve using the flux-controlled mathematical model coincides well with the measured - characteristic curves. The result indicates that the flux-controlled mathematical model with the definite parameters can be used to characterize the behaviors of the physical SBT memristor and guide its application to nonlinear circuit design. [ABSTRACT FROM AUTHOR]

In recent years, memristor has become one of the research focuses. Considerable open literature has shown that many devices and systems possess memristive properties. Thus, research into supplying power source to these special devices and making them work steadily has been a meaningful study. This paper investigates the slow-scale instability whose oscillating frequency is between the line frequency and the switch frequency that occurs in a voltage controlled H-bridge inverter with memristive load. The mechanism of this medium-frequency oscillation is identified via harmonic balance method and Floquet theory. The results show that it is due to the occurrence of Hopf bifurcation. Finally, experimental results are presented to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

Self-excited induction generators (SEIG) are found to be most suitable candidate for wind energy conversion application required at remote windy locations. The major drawbacks of these generators are the poor voltage and frequency control under load and prime mover speed perturbations. In this paper, an attempt has been made to optimize the control strategy under various load and prime mover conditions, of the self-excited wound rotor induction generator (SEWRIG). By tolerating a slight deviation of the output voltage and ensuring a constant frequency with an adequate external rotor resistance, only four values of excitation capacitor are required for the whole range of operation. The effectiveness of the adopted strategy has been confirmed by comparing on a 0.8-kW wound rotor induction generator the simulated results to the corresponding obtained with an experimental test. A close agreement between the computed and experimental results confirms the efficiency of the adopted method. [ABSTRACT FROM AUTHOR]

This paper presents a high-voltage control and readout interface circuit implemented for capacitive Micro-Electro-Mechanic System (MEMS) gyroscope. A charge sensitive amplifier (CSA) with chopper technique is used to accomplish low-noise capacitive sensing. The stabilization of the closed drive loop is maintained by an auto gain controller (AGC) and an adjustable phase shifter. The outputs of the ASIC directly drive the gyroscope after buffered by an on-chip high-voltage level shifter. The chip is fabricated in a 0.35 um 5V/12V Bipolar, CMOS and DMOS (BCD) process. The test of the chip is performed with a MEMS vibratory gyroscope. The result shows that the Application Specific Integrated Circuit (ASIC) can ensure a stable oscillation in the drive axis, and the noise floor is 0.0015°/s/♦Hz within 100Hz. [ABSTRACT FROM AUTHOR]

A new high figure-of-merit (FOM) and low-phase-noise 20.73-GHz voltage-controlled oscillator is designed for K-band applications in this paper. The capacitive feedback technique is used for the low-phase-noise VCO design. The VCO can be tuned from 20.817 GHz to 20.266 GHz. The measured phase noise is -115.57 dBc/Hz at 1 MHz offset from the carrier frequency. The corresponding FOM is calculated to be -190 dBc/Hz. The VCO is implemented with the TSMC 0.18 μm one-poly-six-metal 1.7 V mixed-signal/RF CMOS technology, and the chip size is 0.51 × 0.74 mm2. [ABSTRACT FROM AUTHOR]