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In this paper, a nonisolated two-channel light-emitting diode (LED) driver with automatic current balance and zero-voltage switching (ZVS) is presented. In this LED driver, a dc-blocking capacitor is connected with one side of the coupled inductor. Therefore, based on the ampere–second balance, a current source is generated with the average value of the positive current identical to the absolute average value of the negative current. Accordingly, the LED currents can be balanced naturally without extra active components or current sharing transformer. Consequently, the circuit components can keep at a low count. In addition, the proposed LED driver can achieve ZVS turn-on. Thus, the switching loss can be decreased. Above all, the proposed two-channel LED driver can be extended to a multichannel LED driver. In this paper, detailed theoretical analyses and experimental results are provided to verify the feasibility and effectiveness of the proposed LED driver. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) are being developed for the grid connection of offshore wind or tidal farms. In order to reduce the construction and maintenance costs, it is desirable to reduce the weight and volume of the system. In current MMC submodule designs, the reservoir capacitor usually accounts for over 50% of the total volume and 80% of weight. This paper presents a new design concept and control principle for a submodule using the stacked switched capacitor (SSC) architecture that can significantly reduce the capacitor size in an MMC. Practical considerations for a high-voltage high-power SSC-based MMC submodule are presented in this paper, through the design of a 21-level, 40-kV (pole-pole dc), 19.1-MW, grid-connected system, and the concept is demonstrated experimenttally on a scaled-down 400-V, 12.3-Apeak laboratory prototype submodule. It is shown that with the proposed SSC architecture, the total volume of capacitors in each submodule can be reduced by more than 40% without significantly increasing the power loss. [ABSTRACT FROM AUTHOR]

Superconducting inductive pulsed power supplies have attracted a lot of attention due to its lower electrical loss and higher energy storage density than traditional inductors. To effectively improve charging rate and output continuous current pulses, a repetitive inductive pulsed power supply circuit topology based on high-temperature superconducting (HTS) pulsed power transformer was proposed and simulated in our previous studies. This paper aims to further study the feasibility of the repetitive inductive pulsed power supply circuit topology through experiments. A small air-core HTS pulsed power transformer and a bridge-type capacitor switching circuit were used to build the experimental platform. The experimental results show that the bridge-type capacitor switching circuit can shorten the charging time of each new cycle and the repetitive inductive pulsed power supply circuit is feasible for continuous current pulse output. [ABSTRACT FROM AUTHOR]

The four-switch three-phase (FSTP) inverter has been proposed as an innovative inverter design to reduce the cost, complexity, size, and switching losses of the dc–ac conversion system. Traditional FSTP inverter usually operates at half the dc input voltage; hence, the output line voltage cannot exceed this value. This paper proposes a novel design for the FSTP inverter based on the topology of the single-ended primary-inductance converter (SEPIC). The proposed topology provides pure sinusoidal output voltages with no need for output filter. Compared to traditional FSTP inverter, the proposed FSTP SEPIC inverter improves the voltage utilization factor of the input dc supply, where the proposed topology provides higher output line voltage which can be extended up to the full value of the dc input voltage. The integral sliding-mode control is used with the proposed topology to optimize its dynamics and to ensure robustness of the system during different operating conditions. Derivation of the equations describing the parameters design, components ratings, and the operation of the proposed SEPIC inverter is presented in this paper. Simulation model and experimental setup are used to validate the proposed concept. Simulations and experimental results show the effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]

Soft switching pulse-width modulation (PWM) dc–dc full-bridge converter with controlled rectifier on the secondary side of the high-frequency power transformer is presented in this paper. An active secondary switch, including new nondissipative passive energy recovery turn-off snubber on the secondary side and modified PWM control algorithm, provide conditions for zero-voltage and zero-current turn-on and zero-current turn-off of IGBT transistors on the primary side of the high-frequency dc–dc converter. The simple passive energy recovery snubber ensures also zero-voltage turn-off of the transistor on the secondary side of the power transformer. The principle of operation is explained and analyzed and consequently verified on a 2 kW, 50 kHz laboratory model of the converter. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a new capacitor degradation evaluation method aimed at failure prediction and suitable for digitally controlled switching mode power supply (SMPS) for servers. Electrolytic capacitors have one of the highest component failure rates in SMPS; therefore, we attempt to detect an equivalent series resistance degradation of the electrolytic capacitor directly from the data fetched to a digital controller of the SMPS. With a SPICE simulation and a rapid control prototyping evaluation, we confirm the degradation can be detected by the data at a transient response under a normal operation without additional circuits. Even only 10% of a load step change, which commonly occurs in SMPS for servers, causes detectable transient response degradation. [ABSTRACT FROM PUBLISHER]

This paper investigates the use of multilevel conversion in dc–dc applications that require a large voltage conversion ratio. A quantitative method that can serve as a guide to compare and design multilevel topologies for large conversion ratio applications is presented. The proposed method keeps the conduction loss and switching loss constant across the different converters and employs the passive component volume as the single performance metric. As examples, flying capacitor multilevel converters and hybrid switched-capacitor (SC) converters are compared to conventional two-level buck converters, and are shown analytically to have significantly reduced passive component size. Three converter prototypes are implemented, based on the presented methodology to experimentally validate the method as well as demonstrate the advantages of multilevel and hybrid SC converters. [ABSTRACT FROM PUBLISHER]

An isolated converter such as SEPIC has high voltage stress on the main switch due to transformer leakage inductance. To solve this issue, active or passive clamp action is necessary. The common passive solution based on an RCD snubber is simple but impractical when the value of the leakage inductance is significant. On the other hand, passive regenerative solutions generally compromise the isolation, making the search for a suitable snubber a challenge. In this paper, an effective passive regenerative snubber cell for isolated SEPIC converters operating in DCM or CCM is presented. It is intended to improve the converter efficiency by transferring the energy stored in the transformer leakage inductance to the output. The analysis is presented in detail for DCM and extended to CCM together with a practical design procedure. In order to compare with the RCD, the analysis and design of a conventional cell are presented as well. To validate the proposal and quantify its feasibility, experimental results are performed for both dissipative and regenerative snubbers on a 100 W, 100 V, input and 50 V output voltage converter operating first in DCM and later in CCM. [ABSTRACT FROM PUBLISHER]

This paper presents an analytical and experimental comparison of a two-phase buck converter and a two-phase, series capacitor buck converter. The limitations of a conventional buck converter in high-current (10 A or more), and high-frequency (HF, 3–30 MHz) point-of-load voltage regulators with large voltage conversion ratios (10-to-1) are highlighted. The series capacitor buck converter exhibits desirable characteristics at HF, including lower switching loss, less inductor current ripple, automatic phase current balancing, duty ratio extension, and soft charging of the energy transfer capacitor. Analysis of the topologies indicates that switching loss and inductor core loss can dominate at HF. Results from side-by-side 12 V input, 1.2 V output hardware prototypes demonstrate that the series capacitor buck converter has up to 12 percentage points higher efficiency at 3 MHz and reduces power loss by up to 33% at full load (10 A). Some guidelines for inductor selection are provided, and a switch stress comparison reveals that the maximum converter switch stress is reduced by 30%. [ABSTRACT FROM AUTHOR]

Multilevel converters are mainly used in medium-voltage high-power applications. Active neutral-point-clamped (ANPC) flying capacitor multicell (FCM) converter is a well-known type of multilevel converters which is commercially available in high-power medium-voltage motor drive market. Since power loss investigation can be very advantageous in the design phase of multilevel converters, this paper presents an analytical approach to calculate and investigate the conduction and switching power loss in ANPC-FCM converter. First, the RMS and average currents of insulated-gate bipolar transistors (IGBTs) and antiparallel diodes are analytically calculated by considering the associated duty cycle of each IGBT and diode, converter modulation index, load current, and load power factor. Numerical results of the derived closed-form equations to calculate the RMS and average currents of IGBTs/diodes are compared with simulation results and experimental measurements. Numerical results match the simulation results and experimental measurements which validates the derived closed-form equations. Afterward, the obtained equations for RMS and average current computations are utilized to calculate the conduction power losses in a 12.1-MVA 6.6-kV nine-level (line-to-line) ANPC-FCM multilevel converter. For this purpose, a 4.5-kV 1.2-kA IGBT module from ABB is considered as a power switch and its parameters are employed in analytical computations and simulation of the ANPC-FCM multilevel converter for conduction power loss determination. Moreover, closed-form equations are derived for analytical determination of switching power losses for ANPC-FCM converter using Kapteyn (Fourier-Bessel) series. Based on the derived closed-form equations for conduction loss and switching loss calculation, a method is presented to determine the junction temperature in IGBTs and diodes for ANPC-FCM converter. [ABSTRACT FROM AUTHOR]

High-performance buck converters are often required in modern power electronic applications. An augmented buck converter (a main buck converter with augmentation circuits) can achieve fast transient recovery and small output voltage deviation. Compared with other augmentation circuits, a resonant augmentation circuit offers potential electromagnetic interference reduction due to the relatively low $di/dt$ value and compacts the circuit through a reduced inductance for resonance. In this paper, the performance analysis of an augmented buck converter constructed with the resonant circuit are described in detail in terms of voltage-deviation band and power loss. A circuit design and control principle is also proposed for achieving the required voltage deviation for a given transient-detection delay. A 12-to-5-V converter prototype is built to verify the analysis and effectiveness of the proposed methodology. It is demonstrated that the voltage deviation is reduced from 360 to 200 mV using the proposed resonant augmentation circuits and control scheme. The efficiency study shows that the power loss varies from 0.02 to 0.72 W, when the repetition frequency of 5-to-10-A transients changes from 100 to 5 kHz. [ABSTRACT FROM AUTHOR]

A family of modulation schemes based on mathematical construction for the multimodular matrix converter (MC) with ordinary multiwindings transformer is proposed in this paper. The key to the schemes are the calculation of offset signals. A geometric method is introduced to determine the range of the offset signals. The modulation schemes could be divided in two categories based on the geometric positions of the offset signals: continuous modulation (Method I) and discontinuous modulation (Method II). The former has the advantages of ease of use and good power quality. While the later has the advantage in power losses. Additionally, both methods can achieve the maximum linear voltage transfer ratio. To obtain better output current quality, a switching pattern with specific sequence is provided. Finally, a scaled-down prototype is built to verify the correctness and effectiveness of the proposed modulation strategies. [ABSTRACT FROM AUTHOR]

In this paper, a new discontinuous modulation technique is presented for the operation of the modular multilevel converter (MMC). The modulation technique is based on adding a zero sequence to the original modulation signals so that the MMC arms are clamped to the upper or lower terminals of the dc-link bus. The clamping intervals are controlled according to the absolute value of the output current to minimize the switching losses of the MMC. A significant reduction in the capacitor voltage ripples is achieved, especially when operating with low modulation indices. Furthermore, a circulating current control strategy suitable for this modulation technique is also proposed. Simulation and experimental results under various operating points are reported along with evaluation and comparison results against a conventional carrier-based pulse width modulation method. [ABSTRACT FROM AUTHOR]

This paper proposes a voltage balancing method for stacked multicell converters (SMCs) based on phase-disposition pulse-width modulation (PD-PWM). In order to reduce the switching transitions of the power devices, only optimal transitions between consecutive voltage levels are used. Selection of the optimal transition sequence is performed by evaluating a cost function. Significant reductions in the switching transitions and power losses of the power devices are achieved as compared to the optimal-state voltage balancing method where nonoptimal transitions are allowed. Simulation and experimental results from a seven-level $3\times 2$ SMC verifies that the proposed PD-PWM voltage balancing method is robust under linear/nonlinear loads and transients. [ABSTRACT FROM AUTHOR]

An ideal switch with hysteresis-free \(S_{\rm ideal}=0~{\rm mV/decade}\) switching is desired to keep Moore’s law alive, but has never been achieved. Classical field-effect transistors (FETs) have supported Moore’s law for 50 years, albeit with a thermodynamically limited value of subthreshold swing \(S\ge 60\) mV/decade. Alternatives, such as, tunnel FETs, impact ionization FETs, and negative capacitance FETs promise \(S <60\) mV/decade, but ideal switching is not expected, even in theory. In this paper, we propose a zero subthreshold swing FET (ZSubFET), which is similar to a classical FET with a suspended-gate and a ferroelectric gate insulator. ZSubFET exhibits ideal switching through integration of two negative capacitors (namely, a ferroelectric and an air-gap) in the gate-stack, in series with the channel capacitance. We believe that the proposed device concept should not only lower the power dissipation in an IC, but also open up new research directions for the alternative of classical-FET. [ABSTRACT FROM AUTHOR]

The energy-efficiency issue of switched-capacitor converters is still a controversial topic that requires a more in-depth discussion. In this paper, we address the issue by dividing the analysis of the entire efficiency problem into two parts. In the first part, the efficiency of a capacitor-charging RC circuit under different aspects (partial charging, full charging, at zero capacitor voltage, at nonzero capacitor voltage, etc.) will be conducted. The efficiency analysis of a capacitor-discharging RC circuit with a resistor, capacitor, and paralleled resistor–capacitor loads will be covered. A complete evaluation of the overall efficiency is then performed in terms of both the charging and discharging efficiencies. Based on the analysis, some design rules useful for developing high-efficiency switched-capacitor converters is suggested. Additionally, it is shown that the belief that quasi-switched-capacitor converters are more lossy than switched-capacitor converters is a common misconception. [ABSTRACT FROM AUTHOR]

Most of modern controlled electric drive applications, such as lifts, cranes, and tooling machines, are characterized by a high ratio of the peak to average power. In addition, such applications have high demand for braking at the full rated power. In ordinary drives, the braking energy, which represents 30%–50% of the consumed energy, is dissipated on a brake resistor. Apart from this “energetic” issue, power supply interruption and the input current quality are two additional issues to be solved. A novel regenerative controlled electric drive based on an ultracapacitor as energy storage is presented in this paper. The ultracapacitor with an interface dc–dc converter is used to store and recover the braking energy. In addition, the dc–dc converter controls the rectifier current and reduces the drive input current total-harmonic-distortion factor down to 30%. Moreover, the dc bus voltage is boosted and controlled to be constant and ripple free regardless of the load and the mains voltage variation. In comparison to state-of-the-art solutions, the new solution has better performance regarding size, cost, and efficiency. The presented solution is theoretically analyzed and experimentally verified. The results are presented and discussed. [ABSTRACT FROM AUTHOR]