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As technology node scales down below 90 nm, the conventional complementary metal oxide semiconductor (CMOS) logic circuits suffer from various problems such as high standby power due to increase in leakage current. Spintronic devices based on magnetic tunnel junction (MTJ) is one of the most promising technology candidates for the future of the digital circuits. MTJ-based logic circuits can offer nonvolatility, high endurance, high density, low standby power dissipation, and 3-D integration capability with the CMOS technology. In recent years, several full-adder circuits are proposed based on MTJs that are not fully nonvolatile since they use MTJs to store only one of their inputs. This paper proposes a fully nonvolatile magnetic full-adder (MFA) circuit offering the capability of power gating with no loss of data. The proposed circuit stores all the inputs in MTJs using the spin-transfer torque (STT) method assisted by the spin-Hall effect (SHE). Thanks to the SHE assistance, delay and power consumption of the MTJ switching are reduced significantly. Moreover, as a result of lower write current, the endurance of the oxide barrier can be increased. Using a three-terminal SHE–STT–MTJ model and a 45 nm CMOS SPICE model, we simulated and validated the functionality of our design and compared it with some recent previous MFAs. Simulation results reveal that the proposed MFA offers considerable superiorities over the recent counterparts. [ABSTRACT FROM AUTHOR]

Superconducting inductive pulsed power supplies have attracted a lot of attention due to its lower electrical loss and higher energy storage density than traditional inductors. To effectively improve charging rate and output continuous current pulses, a repetitive inductive pulsed power supply circuit topology based on high-temperature superconducting (HTS) pulsed power transformer was proposed and simulated in our previous studies. This paper aims to further study the feasibility of the repetitive inductive pulsed power supply circuit topology through experiments. A small air-core HTS pulsed power transformer and a bridge-type capacitor switching circuit were used to build the experimental platform. The experimental results show that the bridge-type capacitor switching circuit can shorten the charging time of each new cycle and the repetitive inductive pulsed power supply circuit is feasible for continuous current pulse output. [ABSTRACT FROM AUTHOR]

In this paper, a new T-type inverter topology based on multistate switching cell is proposed. The topology presents five-level voltage before the output $LC$ filter, providing high-order harmonics that are easily filtered. In this topology, the output filter ripple frequency is twice the switching frequency, therefore reducing the magnetic weight and volume. Other characteristics of the inverter are current sharing through the devices, facilitating its losses' dissipation, due to increased contact area and few involved components in the current flow path. In order to verify its feasibility, a design example, as well as experimental results, for a 5-kW prototype is presented in this paper. [ABSTRACT FROM AUTHOR]

Switch-mode hydraulic control is a compact and theoretically efficient alternative to throttling valve control or variable displacement pump control. However, a significant source of energy loss in switch-mode circuits is due to throttling during valve transitions. Hydraulic soft switching was previously proposed as a method of reducing the throttling energy loss, by absorbing, in a small variable volume chamber, the flow that would normally be throttled across the transitioning high-speed valve. An active locking mechanism was previously proposed that overcomes the main challenge with soft switching, which is a lock mechanism that releases quickly and with precise timing. This prior work demonstrated a reduction in energy losses by 66% compared to a control circuit. In this paper, a numerical model is developed for a switch-mode virtually variable displacement pump (VVDP) circuit, utilizing the proposed soft switch. The model is then used as a means of designing a proof of concept prototype to validate the model. The prototype design includes methods for controlling the soft switch spring preload, travel distance, piston displacement required to unlock the soft switch, valve command duty cycle, switching cycle period, and load pressure. Testing demonstrated that the soft switch circuit performed as expected in a baseline condition. The operating region for this prototype was found to be quite narrow. However, the model does a good job of predicting the displacement of the soft switch. [ABSTRACT FROM AUTHOR]

The role of universal memory can be successfully satisfied by magnetic tunnel junctions (MTJs) where the writing mechanism is based on spin-transfer torque (STT). An improvement in the switching properties (lower switching current density maintaining the thermal stability) has been achieved in MTJs with interfacial perpendicular anisotropy (IPA) at the interface between CoFeB and MgO. In this paper, micromagnetic simulations point out the influence of IPA and saturation magnetization (M \(_{\mathbf {S}}\) ) on the properties of fast magnetization reversal achieved in 5, 10, and 20 ns. Both cases of in-plane and out-of-plane free layer are considered. In addition, the thermal effect is included for the in-plane switching at 20 ns and a complete analysis of energy dissipation during the switching is illustrated. This paper can provide useful information for the design of STT-based memories. [ABSTRACT FROM PUBLISHER]

This paper presents an analytical and experimental comparison of a two-phase buck converter and a two-phase, series capacitor buck converter. The limitations of a conventional buck converter in high-current (10 A or more), and high-frequency (HF, 3–30 MHz) point-of-load voltage regulators with large voltage conversion ratios (10-to-1) are highlighted. The series capacitor buck converter exhibits desirable characteristics at HF, including lower switching loss, less inductor current ripple, automatic phase current balancing, duty ratio extension, and soft charging of the energy transfer capacitor. Analysis of the topologies indicates that switching loss and inductor core loss can dominate at HF. Results from side-by-side 12 V input, 1.2 V output hardware prototypes demonstrate that the series capacitor buck converter has up to 12 percentage points higher efficiency at 3 MHz and reduces power loss by up to 33% at full load (10 A). Some guidelines for inductor selection are provided, and a switch stress comparison reveals that the maximum converter switch stress is reduced by 30%. [ABSTRACT FROM AUTHOR]

Multilevel converters are mainly used in medium-voltage high-power applications. Active neutral-point-clamped (ANPC) flying capacitor multicell (FCM) converter is a well-known type of multilevel converters which is commercially available in high-power medium-voltage motor drive market. Since power loss investigation can be very advantageous in the design phase of multilevel converters, this paper presents an analytical approach to calculate and investigate the conduction and switching power loss in ANPC-FCM converter. First, the RMS and average currents of insulated-gate bipolar transistors (IGBTs) and antiparallel diodes are analytically calculated by considering the associated duty cycle of each IGBT and diode, converter modulation index, load current, and load power factor. Numerical results of the derived closed-form equations to calculate the RMS and average currents of IGBTs/diodes are compared with simulation results and experimental measurements. Numerical results match the simulation results and experimental measurements which validates the derived closed-form equations. Afterward, the obtained equations for RMS and average current computations are utilized to calculate the conduction power losses in a 12.1-MVA 6.6-kV nine-level (line-to-line) ANPC-FCM multilevel converter. For this purpose, a 4.5-kV 1.2-kA IGBT module from ABB is considered as a power switch and its parameters are employed in analytical computations and simulation of the ANPC-FCM multilevel converter for conduction power loss determination. Moreover, closed-form equations are derived for analytical determination of switching power losses for ANPC-FCM converter using Kapteyn (Fourier-Bessel) series. Based on the derived closed-form equations for conduction loss and switching loss calculation, a method is presented to determine the junction temperature in IGBTs and diodes for ANPC-FCM converter. [ABSTRACT FROM AUTHOR]

With the rapid growth of battery-powered portable electronics, an efficient power management solution is necessary for extending battery life. Generally, basic switching regulators, such as buck and boost converters, may not be capable of using the entire battery output voltage range (e.g., 2.5–4.7 V for Li-ion batteries) to provide a fixed output voltage (e.g., 3.3 V). In this paper, an average-current-mode noninverting buck–boost dc–dc converter is proposed. It is not only able to use the full output voltage range of a Li-ion battery, but it also features high power efficiency and excellent noise immunity. The die area of this chip is 2.14 × 1.92mm^2, fabricated by using TSMC 0.35 μm 2P4M 3.3 V/5 V mixed-signal polycide process. The input voltage of the converter may range from 2.3 to 5 V with its output voltage set to 3.3 V, and its switching frequency is 500 kHz. Moreover, it can provide up to 400-mA load current, and the maximal measured efficiency is 92.01%. [ABSTRACT FROM PUBLISHER]

The power dissipation during the application of scan-based tests can be significantly higher than during functional operation. An exception is the second, fast functional capture cycles of functional broadside tests, where it is guaranteed that the power dissipation will not exceed that possible during functional operation. The power dissipation during the other clock cycles of functional broadside tests is studied here for the first time. The clock cycles under consideration are referred to as scan shift cycles. This paper describes a test generation procedure that limits the power dissipation during scan shift cycles of functional broadside tests. Experimental results for benchmark circuits demonstrate the extent to which the power dissipation during scan shift cycles can be limited without affecting the transition fault coverage. [ABSTRACT FROM PUBLISHER]