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The emergence of applications which require high-voltage switches has created a tendency to use semiconductor device series stacks. These series stacks permit operation at blocking voltages above semiconductor elements’ nominal voltage. Insulated-gate bipolar transistors (IGBT) are currently utilized for controllability and switching speed, when these topologies are employed. The main challenge therewith is guaranteeing voltage balance between IGBTs, both when blocked and when switching transistors. Most of the methods which have been proposed to mitigate static and dynamic voltage unbalances increase transistor losses. The series stack loss-less high voltage switch (LHVS) which mitigates voltage unbalances, thus reducing switching losses, is presented in this paper. LHVS consists of a circuit, which ensures soft IGBT switching, an energy recovery circuit, and a gate delay compensation circuit. Additionally, the insulation voltage level is guaranteed to be equal between control circuit and high-voltage side of each IGBT. The operating principle of the LHVS is detailed in this paper, as is experimental validation which has been performed for three series stack modules. Static unbalances are reduced to 1%, while the differences between collector–emitter voltage curves in switching “on” do not surpass 8 ns, and switching losses are reduced by 41%, as compared to the hard-switching topology. [ABSTRACT FROM AUTHOR]

This paper presents a unified framework for the modeling, analysis, and design of load-independent Class E and Class EF inverters and rectifiers. These circuits are able to maintain zero-voltage switching and, hence, high efficiency for a wide load range without requiring tuning or use of a feedback loop, and to simultaneously achieve a constant amplitude ac voltage or current in inversion and a constant dc output voltage or current in rectification. As switching frequencies are gradually stepping into the megahertz (MHz) region with the use of wide-bandgap (WBG) devices such as GaN and SiC, switching loss, implementing fast control loops, and current sensing become a challenge, which load-independent operation is able to address, thus allowing exploitation of the high-frequency capability of WBG devices. The traditional Class E and EF topologies are first presented, and the conditions for load-independent operation are derived mathematically; then, a thorough analytical characterization of the circuit performance is carried out in terms of voltage and current stresses and the power-output capability. From this, design contours and tables are presented to enable the rapid implementation of these converters given particular power and load requirements. Three different design examples are used to showcase the capability of these converters in typical MHz power conversion applications using the design equations and methods presented in this paper. The design examples are chosen toward enabling efficient and high-power-density MHz converters for wireless power transfer (WPT) applications and dc/dc conversion. Specifically, a 150-W 13.56-MHz Class EF inverter for WPT, a 150-W 10-MHz miniature Class E boost converter, and a lightweight wirelessly powered drone using a 20-W 13.56-MHz Class E synchronous rectifier have been designed and are presented here. [ABSTRACT FROM AUTHOR]

In applications that demand single-input dual-output (SIDO) or dual-input single-output (DISO) dc–dc converters, employing two separate single-input single-output (SISO) converters is a solution. However, the number of components is doubled, resulting in high overall cost. In order to reduce costs, this paper proposes a novel topology synthesis methodology, with which a variety of SIDO and DISO dc–dc converters with reduced components can be derived. The principle of topology synthesis states that integrated SIDO and DISO dc–dc converters can be easily developed from conventional SISO converters by replacing a diode with a basic cell inclusive of additional input/output port. The principle is effective for many SISO dc–dc converters, and as an example, topology synthesis based on buck, boost, buck–boost, Cuk, sepic, and zeta SISO converters is performed in this paper. In order to achieve better understanding of the proposed converters, the integrated SIDO Cuk converter is specifically analyzed and experimentally verified. In comparison with the conventional scheme of two separate SISO Cuk converters, good cross regulation is retained while the number of diodes, inductors, and capacitors is reduced in the proposed SIDO Cuk converter. In addition, zero-voltage-switching operation of one switch is achieved, contributing to lower switching losses. Finally, a prototype circuit with 48-V input and 156 V/1 A, 24 V/4 A outputs is built to validate the theoretical analysis. [ABSTRACT FROM PUBLISHER]

In this paper, direct torque control (DTC) of five-phase induction motor (FPIM) is implemented using three-level neutral point clamped (TL-NPC) inverter. One of the advantages of three-level inverter over two-level one for DTC operation is the low torque ripple. Also TL-NPC inverter through space vector modulation technique gives low $ dv/dt$ transition with better voltage waveform. By applying conventional lookup table for DTC, the TL-NPC inverter does not ensures lower $dv/dt$ transition. In this paper, a novel switching scheme for DTC of FPIM using TL-NPC inverter is proposed that ensures the low $ dv/dt$ transition and balancing of dc-link capacitor voltages of TL-NPC inverter. To form the lookup table for DTC operation, instead of using voltage vectors directly, virtual vectors (VVs) are utilized. Two switching states are used in one sample time to generate a VV in $\alpha \beta$ plane, which gives zero resultant voltage in $ xy$ plane. The switching strategy ensures low number of transitions to reduce the switching losses. The switching state redundancies are used in a novel way to balance the dc-link capacitor voltages without using any additional hardware. The proposed technique to balance the dc-link capacitor voltage gives lower switching frequency. The MATLAB/Simulink environment is used for the simulation and the results are validated through experiments. [ABSTRACT FROM AUTHOR]

This paper introduces a novel five-level nested neutral point piloted (NNPP) converter and analyzes the operating principle of five-level NNPP converter. This paper presents a novel space vector pulse width modulation (SVPWM) algorithm based on gh coordinate for five-level NNPP converter. First, the common-mode voltage is reduced by choosing the appropriate redundant switching states. After that, the floating-capacitor voltage balance control strategy is presented. The appropriate switch combinations of each phase are determined by the control requirements of floating-capacitor voltages respectively and the hardware mapping method of the switching states is presented. Furthermore, the neutral-point voltage balance control strategy is presented. In order to balance the dc-link capacitor voltages, the seven-segment switching sequence is selected according to the control requirements of dc-link capacitor voltages and the neutral-point voltage regulatory factor is introduced to regulate the durations of the redundant switching states in a switching cycle. Finally, the validity of the novel SVPWM algorithm with decoupling control strategies of floating-capacitor voltages and dc-link capacitor voltages is verified by the experimental results of five-level NNPP converter under steady-state and dynamic conditions. [ABSTRACT FROM AUTHOR]

In this paper, a fixed switching frequency model predictive current controller is designed and implemented on a sensorless five-level packed U-cell (PUC5) inverter interfacing the utility. The predictive control methodology is based on a voltage vector generation technique for the cost function optimization by nullifying its derivative. The aim of the controller is to allow a fixed-frequency operation with no iterations while operating as a utility line current regulator. A pulsewidth modulator based on employing PUC5 redundant switching states fixes the PUC5 auxiliary dc bus capacitor voltage to its desired level with no necessity of a regulator; the overall technique reduces system complexity with less sensors and no loops in the predictive algorithm making it suitable for industrial applications. System discrete model is developed and experimental results verify the performance of the designed controller in making a fast response in regulating the grid current and balancing the capacitor voltage. [ABSTRACT FROM AUTHOR]

A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]

Cascaded H-bridge (CHB) multilevel inverters (MLIs) have been widely used for power electronics systems. While high-voltage blocking across power switches is not a constraint for low voltage applications, the research trend has been oriented to the design of more compact module topologies as an alternative for CHB. Despite the generation of more voltage levels with reduced switch count, the existing module topologies in recent literature take no account of the freewheeling current path during dead-time, thus, inducing multistep jumps in voltage levels and giving rise to undesirable voltage spikes. Addressing this concern, this paper proposes two symmetrical compact-module topologies for cascaded MLI, where freewheeling current path during dead-time is provided for smooth transition between voltage levels to prevent voltage spikes. The proposed 7-level and 13-level compact-modules demonstrated low number of conducting switches for all voltage levels. Comprehensive analysis and comparison with the latest module topologies are conducted. To validate the operation of the proposed compact-module topologies, simulation and experimental results are presented. [ABSTRACT FROM PUBLISHER]

This paper presents a solution for the voltage balance problem of the series-connected devices that can be applied to multilevel converters in which the series-connected devices need to block twice their switched voltage. The solution is based on two ideas, the control of the switching commands to achieve proper switching losses balance and the use of additional circuitry to achieve proper voltage balance during their blocking state. The proposed strategy is experimentally validated into a 5-level multipoint clamped full-scale converter. However, it can be used in any other converter topology in which the devices need to block twice their switched voltage. [ABSTRACT FROM PUBLISHER]

In this paper, a new fault tolerant dc–ac converter-fed induction motor drive is proposed to maintain motor as close as possible to its desired normal operation under open- and short-circuit switch failures. The operational principles for fault detection and isolation schemes are provided. Two control strategies including predictive control and voltage mode-controlled PWM with integral-double-lead controller for two stage of the converter are presented in conjunction with the elaborated discussion. The control strategy determines appropriate switching states for continuous operation of the drive after a fault. The proposed topology makes it possible to integrate the minimal redundant hardware and full tolerance capability which is an important advantage of the proposed topology. Moreover, the most important advantages of the proposed topology are a fast response in a fault condition and low cost of the converter in comparison with the evaluated topologies. A Joule-integral-based method for selecting an appropriate rating of applied fuses has been presented to provide a reliable fault-isolation operation. Also, a comparison with currently available fault-tolerant dc–ac converters is given to show the merits of the proposed topology. Finally, the experimental results are presented to verify the validity of the theoretical analysis and industrial feasibility of the proposed converter. [ABSTRACT FROM AUTHOR]

To prevent partial-shading issues in photovoltaic (PV) systems, various kinds of voltage equalizers that virtually unify characteristics of shaded and unshaded modules have been proposed. Although PV string utilization can be dramatically improved, PV systems tend to be complex and costly because, in addition to the main converter for string control, voltage equalizers are separately necessary. This paper proposes the single-switch single-magnetic pulse width modulation (PWM) converter integrating the voltage equalizer using the series-resonant voltage multiplier (SRVM) for standalone PV systems. By utilizing a square wave voltage generated across a filter inductor in a PWM buck converter for driving the SRVM, the main PWM converter and voltage equalizer can be integrated into a single unit with reducing the total switch and magnetic component counts, achieving not only system-level but also circuit-level simplifications. The experimental test using the prototype for three PV modules connected in series was performed emulating a partial-shading condition. The integrated converter effectively precluded the partial-shading issues and significantly improved the power available at a load, demonstrating its efficacy. [ABSTRACT FROM AUTHOR]

The traditional finite-control-set model predictive control (FCS-MPC) method for a cascaded H-bridge (CHB) rectifier has two main issues: heavy computational burden and low steady-state current performance. In this paper, a novel FCS-MPC method has been proposed for a single-phase CHB rectifier. The proposed method solves the optimization problem of FCS-MPC for one cell by one cell, like a “pipeline.” In the proposed method, the sampling period is divided into equal intervals by the number of cells. At the beginning of the first interval, the first cell selects its switching state to be applied. Then, the following cell selects its switching state to be applied at the beginning of next interval. Finally, the selected switching state of last cell will be applied at the beginning of the last interval. A cost function presenting the control objectives of common source current error and itself dc-link voltage error is evaluated for each cell. A single-phase three-cell CHB rectifier controlled by a DSpace DS1104 is tested and the experimental results show that a significant reduction in computational time, an improved steady-state current performance, and a comparable dynamic response are achieved in the proposed method in comparison with the traditional FCS-MPC method. [ABSTRACT FROM AUTHOR]

The paper presents a new bridgeless power factor correction (PFC) topology, using a recently proposed controllable LCL filter, namely active virtual ground to achieve efficient power conversion, and high-frequency common mode voltage (CM) reduction. The proposed PFC circuit consists of high-frequency semiconductors for shaping inductor current and low-frequency semiconductors to form two different LCL structures for different conditions. This reduces grid differential mode current ripple or inductance. Besides, the PFC CM voltage, a main problem of bridgeless PFCs, is significantly reduced, since the capacitor in the LCL filter clamps the voltage between the grid and the converter ground. The performance of the proposed PFC is experimentally verified. The results show that the proposed PFC guarantees sinusoidal input current, low high-frequency common-mode voltage noise, and has a good agreement with the theoretical findings. [ABSTRACT FROM AUTHOR]

This paper presents a novel soft-switching galvanically isolated buck-boost dc–dc converter as a module-integrated converter for photovoltaic (PV) applications. It features three major operating modes: boost, normal, and buck mode. Their proper distribution over the input voltage range enables wide voltage regulation capabilities, i.e., close to those of nonisolated power optimizers. The proposed control algorithm requires only one buck-boost switching stage that performs voltage regulation by means of the switching stage reconfiguration with smooth transition between the modes. The design guidelines and the digital control system for PV applications are provided. The module-integrated converter was verified experimentally with a solar array simulator. The converter showed good maximum power point tracking performance and a peak efficiency of nearly 97%. [ABSTRACT FROM PUBLISHER]

This paper presents a new multicell topology based on flying capacitor (FC) structure suitable for multilevel converters. The proposed topology employs the concept of phase-shifted carrier pulse width modulation (PWM) with modified modulating signals to generate appropriate PWM signals. The modulation strategy along with all possible switching states are explained. The implementation of the proposed PWM technique is shown by the help of illustrating waveforms. To show the advantages of the proposed structure, different performance criteria are compared with other FC multicell (FCM) structures. Simulation results are used to further evaluate the potential merits of the proposed topology. It is shown that the proposed structure is superior to other FCM-based structures from different standpoints. Specifically, it reduces the number of high-frequency switches, the number of FCs, and at the same time improves the quality of output voltage. A laboratory-type experimental setup is used to validate the modulation strategy and other theoretical findings. [ABSTRACT FROM AUTHOR]

This paper presents an analytical and experimental comparison of a two-phase buck converter and a two-phase, series capacitor buck converter. The limitations of a conventional buck converter in high-current (10 A or more), and high-frequency (HF, 3–30 MHz) point-of-load voltage regulators with large voltage conversion ratios (10-to-1) are highlighted. The series capacitor buck converter exhibits desirable characteristics at HF, including lower switching loss, less inductor current ripple, automatic phase current balancing, duty ratio extension, and soft charging of the energy transfer capacitor. Analysis of the topologies indicates that switching loss and inductor core loss can dominate at HF. Results from side-by-side 12 V input, 1.2 V output hardware prototypes demonstrate that the series capacitor buck converter has up to 12 percentage points higher efficiency at 3 MHz and reduces power loss by up to 33% at full load (10 A). Some guidelines for inductor selection are provided, and a switch stress comparison reveals that the maximum converter switch stress is reduced by 30%. [ABSTRACT FROM AUTHOR]

In this paper, a new cascaded nonlinear controller has been designed and implemented on the packed U-cell (PUC) seven-level inverter. The proposed controller has been designed based on a simplified model of PUC inverter and consists of a voltage controller as an outer loop and a current controller as an inner loop. The outer loop regulates the PUC inverter capacitor voltage as the second dc bus. The inner loop is in charge of controlling the flowing current, which is also used to charge and discharge that capacitor. The main goal of the whole system is to keep the dc capacitor voltage at a certain level results in generating a smooth and quasi-sine-wave seven-level voltage waveform at the output of the inverter with low switching frequency. The proposed controller performance is verified through experimental tests. Practical results prove the good dynamic performance of the controller in fixing the PUC capacitor voltage for various and variable load conditions and yet generating low-harmonic seven-level voltage waveform to deliver power to the loads. Operation as an uninterruptible power supply (UPS) or ac loads interface for photovoltaic energy conversion applications is targeted. [ABSTRACT FROM AUTHOR]

A systematic method for deriving soft-switching three-port converters (TPCs), which can interface multiple energy, is proposed in this paper. Novel full-bridge (FB) TPCs featuring single-stage power conversion, reduced conduction loss, and low-voltage stress are derived. Two nonisolated bidirectional power ports and one isolated unidirectional load port are provided by integrating an interleaved bidirectional Buck/Boost converter and a bridgeless Boost rectifier via a high-frequency transformer. The switching bridges on the primary side are shared; hence, the number of active switches is reduced. Primary-side pulse width modulation and secondary-side phase shift control strategy are employed to provide two control freedoms. Voltage and power regulations over two of the three power ports are achieved. Furthermore, the current/voltage ripples on the primary-side power ports are reduced due to the interleaving operation. Zero-voltage switching and zero-current switching are realized for the active switches and diodes, respectively. A typical FB-TPC with voltage-doubler rectifier developed by the proposed method is analyzed in detail. Operation principles, control strategy, and characteristics of the FB-TPC are presented. Experiments have been carried out to demonstrate the feasibility and effectiveness of the proposed topology derivation method. [ABSTRACT FROM AUTHOR]

A capacitor voltage-balancing method for a nested neutral point clamped (NNPC) inverter is proposed in this paper. The NNPC inverter is a newly developed four-level voltage-source inverter for medium-voltage applications with properties such as operating over a wide range of voltages (2.4–7.2 kV) without the need for connecting power semiconductor in series and high-quality output voltage. The NNPC topology has two flying capacitors in each leg. In order to ensure that the inverter can operate normally and all switching devices share identical voltage stress, the voltage across each capacitor should be controlled and maintained at one-third of dc bus voltage. The proposed capacitor voltage-balancing method takes advantage of redundancy in phase switching states to control and balance flying capacitor voltages. Simple and effective logic tables are developed for the balancing control. The proposed method is easy to implement and needs very few computations. Moreover, the method is suitable for and easy to integrate with different pulse width modulation schemes. The effectiveness and feasibility of the proposed method is verified by simulation and experiment. [ABSTRACT FROM PUBLISHER]

This paper presents a single-phase transformerless grid-connected photovoltaic converter based on two cascaded full bridges with different dc-link voltages. The converter can synthesize up to nine voltage levels with a single dc bus, since one of the full bridges is supplied by a flying capacitor. The multilevel output reduces harmonic distortion and electromagnetic interference. A suitable switching strategy is employed to regulate the flying-capacitor voltage, improve the efficiency (most devices switch at the grid frequency), and minimize the common-mode leakage current with the help of a novel dedicated circuit (transient circuit). Simulations and experiments confirm the feasibility and good performance of the proposed converter. [ABSTRACT FROM PUBLISHER]

Hybrid cascade multilevel inverters combine semiconductor devices of different voltage ratings and technologies, which theoretically allow high efficiency to be achieved. The bottlenecks of these topologies are, however, the need for isolated supplies for the cells and the lack of modularity. This paper focuses on the design and control of high-resolution, high-efficiency multilevel inverters with simplified dc power supplies. It introduces several rules for systematically designing the dc voltages of the cells, for which all unsupplied capacitor voltages can be regulated. Six classes of inverters are obtained covering single- and three-phase, staircase and pulsewidth-modulated (PWM) inverters. New configurations of hybrid cascade multilevel inverters are obtained for each class. A double modulation strategy with two different frequencies is proposed that allows switching losses of PWM inverters to be reduced. Decoupled mechanisms are proposed for the total and internal energy balances. It is shown how to make the design robust by taking into account conversion losses and large dc-voltage imbalances in the design and control. An analysis of the maximum voltage utilization and efficiency of the resulting configurations is carried out. The effectiveness of the novel concepts is validated experimentally for two of the proposed topologies. [ABSTRACT FROM PUBLISHER]

AC test power sources are essential for testing electric equipment that is ac-mains connected. Typically, linear power amplifiers (LPAs) are mainly employed as ac test sources because of their high fidelity and excellent dynamic behavior. However, these LPAs have very high losses in their output stages, which make the systems bulky and expensive due to the large heatsinks that are required. In recent years, two approaches have attracted popular interest to improve the efficiency of ac power sources. These are hybrid operation, i.e., combination of linear and switch mode, and multilevel switch-mode inverters. In this paper, three types of multilevel power amplifiers, based on hybrid or switching technology, are presented, namely: hybrid multicell amplifier (H-MCA), amplitude-modulated (AM) + pulsewidth-modulated (PWM) MCA (AP-MCA), and PWM MCA (P-MCA). For each of these topologies, the operating principle and control scheme are introduced. Finally, a 1-kVA laboratory prototype, which can realize all the three topologies, is built, and the measured performance based on this universal prototype are compared. [ABSTRACT FROM PUBLISHER]