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Thanks to the favorable advantage of low cost, integrated three-port dc–dc converters with reduced switches have attracted extensive attention. In order to provide more new topologies, this paper aims to propose a programmable topology derivation method, which effectively simplifies the cumbersome process of the conventional combination method. Instead of the manual connection and examination, the proposed alternative can quickly and rigorously derive multiple viable integrated three-port dc–dc topologies from a great number of possible connections with the aid of computer program. Besides, generalized analysis is also accomplished, with which performance characteristics of all derived converters are simultaneously obtained and then a comprehensive comparison can be easily conducted to select a preferred one for the practical application. Finally, an example-specific application with one input and two outputs is given, with topology selection, design, and experimental results demonstrated in detail. [ABSTRACT FROM AUTHOR]

This paper extends the voltage-doubler concept to the single-phase SEPIC rectifier in discontinuous conduction mode and, as a consequence, novel rectifiers are proposed. A comparison with the classic SEPIC rectifier shows that the proposed converters can either provide reduced voltage stress on the semiconductors for the same output voltage level or supply double the gain of the output voltage with the same voltage stress. The proposed voltage-doubler SEPIC rectifiers provide a high power factor with no current control and they can be applied in order to improve the static gain of the structure, which can make the SEPIC rectifier suitable for applications that require a high voltage level. In this paper, the generic structure based on a three-state switch, four different implementations of the proposed concept (including bridgeless structures), steady-state analysis, a dynamic model, system control, and experimental results are presented. The proposed rectifiers were verified by experimental results obtained with a prototype built with the following specifications: 1000 W output power, 220 V input voltage, 400 V output voltage, and 50 kHz switching frequency. Peak efficiency of 95.84%, THD of 2%, and power factor of 0.9997 were obtained and, most importantly, double the gain of the output voltage was verified. [ABSTRACT FROM AUTHOR]

In this paper, a high-voltage unipolar pulse power generator is introduced for electroporation applications. Operating principle of the proposed structure is based on the buck–boost (BB) converter. The generator is comprised of parallel modules connected to the converter through an SCR and is supplied by a low-voltage dc source. Each module consists of an insulated gate bipolar transistor (IGBT), two diodes, and a capacitor. In fact, the proposed topology is a combination of the Marx generator and BB (MG-BB) converter. In comparison with other modular MG-BB structures, the proposed topology achieves interesting advantages including simpler structure, reduction of IGBTs voltage rating, and reducing number of components (inductors and switches). In order to clarify the features of the proposed structure, it has been compared with other unipolar MGs considering different aspects including the number of circuit components, number of required input supplies, amplitude of the output pulse, and the maximum voltage across switches and diodes. To validate the effectiveness of the structure, simulation and experimental results are presented. The results confirm that the proposed topology is capable of generating unipolar pulses with desirable amplitude and repetition frequency using a low-voltage dc supply. [ABSTRACT FROM AUTHOR]

This paper presents a new concept and approach for topology control and switching in distribution systems by extending the traditional circuit switching to laterals and single-phase loads. Voltage unbalance and other key performance indicators including voltage magnitudes, line loading, and energy losses are used to characterize and demonstrate the technical value of optimizing system topology on a per-phase basis in response to feeder conditions. The near-optimal per-phase topology control is defined as a series of hierarchical optimization problems. The proposed approach is applied to IEEE 13-bus and 123-bus test systems for demonstration, which included the impact of integrating electric vehicles (EVs) in the test circuit. It is concluded that the proposed approach can be effectively leveraged to improve voltage profiles with electric vehicles, the extent of which depends on the performance of the base case without EVs. [ABSTRACT FROM AUTHOR]

Inductive power transfer (IPT) for battery charging applications has significant advantages over the traditional plug-in system. Since misalignment between the primary and secondary windings is inevitable, it is of significance to improve the misalignment tolerance of IPT systems with constant-current (CC) and constant-voltage (CV) outputs for battery charging. In this paper, the load-independent output characteristic of the hybrid topology and the function switching between CC and CV of the reconfigurable topology are analyzed. Besides, a hybrid and reconfigurable IPT system with 3-D misalignment tolerance for CC and CV outputs is proposed, simplifying or even canceling control schemes. Moreover, a novel parametric design method is given for the IPT system, which can suppress the fluctuation of the output voltage/current within a certain range of misalignment. In order to validate the performance of the proposed topology, a 1-kW prototype is built, and the corresponding experiments are carried out. In the CC/CV mode, the system can operate with the longitudinal misalignment to 50% when the load varies from 36 to 480 Ω, and the fluctuation of the output current/voltage is within 5%. Similarly, the misalignment in Y- and Z-axis is 12.5% and 33.3%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents nonisolated single-switch high step-up converters with low voltage stress. Based on the conventional flyback converter, one single-switch high step-up converter is derived. The voltage stresses on the switch and diodes are limited by using a clamping diode and voltage doubler structure. Also, to further reduce the voltage stresses of them, another single-switch high step-up converter is proposed simply by using one additional capacitor and rearranging the components. Thus, lower voltage-rated switch and diodes can be used, which results in higher efficiency. The operational principle, analysis and design considerations of each converter are presented in this paper. The validity of this study is confirmed by the experimental results from 24 V input and 250 V/125 W output prototype. [ABSTRACT FROM AUTHOR]

In this paper, a single-phase multilevel ac/ac converter with reduced number of power semiconductor devices is proposed. For the simple case of a three-level converter, only three bidirectional switches and two capacitors are required. The proposed converter provides a highly sinusoidal and regulated output voltage with a simple topology. The efficiency is high because in each state of operation only one semiconductor conducts. The converter can be easily extended to any desired levels in the output voltage to even more reduce the output total harmonics distortion. Another advantage of the proposed converter is that by increasing the voltage levels, the stress on the switches will decrease. The proper performance of the proposed converter is confirmed through extensive simulation and experimental tests. [ABSTRACT FROM PUBLISHER]

A new approach for modulation of an 11-level cascade multilevel inverter using selective harmonic elimination is presented in this paper. The dc sources feeding the multilevel inverter are considered to be varying in time, and the switching angles are adapted to the dc source variation. This method uses genetic algorithms to obtain switching angles offline for different dc source values. Then, artificial neural networks are used to determine the switching angles that correspond to the real-time values of the dc sources for each phase. This implies that each one of the dc sources of this topology can have different values at any time, but the output fundamental voltage will stay constant and the harmonic content will still meet the specifications. The modulating switching angles are updated at each cycle of the output fundamental voltage. This paper gives details on the method in addition to simulation and experimental results. [ABSTRACT FROM PUBLISHER]

In this paper, a small signal model is proposed for the new unidirectional three-phase T-type rectifier topology known as five-level T-Rectifier (5L T-RECT). The proposed model is obtained starting from the large signal analytical representation of the 5L T-RECT configuration. The derived equations have been simplified using the synchronous reference frame transformation; to this purpose, the average values over the fundamental period T0 are considered for the input phase voltages. After that, the converter steady-state and dynamic models are derived by means of the local linearization around the desired operating point. The transfer functions related to the inputs and outputs of the system are, therefore, obtained and depicted. The achieved 5L T-RECT model has been first verified using the linear analysis tool in the matlab/Simulink environment starting from the detailed switching model. Theoretical results exhibit a very good accuracy between the small-signal, the large-signal, and the switching models. Then, experimental activity is depicted to further validate the proposed small-signal model. [ABSTRACT FROM AUTHOR]

This paper addresses the inverter nonlinearity of a three-level T-type inverter. The main causes of the nonlinearity are pulse shaping, pulse skipping due to narrow pulses for the dead time, and voltage drop of the switching devices. Although the same causes have existed in two-level inverters, the pulse skipping phenomenon and results are quite different in the case of the three-level T-type inverter. The effects of pulse shaping and skipping have been investigated and discussed. In addition, the voltage drop of the switching devices has been considered in conjunction with the conduction path of the T-type inverter. Compensation methods based on the pulse width modulation (PWM) of T-type inverter to alleviate the inverter nonlinearity have been proposed from research results. The proposed methods could be easily implemented by adding appropriate offset voltages to the voltage references of the inverter in PWM. Furthermore, a neutral voltage balancing method of a three-level T-type inverter has been proposed in conjunction with the proposed PWM methods using offset voltage. Through extensive experimental tests, the fifth- and seventh-harmonic components of the current are conspicuously reduced along with the even harmonics. The neutral voltage of the inverter can be balanced effectively with the proposed offset voltage adjustments as well. [ABSTRACT FROM AUTHOR]

In this paper, a new cascade switch-ladder multilevel inverter topology is presented which can generate a large number of output voltage levels. First, a fundamental switch-ladder multilevel inverter structure is described. Then, the structure of recommended cascade topology based on series connection of fundamental switch-ladder topologies is presented. To generate maximum number of levels with minimum number of switching elements, dc sources, and voltage on switches, the proposed cascade topology is optimized. Comparison results prove that the presented cascade topology requires fewer numbers of components. Also, the value of voltage rating on switches is less than other structures. Experimental results for two topologies are analyzed to verify the performance of the proposed topology. [ABSTRACT FROM PUBLISHER]

This paper deals with a new family of high boost voltage inverters called switched-inductor quasi-Z-source inverters (SL-qZSIs). The proposed SL-qZSI is based on the well-known qZSI topology and adds only one inductor and three diodes. In comparison to the SL-ZSI, for the same input and output voltages, the proposed SL-qZSI provides continuous input current, a common ground with the dc source, reduced the passive component count, reduced voltage stress on capacitors, lower shoot-through current, and lower current stress on inductors and diodes. In addition, the proposed SL-qZSI can suppress inrush current at startup, which might destroy the devices. This paper presents the operating principles, analysis, and simulation results, and compares them with those of the SL-ZSI. To verify the performance of the proposed converter, a laboratory prototype was constructed with 48 Vdc input and an ac output line-to-line voltage of 120 Vrms. The simulation and experimental results verified that the converter has high step-up inversion ability. [ABSTRACT FROM AUTHOR]

This paper presents a novel topology for a direct ac–ac power converter, called as the “three-to- k” phase matrix converter. The input to the proposed matrix converter configuration is a three-phase fixed voltage and a fixed frequency supply from the grid. The output is a variable voltage and variable frequency ac supply of any number of phases (k phase). However, the discussion is limited here for a k that is equal to odd number of phases. As an example, a “three-to-five” phase matrix converter is utilized for discussion and analysis. This paper also proposes two pulsewidth modulation (PWM) control techniques for the general topology of the “three-to- k” phase matrix converter. This is based on the so-called direct duty ratio PWM (DPWM). In one presented technique, the output voltage is limited to one half of the input voltage. For the other proposed scheme, the output voltage is enhanced to 78.86% of the input voltage. The proposed control algorithm is validated using simulation and an experimental approach. [ABSTRACT FROM AUTHOR]

The multistring LED in parallel is a popular structure in backlight and lighting applications. The current balancing for each string is required to achieve uniform luminance and reliable operation. This paper proposes a simple and precise lossless passive current balancing circuit for multiple LED strings application. With a dc block capacitor in series with the transformer secondary side and the proposed two outputs rectifier structure, the currents of the two outputs can be automatically balanced due to the charge balancing of the capacitor. Compared to the conventional active current sharing technique using switching converter or linear switch, the proposed methods can achieve high efficiency and low cost. The proposed method can be applied to both current-fed topology and voltage-fed topology, which can also be extended to even outputs application. The basic two balanced output structure with a voltage-fed half-bridge topology is analyzed in this paper to show the detailed operation principle. The design considerations for continuous conduction mode and discontinuous conduction mode operations are also presented. Performance of the proposed circuit is validated by the experimental results from a 60 W prototype with 400-V dc input. [ABSTRACT FROM AUTHOR]

This paper proposes and evaluates an active voltage-balancing method for stacked multicell converters (SMCs) using phase-shifted pulse width modulation. The method is easy to implement and can be applied to SMCs with any number of levels. The proposed method balances the voltages of the capacitors by modifying the duty cycle of each switch of the SMC using a proportional controller. The direction of the output current and the crossed effect among the duty cycles of the switches is considered and used to improve capacitor voltage balance. The performance of the proposed voltage-balancing method is verified experimentally for different loads, such as linear and nonlinear loads, and under transient conditions. [ABSTRACT FROM PUBLISHER]

This paper introduces the application of a switched-diode-capacitor voltage accumulator (SDCVA) on conventional boost converter. This study aims to obtain two different kinds of multi-input step-up converters with high voltage gains, low component stresses, low ripples, simple control, and high conversion efficiencies: one is based on the parallel SDCVA and the other based on the serial SDCVA. The double-input step-up converter based on the parallel SDCVA and the double-input step-up converter based on the serial SDCVA are, respectively, taken as an example to do theoretical analysis, including operating principles and performance analyses when they work individually and simultaneously. The two proposed converters are implemented with a voltage closed-loop control at the switching frequency of 30 kHz. Experimental results obtained from the implemented prototypes are provided to validate the feasibility and effectiveness of the proposed converters. [ABSTRACT FROM AUTHOR]

This paper introduces a digitally controlled single-phase rectifier with power factor correction (PFC) based on a modified three-level boost converter topology. In comparison with the conventional boost-based systems, the new PFC rectifier has about three times smaller inductor and significantly lower switching losses. The improvements are achieved by replacing the output capacitor of the boost converter with a nonsymmetric active capacitive divider, with a 3:1 division ratio, and by utilizing the downstream converter stage for the capacitive divider's center-tap voltage regulation. The nonsymmetric voltage divider and applied switching sequence effectively provide four-level converter behavior using the same number of components as three-level converters. As a result, a 66% reduction of the inductor compared to the conventional boost-based PFC and a 33% compared to the standard three-level solutions operating at the same effective switching frequencies are also achieved. Experimental results obtained with a 400 W, 200 kHz, universal input voltage (85 Vrms-265 Vrms) PFC prototype demonstrate three times smaller inductor current ripple than that of the conventional boost converter allowing for the same inductor reduction. Efficiency improvements of up to a 6% are also demonstrated. [ABSTRACT FROM AUTHOR]

In this paper, a novel transformer-less adjustable voltage quadrupler dc-dc converter with high-voltage transfer gain and reduced semiconductor voltage stress is proposed. The proposed topology utilizes input-parallel output-series configuration for providing a much higher voltage gain without adopting an extreme large duty cycle. The proposed converter cannot only achieve high step-up voltage gain with reduced component count but also reduce the voltage stress of both active switches and diodes. This will allow one to choose lower voltage rating MOSFETs and diodes to reduce both switching and conduction losses. In addition, due to the charge balance of the blocking capacitor, the converter features automatic uniform current sharing characteristic of the two interleaved phases for voltage boosting mode without adding extra circuitry or complex control methods. The operation principle and steady analysis as well as a comparison with other recent existing high step-up topologies are presented. Finally, some simulation and experimental results are also presented to demonstrate the effectiveness of the proposed converter. [ABSTRACT FROM AUTHOR]

In this paper, a novel three-port converter (TPC) with high-voltage gain for stand-alone renewable power system applications is proposed. This converter uses only three switches to achieve the power flow control. Two input sources share only one inductor. Thus, the volume can be reduced. Besides, the conversion ratio of the converter is higher than other TPCs. Thus, the degree of freedom of duty cycle is large. The converter can have a higher voltage gain for both low-voltage ports with a lower turns ratio and a reasonable duty ratio. The voltage stress of switches is low; thus, conduction loss can be further improved by adopting low Rds(on) switches. Therefore, the converter can achieve a high conversion ratio and high efficiency at the same time. The operation principles, steady-state analysis, and control method of the converter are presented and discussed. A prototype of the proposed converter with a low input voltage 24 V for photovoltaic source, a battery port voltage 48 V, and an output voltage 400 V is implemented to verify the theoretical analysis. The power flow control of the converter is also built and tested with a digital signal processor. [ABSTRACT FROM AUTHOR]

Multilevel converters have received increased interest recently as a result of their ability to generate high quality output waveforms with a low switching frequency. This makes them very attractive for high-power applications. A cascaded H-bridge converter (CHB) is a multilevel topology which is formed from the series connection of H-bridge cells. Optimized pulse width modulation techniques such as selective harmonic elimination or selective harmonic mitigation (SHM-PWM) are capable of preprogramming the harmonic profile of the output waveform over a range of modulation indices. Such modulation methods may, however, not perform optimally if the dc links of the CHB are not balanced. This paper presents a new SHM-PWM control strategy which is capable of meeting grid codes even under nonequal dc link voltages. The method is based on the interpolation of different sets of angles obtained for specific situations of imbalance. Both simulation and experimental results are presented to validate the proposed control method. [ABSTRACT FROM PUBLISHER]

In this paper, two reduced switch count topologies are introduced for independently supplying two single-phase ac loads with one inverter. Using a new three-switch leg structure recently introduced and implemented in three-phase converters, two types of dual-leg and single-leg topologies are developed which respectively are functionally comparable to two full-bridge and half-bridge inverters working independently though with a less number of semiconductor switches and hence control and gate drive circuit components. The proposed six-switch and three-switch topologies are introduced; two modes of equal frequency and different frequency operation each of its own distinctive characteristics are considered for them and their pulse width modulation schemes are elaborated. Comprehensive analyses of power loss profile and output waveform properties are conducted via simulation for the proposed inverters, and the results are compared with full-bridge and half-bridge inverters. To assess the performance of the proposed inverter topologies, working prototypes are built, and the experimental results are provided. [ABSTRACT FROM PUBLISHER]

This paper presents a high-efficiency switched-capacitor voltage tripler topology aimed at high-power applications. A soft-switching scheme without the addition of extra components is adopted to minimize the switching loss and the electromagnetic interference noises. A two-step current charging method is used to enable the input current and output voltage interleaving functionality without adding an excessive number of components. The large loss on the input capacitor that exists in the traditional switched-capacitor topologies is eliminated by employing this interleaving scheme. The soft switching and interleaving results are analyzed in detail. The experimental results for a 2-kW prototype are demonstrated to verify the functionality of the proposed topology. [ABSTRACT FROM AUTHOR]

Flying-capacitor converters (FCCs), like most multilevel converter topologies, require a balancing mechanism of the capacitor voltages. FCCs feature natural voltage balancing when a special modulation technique is used. The classic methods, such as phase-shifted pulse width modulation (PS-PWM), result in very slow balancing for some duty-ratio ranges. Previous work has shown that for a single-leg five-level FCC, one time constant is infinite for a zero desired output voltage. In this paper, a modified PS-PWM scheme for a single-leg five-level FCC is presented, which results in faster balancing over the total duty-ratio range. The modified PS-PWM scheme is studied, resulting in an averaged voltage-balancing model. This model is verified using simulations and experiments. The modified PS-PWM scheme solves the slow-balancing problems of the normal PS-PWM method for odd-level FCCs, while maintaining the passive control property, and it provides a self-precharge capability. [ABSTRACT FROM AUTHOR]

In this paper, a new three-level (3L) converter is presented. It is called 3L Vienna neutral-point-clamped (3L-VNPC) converter and consists of two stacked high-frequency (HF) commutation cells working with a shared power device. The HF cells are connected to a single-phase switched bridge controlled at low frequency. The 3L-VNPC topology is extended to 3L active VNPC (3L-AVNPC) concept, which is generalized for five levels (5L) and N odd voltage levels (N \L). The proposed multilevel converters can be seen as two cascaded voltage stages. The high-voltage stage is specific to the single-phase switched bridge, while the low-voltage (LV) stage corresponds to the stacked HF cells with shared power devices. The new concept AVNPC is a useful and suitable solution for medium-voltage applications, where small modulation index (M) is as crucial as large M. The analyses of the new converters are verified by simulations both for 3L and for 5L topologies, and their features are generalized for N\L. Experimental results for single-phase 3L-AVNPC converter on an LV test bench are also provided to validate the proper operation of the new concept. [ABSTRACT FROM AUTHOR]

This paper proposes a generalized scheme of new soft-switching interleaved boost converters that is suitable for high step-up and high-power applications. The proposed converter is configured with proper numbers of series and parallel connected basic cells in order to fulfill the required output voltage and power levels, respectively. This leads to flexibility in device selection resulting in high component availability and easy thermal distribution. Design examples of determining the optimum circuit configuration for given output voltage and power level are presented. Experimental results from a 1.5-kW prototype are provided to validate the proposed concept. [ABSTRACT FROM AUTHOR]

The novel multilevel circuit topologies are proposed in this paper. They are called multilevel circuit topologies based on switched-capacitor and diode-clamped converters (MCT-BSD). The topology structure and the operation principle, including the working states’ transitions of the diode-clamped part, the voltages balancing mechanism of the dc link capacitors, and the pulse width modulated carrier control strategy are given. The switched-capacitor circuits contribute not only to balancing the voltages of capacitors but also to boosting the output voltage with a certain input dc voltage. The validity of the MCT-BSD is verified by simulations and experiments. The results show that balancing the voltages of capacitors, boosting the output voltages, and operating under the three-phase condition are all realized effectively in the MCT-BSD. The simulations also show the generalization of the MCT-BSD for n-level topologies. [ABSTRACT FROM AUTHOR]

This paper presents a new three-level topology based on the neutral-point (NP)-clamped converter. An additional leg is added to the basic topology. The main purpose of this leg is to provide the converter with fault-tolerant capabilities. In addition, during normal operation mode, the fourth leg can be used to balance the NP voltage. In this way, the low-frequency voltage oscillations that appear in the NP under some operating conditions are cancelled out effectively. As a result, the modulation strategy of the three main legs of the converter does not have to take care of the voltage balance and can focus on other aspects such as, for instance, minimizing the switching losses of the converter. However, the inclusion of the fourth leg produces some additional losses. A resonant topology is proposed to minimize the switching losses of this leg. Three different fault-tolerant solutions based on the fourth-leg topology are presented. A comparison of these topologies showing their respective advantages and drawbacks is made. Experimental results are presented to show the viability of this approach. [ABSTRACT FROM AUTHOR]

Unipolar sinusoidal pulsewidth modulation (SPWM) full-bridge inverter brings high-frequency common-mode voltage, which restricts its application in transformerless photovoltaic grid-connected inverters. In order to solve this problem, an optimized full-bridge structure with two additional switches and a capacitor divider is proposed in this paper, which guarantees that a freewheeling path is clamped to half input voltage in the freewheeling period. Sequentially, the high-frequency common-mode voltage has been avoided in the unipolar SPWM full-bridge inverter, and the output current flows through only three switches in the power processing period. In addition, a clamping branch makes the voltage stress of the added switches be equal to half input voltage. The operation and clamping modes are analyzed, and the total losses of power device of several existing topologies and proposed topology are fairly calculated. Finally, the common-mode performance of these topologies is compared by a universal prototype inverter rated at 1 kW. [ABSTRACT FROM AUTHOR]

A novel three-phase diode boost rectifier is proposed in this paper. The core of the proposed topology is a power conversion device [the loss-free transformer (LFT)] with two terminals; one input and one output. The input is parallel-connected with the dc bus capacitor, while the output is connected between the rectifier plus rail and the dc bus plus rail. The LFT is controlled in such a way to control the rectifier current and boost the dc bus voltage. In contrast to the ordinary boost rectifiers, the switches of the new boost rectifier are rated on a fraction of the dc bus voltage and a fraction of the input current. It makes this topology very compact and efficient. Power rating, size, and losses depend strongly on the ratio of the dc bus voltage to rectifier voltage (boosting factor). For example, if the boosting factor is low, below 1.5, the power converter efficiency could be 98–99%. The proposed boost rectifier has been analyzed and experimentally verified on a 5.5-kW prototype. The results are presented and discussed. [ABSTRACT FROM AUTHOR]

A newly designed zero-voltage-switching (ZVS) multi-input converter is proposed in this paper. The converter can boost the different voltages of two power sources to a stable output voltage. An auxiliary circuit is employed for achieving turn-on ZVS of all switches in the proposed converter. According to various situations, the operational states of the proposed converter can be divided into two states, including a single-power-supply and a dual-power-supply state. In the dual-power-supply state, the input circuits connected in series together with the designed pulsewidth modulation can greatly reduce the conduction loss of the switches. In addition, the effectiveness of the designed circuit topology and the ZVS properties are verified by experimental results, and the goal of high-efficiency conversion can be obtained. [ABSTRACT FROM AUTHOR]

Multilevel cascaded H-bridge converters have found industrial application in the medium-voltage high-power range. In this paper, a generalized modulation technique for this type of converter based on a multidimensional control region is presented. Using the multidimensional control region, it is shown that all previous modulation techniques are particularized versions of the proposed method. Several possible solutions to develop a specific implementation of the modulation method are addressed in order to show the potential possibilities and the flexibility of the proposed technique. In addition, a feedforward version of this technique is also introduced to determine the switching sequence and the switching times, avoiding low harmonic distortion with unbalanced dc voltages. Experimental results are shown in order to validate the proposed concepts. [ABSTRACT FROM AUTHOR]

The focus of this paper is the study of direct alternating-current (ac)–ac converters, beginning by buck, half-bridge, full-bridge, and push–pull converters. From the basic converters, we apply a simple methodology to make the use of switches in commercial configurations possible. Following that, eight voltage restorers supplied either on the line side or on the load side are proposed. A comparative evaluation of these topologies concerning implementation, complexity, and component effort is presented. It is notable that some of the studied topologies are known in the literature and others are new. For one of the presented topologies, the design of a 3-kVA voltage restorer is developed, and experimental results are shown, certifying the correct operation of the drive strategy used. [ABSTRACT FROM AUTHOR]

A novel H-bridge multilevel pulsewidth modulation converter topology based on a series connection of a high-voltage diode-clamped inverter and a low-voltage conventional inverter is proposed in this paper. A dc link voltage arrangement for the new hybrid and asymmetric solution is presented to have a maximum number of output voltage levels by preserving the adjacent switching vectors between voltage levels. Hence, a 15-level hybrid converter can be attained with a minimum number of power components. A comparative study has been carried out to present high performance of the proposed configuration to approach a very low total harmonic distortion of voltage and current, which leads to the possible elimination of the output filter. Regarding the proposed configuration, a new cascade inverter is verified by cascading an asymmetrical diode-clamped inverter, in which 19 levels can be synthesized in output voltage with the same number of components. To balance the dc link capacitor voltages for the maximum output voltage resolution as well as synthesize asymmetrical dc link combination, a new multi-output boost converter is utilized at the dc link voltage of a seven-level H-bridge diode-clamped inverter. Simulation and hardware results based on different modulations are presented to confirm the validity of the proposed approach to achieve a high-quality output voltage. [ABSTRACT FROM PUBLISHER]

This paper presents a three-stage 18-level inverter design with a novel control method. The inverter consists of a series-connected main high-voltage, medium-voltage, and low-voltage stages. The high-voltage stage is made of a three-phase, six-switch conventional inverter. The medium- and low-voltage stages are made of three-level inverters constructed by H-bridge units. The proposed control strategy assumes a reference-input voltage vector and aims to operate the inverter in one state per sampling time to produce the nearest vector to that reference. The control concept is based on representing the reference voltage in 60^\circ-spaced two-axis coordinate system. In this system, the inverter vectors’ dimensions are integer multiples of the inverter's dc voltage, and the expression of the inverter's vectors in terms of its switching variables is straightforward. Consequently, the switching signals can be obtained by simple fixed-point calculations. The approach of the proposed control strategy has been presented, the transformed inverter vectors and their relation to the switching variables have been defined, and the implementation process has been described. The test results verify the effectiveness of the proposed strategy in terms of computational efficiency as well as the capability of the inverter to produce very low distorted voltage with low-switching losses. [ABSTRACT FROM PUBLISHER]

This paper describes the operation of a solid-state series stacked topology used as a serial and parallel switch in pulsed power applications. The proposed circuit, developed from the Marx generator concept, balances the voltage stress on each series stacked semiconductor, distributing the total voltage evenly. Experimental results from a 10 kV laboratory series stacked switch, using 1200 V semiconductors in a ten stages solid-state series stacked circuit, are reported and discussed, considering resistive, capacitive and inductive type loads for high and low duty factor voltage pulse operation. [ABSTRACT FROM AUTHOR]