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This paper investigates the short-circuit behavior of SiC MOSFETs in half bridge configuration during shoot-through event. The short-circuit peak current (ISCP) as well as the distribution of drain to source voltage (VDS) of half bridge configuration are analyzed under various mismatch operating condition. Further, the determinants on total amount and distribution of short-circuit energy (SC energy) are obtained. It is revealed that the device with the lowest short-circuit current carrying capacity determines the ISCP and the total SC energy of half bridge leg. Besides, the decrease of active switch common source inductance can mitigate the VDS and SC energy imbalance caused by load current. The conclusions are validated by experimental results., Part of ISBN 9798350316445QC 20240201

This paper gives a layout design principle for multichip SiC MOSFET power modules taking the transient current distribution among paralleled dies into consideration. A few typical power module layouts are analyzed and modeled with parasitic layout parameters. With the analysis and comparison, a universal and practical design principle is proposed, which is to make the direction of parallel connections perpendicular to the direction of current flow. Applying this design principle mitigates the di/dt through the parasitic inductance between the source terminals of the paralleled dies. Furthermore, this approach avoids current coupling effects, which aggravate transient current imbalances. The design principle is verified with experimental results., Part of ISBN 9789075815412QC 20231116

Power semiconductor devices are often connected in parallel to increase the current rating of the power conversion systems. However, due to mismatched circuit parameters or semiconductor fabrication discrepancies, the current of paralleled power semiconductor devices can be unbalanced, which potentially leads to accelerated aging and long-term reliability issues. The fast-switching speed of silicon carbide (SiC) devices aggravates this problem due to its higher sensitivity to parasitic parameters. Numerous efforts have been dedicated to analyzing and addressing the current imbalance issue of paralleling SiC devices. This article comprehensively summarizes and presents state-of-the-art research regarding the current imbalance in paralleled SiC devices. Degree of imbalance is proposed to comprehensively quantify the current mismatch. Starting with mechanism analysis, different types of current imbalance are categorized. Various device parameters and the package layout that impact the current distribution are investigated. The existing solutions including passive methods and active methods are concluded and categorized. This work also incorporates insight into the future development needs of high-power multichip SiC module packaging and driving technologies., QC 20230725

Frequency-domain dissipativity of the converter admittance provides an intuitive approach to analyze wideband resonances due to the interactions with the grid. Although the reasons for high- and low-frequency resonances are different, it is found that the proportional capacitor voltage feedforward (CVF) can affect and reshape the converter admittance in a wide frequency range. To enhance wideband dissipativity under a weak/capacitive grid, a proportional-integral (PI)-derivative CVF is proposed in this article. Specifically, high-frequency dissipativity can be guaranteed through the multisampling control (MSC) with proportional-derivative CVF. The low-frequency nondissipative region caused by the phase-locked loop (PLL) and proportional CVF can be compensated through multiorder integrations. In light of grid frequency disturbances, modified integrators are further proposed for the multiorder integrations. The proposed method also applies to the conventional double-sampling control (DSC) with regard to the low-frequency dissipativity enhancement. Finally, experiments validate the proposed control method., QC 20230705