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In this letter, we study the formation and electrical properties of Ni-GaSb alloys by direct reaction of Ni with GaSb. It is found that several properties of Ni-antimonide alloys, including low thermal budget processing (300 deg C), low Schottky barrier height for holes (0.1 eV), low sheet resistance of Ni-InGaSb (53 ohm/square ), and low specific contact resistivity (7.6 x 10) expn -7 ohm cm[expn 2]), show good progress toward antimonide-based metal source/drain (S/D) p-channel metal oxide semiconductor field-effect transistors. Devices with a self-aligned metal S/D were demonstrated, in which heterostructure design is adopted to further improve the performance, e.g., ON/OFF ratio (10[expn 4]), subthreshold swing (140 mV/decade), and high effective-field hole mobility of 510 cm(expn 2)/Vs at sheet charge density of 2 x 10(expn 12) cm(expn -2)., Published in IEEE Electron Device Letters, v34 n11 p1367-1369, Nov 2013. Prepared in cooperation with the Center for Integrated Systems, Department of Electrical Engineering, Stanford University, Stanford, CA, and the ilicon System Group, Applied Materials Inc., Santa Clara, CA.

Low density-of-states (DOS) of carriers and higher dielectric constants in III-Vs warrants transistor architecture with better electrostatics than conventional bulk FinFETs [1]. Additionally, the integration of III-V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III-Vs and silicon [2]. This paper presents a statistical variability study of III-V and Si FinFETs, from which SOI-FinFET architecture is recommended for III-Vs. The co-integration of InAs-OI NMOS and GaSb-OI PMOS on silicon is proposed for its excellent carrier transport and favorable band-lineup. Such hetero-integration is demonstrated on silicon substrate using rapid-melt-growth technique. © 2013 JSAP.

Transistors based on III-V semiconductor materials have been used for a variety of analog and high frequency applications driven by the high electron mobilities in III-V materials. On the other hand, the hole mobility in III-V materials has always lagged compared to group-IV semiconductors such as germanium. In this paper, we explore the use of strain and heterostructure design guided by bandstructure modeling to enhance the hole mobility in III-V materials. Parameters such as strain, valence band offset, effective masses, and splitting between the light and heavy hole bands that are important for optimizing hole transport are measured quantitatively using various experimental techniques. A peak Hall mobility for the holes of 960 cm(expn 2)/Vs is demonstrated and the high hole mobility is maintained even at high sheet charge., Published in the Journal of Applied Physics, v111 article ID 103706, 21 May 2012. Prepared in cooperation with the Department of Electrical Engineering, Center for Integrated Systems, Stanford University, Stanford, CA.

We have studied the surface cleaning of Sb-based compound semiconductors using HF, NH4OH, and HCl cleans and the metal oxide semiconductor (MOS) capacitors fabricated subsequently. GaSb, InGaSb, and AlGaSb surfaces are investigated using low-energy radiation from the synchrotron. Capacitance voltage (C V) and photoluminescence measurements are carried out on capacitors made with Al2O3 from atomic layer deposition and corroborated with the results from synchrotron spectroscopy. Excellent C V characteristics with a mid-band-gap interface state density of 3 1011/cm2eV are obtained on samples with the HCl clean. This is consistent with the finding that only the HCl acid clean is able to remove the native oxides present on GaSb and InGaSb surfaces, and produce clean and stable surfaces suitable for MOSFET development. Complete removal of AlOx on the AlGaSb surface was not possible using chemical cleaning. Termination of AlGaSb with two monolayers of GaSb is proposed as a solution, Published in Journal of Applied Physics, v109 p114908-1/114908-7, 2011.

While there have been many demonstrations on n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) in III-V semiconductors showing excellent electron mobility and high drive currents, hole mobility in III-V p-channel MOSFETs (pMOSFETs) has traditionally lagged in comparison to silicon. GaSb is an attractive candidate for high-performance III-V pMOSFETs due to its high bulk hole mobility. We fabricate and study GaSb pMOSFETs with an atomic layer deposition Al2O3 gate dielectric and a self-aligned source/drain formed by ion implantation. The band offsets of Al2O3 on GaSb were measured using synchrotron radiation photoemission spectroscopy. The use of a forming gas anneal to passivate the dangling bonds in the bulk of the dielectric was demonstrated. The density of interface states Dit was measured across the GaSb band gap using conductance measurements, and a midband-gap Dit of 3 x 10 to the 11th power/cm2eV was achieved. This enabled pMOSFETs with a peak hole mobility value of 290 cm2/Vs., Published in IEEE Transactions on Electron Devices, v58 n10 p3407-3415, October 2011.

InxGa1-xSb is an attractive candidate for high performance III-V p-metal-oxide-semiconductor field effect transistors (pMOSFETs) due to its high bulk hole mobility that can be further enhanced with the use of strain. We fabricate and study InxGa1-xSb-channel pMOSFETs with atomic layer deposition Al2O3 dielectric and self-aligned source/drain formed by ion implantation. The effects of strain and heterostructure design for enhancing transistor performance are studied systematically. Different amounts of biaxial compression are introduced during MBE growth, and the effect of uniaxial strain is studied using wafer-bending experiments. Both surface and buried channel MOSFET designs are investigated. Buried (surface) channel InxGa1-xSb pMOSFETs with peak hole mobility of 910 (620) sq cm/Vs and subthreshold swing of 120 mV/decade are demonstrated. Pulsed I-V measurements and low-temperature I-V measurements are used to investigate the physics in transistor characteristics., Published in Journal of Applied Physics, v110 article 014503, 2011.

InXGa1-xSb has the highest hole mobility amongst all III-V semiconductors which can be enhanced further with the use of strain. The use of confinement and strain in InXGa1-xSb quantum wells lifts the degeneracy between the light and heavy hole bands which leads to reduction in the hole effective mass in the lowest occupied band and an increase in the mobility. We present magnetotransport measurements on compressively strained InXGa1-xSb and GaSb quantum wells. Hall-bar and Van de Pauw structures were fabricated and Shubnikov de Haas oscillations in the temperature range of T = 2 10 K for magnetic fields of B = 0-9 T were measured. The reduction of effective hole mass with strain was quantified. These results are in excellent agreement with modeling results from band structure calculations of the effective hole mass in the presence of strain and confinement., Published in Solid-State Electronics 62 (2011) p138-141. Produced in collaboration with Stanford Univ., Center for Integrated Systems Ca.

In(sub x)Ga(sub 1-x)Sb channel materials have the highest hole and electron mobility among all III-V semiconductors, high conduction and valence band offsets (CBO/VBO) with lattice matched Al(sub x)In(sub 1-x)Sb for heterostructure MOSFET design and allow low thermal budget MOSFET fabrication. While buried channel HEMT-like devices with excellent electron and hole transport have been demonstrated, realization of an Sb-channel MOSFET has remained elusive due to the highly reactive nature of the Sb-surface. In this paper we overcome these challenges and fabricate an In(sub x)Ga(sub 1-x)Sb pMOSFET with high hole mobility: a bottleneck for III-V complimentary logic. Synchrotron Radiation Photoemission Spectroscopy (SRPES) is used to aid the development of ALD Al2O3 on GaSb with a mid bandgap Dit of 3 x 10(to the 11th power)/cm2eV-1. A p+/n diode with ideality factor of 1.4 and I(sub ON)/I(sub OFF) > 5 x 10(to the 4th power) is developed. pMOSFETs with various channel configurations to optimize the hole transport are fabricated using a sub 350 degrees Celsius gate-first process. Surface (buried) channel pMOSFETs with peak hole mobility of 620 (910) cm2/Vs and having more than 50 (100)% higher mobility than Germanium over the entire sheet charge range are demonstrated and analyzed., Published in the Proceedings of the 2010 IEEE International Electron Devices Meeting (IEDM), held on 6-8 December 2010 in San Francisco, CA. The original document contains color images. Figures on last two pages of document are condensed and difficult to read.

This report presents the results of the development of an ultrasonic sensor for in-situ monitoring of silicon wafer temperature. The sensor is based on the measurement of the velocity of ultrasonic Lamb waves in the wafer, and relating this velocity to temperature. We present a method for efficient excitation and detection of Lamb waves in the wafer, a theoretical model for relating the variation of velocity as a function of temperature, and an electronic implementation for the sensor. Our results indicate the ability to measure the temperature with an accuracy of 10C in most integrated circuit processing environments. The sensor has also been used in a tomographic configuration to allow the measurement of spatial distribution of temperature. Finally, we highlight the potential for simultaneous measurement of temperature and film thickness in-situ.

Rapid thermal processing of silicon in oxygen and ammonia reactive ambients was employed to grow thin layers of Silicon dixoide, silicon nitride and nitroxide for high-quality gate insulators of submicron CMOS VLSI. Rapid thermal oxidation of (100) silicon in dry oxygen exhibited a nonlinear growth in the short-time regime. The oxide-growth rate rises as the oxidation time is reduced, and the highest rate occurs for the shortest rapid oxidation time. The formation kinetics of the surface and interface nitrogen-rich layers in rapidly nitrided oxide dielectrics were analyzed and correlated to their electrical performance. Rapid thermal nitridation of approx. 100 A SiO2 on silicon results in a negative shift of flatband voltage, a slight rise in surface-state density, a higher low-field and a lower high field conductivity, an improvement in the dielectric breakdown field, modified trapping characteristics, and a slower generation rate of new surfce states by the high-field electrical stress., Pub. in Proceedings of the International Symposium on Silicon Materials Science and Technology (5th).

This paper presents an analysis model which correctly explains the two dimensional (2-D) current crowding effects observed in the cross bridge Kelvin resistor (CBKR). The model explains that the kelvin resistance measured by this device consists of two components, one due to specific resistivity and the other due to current flowing in the overlap region between the contact and the diffusion edges. The geometrical dependence of this second component is derived analytically and compared with two dimensional numerical simulations. It becomes significant when specific contact resistivity rho sub c < R sub s x delta - sq., where delta is the amount of overlap between edge of the contact and the edge of the diffusion path, and R sub s is the diffusion sheet resistance. (Reprints).

Metal-oxide-semiconductor devices fabricated with tungsten/n+ polysilicon composite gates and subhundred-angstrom SiO2 gate insulators grown by rapid thermal oxidation were characterized by various electrical measurements. The as-fabricated devices with unannealed rapidly grown oxides exhibited breakdown characteristics superior to furnace-grown oxides as evidenced by their excellent breakdown uniformity, an average breakdown field of 15 MV/cm, and an average breakdown charge density of over 50 C/ sq cm 2 at a stress current density of 1 A/sq cm. The preoxidation surface cleaning procedure was observed to affect the charge-to-breakdown and the densities of fixed oxide charges and surface states in these MOS structures.

Nitroxide thin films have been grown by rapid thermal nitridation of oxidized silicon in ammonia. The kinetics of formation of the surface and interface nitrogen-rich layers has been investigated and correlated to the electrical behavior of these films. It could be concluded that rapid thermal nitridation of = 100 A SiO2 results in negative shift of flatband voltage, slightly increases the surface state density, increases the low-field conductivity, reduces the high-field conductivity, improves the dielectric breakdown field, modifies the trapping behavior of the insulator, and slows down the generation rate of new surface states due to high-field electrical stress.

Continuous advancements in technology have resulted in integrated circuits with smaller device dimensions, and larger area and complexity. The overall circuit performance has depended primarily on the device properties. However, the parasitic resistance and capacitance associated with interconnections and contacts, as for an MOS transistor, are now beginning to influence the circuit performance and will be the primary factors in the evolution of submicron VLSI technology. Examples of contact resistance shallow junction series resistance and rc time delay of interconnections, respectively are shown. Results of theoretical modeling indicate that below 1 micron minimum feature size the impact of these parsitics will seriously hurt the circuit and system performance. The RC time delay, the IR voltage drop, the power consumption and the crosstalk noise due to these parastics will become appreciable. Thus even with very fast devices, the overall performance of a large circuit could be seriously affected by the limitations of interconnections and contacts. It is evident that refractory metals and silicides are playing increasingly important roles. It must be also be pointed out that these materials will not replace aluminum but compliment it. The materials which have been used or proposed for forming interconnections can be broadly classified into four categories: heavily doped polysilicon, low temperature metals, high temperature refractory metals and metal silicides. Table compares properties of some of these materials showing their compatibility with present silicon fabrication technology., Paper presented at the Symposium of the American Vacuum Society (32nd) Held in Houston, TX in Nov 85.

A film of a silicide of a refractory metal is chemically vapor deposited onto a substrate by placing a susceptor containing the substrate in a chemical vapor deposition reactor, flowing a compound of a refractory metal and a silicon bearing chemical diluted in nitrogen over the susceptor containing the substrate and heating the susceptor and substrate. The film is compatible with common integrated circuit techniques. (Author)

A novel cold wall single wafer lamp heated Rapid Thermal/Microwave Remote Plasma Multiprocessing (RTMRPM) reactor has been developed for multilayer in-situ growth and deposition of dielectrics, silicon, and metals. This equipment is the result of an attempt to enhance semiconductor processing equipment versatility, to improve process reproducibility and uniformity, to increase growth and deposition rates at reduced processing temperatures, and to achieve in situ multiprocessing in conjunction with real time process monitoring and automation. For high performance MOS VLSI applications, a variety of selective and nonselective tungsten deposition processes were investigated in this work. The tungsten gate MOS devices fabricated using the remote plasma multiprocessing techniques exhibited negligible plasma damage and near ideal electrical characteristics. The flexibility of the reactor allows optimization of each process step yet allows multiprocessing.

This paper presents a generalized model of ohmic contacts and a unified approach for the accurate extraction of specific contact resistivity rho(c) for ohmic contacts from measured contact resistance using the cross bridge Kelvin resistor, the contact end resistor, and the transmission line tap resistor test structures. A general three-dimensional (3-D) model of the contacts has been developed from the first principles and has been reduced to 2-D, 1-D, and 0-D (one lump) models with the necessary approximations. It is shown that the conventional 1-D models overestimate the value of rho(c) because of the parasitic resistance due to 2-D current flow around the periphery of the contact window. Using 2-D simulations, we have accurately modeled the current crowding effects and have extracted accurate values of rho(c) independent of contact size and the test structure type. A theory of scaling of contacts has been developed and is applied to commonly used structures. A universal set of curves has been derived for each particular contact resistance test structure and, given the geometry of the structure, these allow accurate determination of RHO (c) without the actual use of the 2-D simulator. Experimental and theoretical ree test structures has been compared. Accurate values of rho(c) for various contact materials to n+ and p+ Si have been determined. The data confirm that in the past researchers have overestimated rho(c) and that rho(c) will not limit device performance even with submicrometer design rules. (Reprints).

Low temperatures and short times are essential requirements of future VLSI presenting and the use of plasma in conjunction with single-wafer lamp heating is a major step to realize this goal. In-situ multiprocessing reduces contamination and enhances yield. Reproducible growth of thin oxides in hot-wall furnaces is difficult due to long transient times and constant furnace temperatures. Since furnaces are not designed for single-wafer processing, no extensive in-situ real-time measurements can be performed. RTP of Si in O2 and NH3 ambients is an attractive technique for the growth of silicon nitride, silicon dioxide, nitrided oxides, oxidized nitrides, and application-specific insulators. The feasibility of low temperature nitridation of Si nitrogen plasma generated by microwave discharge is demonstrated. LPCVD of tungsten (W) has emerged as a viable technology for VLSI. The conventional hot wall furnaces are not suitable for reproducible high rate W deposition and nonselective formation of W on insulators., Presented at the VLSI Symposium, 1987.