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Overlapping sound events are ubiquitous in real-world environments, but existing end-to-end sound event detection (SED) methods still struggle to detect them effectively. A critical reason is that these methods represent overlapping events using shared and entangled frame-wise features, which degrades the feature discrimination. To solve the problem, we propose a disentangled feature learning framework to learn a category-specific representation. Specifically, we employ different projectors to learn the frame-wise features for each category. To ensure that these feature does not contain information of other categories, we maximize the common information between frame-wise features within the same category and propose a frame-wise contrastive loss. In addition, considering that the labeled data used by the proposed method is limited, we propose a semi-supervised frame-wise contrastive loss that can leverage large amounts of unlabeled data to achieve feature disentanglement. The experimental results demonstrate the effectiveness of our method., Comment: accepted by icassp2024

We experimentally demonstrate a GaN/SiC hybrid field-effect transistor (HyFET)—a novel power electron device that can harness the complementary merits of GaN and SiC and circumvent their notorious drawbacks. The HyFET regulates currents by gating an AlGaN/GaN high-mobility 2- dimensional-electron-gas (2DEG) channel and blocks voltages with a vertical SiC junction-field-effect-transistor (JFET) structure. The channel mobility can be boosted by ~100 times compared to a SiC MOS-channel. The HyFET can be vertically configured to provide voltage blocking with avalanche capability and be free of the dynamic ON-resistance issue, which are difficult for GaN HEMTs. Critical technology enablers for implementing the GaN/SiC HyFET include a dual-epitaxy SiC JFET structure, GaN epitaxy on patterned 4°- off-axis 4H-SiC substrate, and a Damascene-process-based in- cell interconnection solution. Our experimental demonstration unveils a new power device platform that gears toward the utmost integration of these two prevailing wide-bandgap semiconductors.

As the only known intelligent civilization, human beings are always curious about the existence of other communicating extraterrestrial intelligent civilizations (CETIs). Based on the latest astrophysical information, we carry out Monte Carlo simulations to estimate the number of possible CETIs within our Galaxy and the communication probability among them. Two poorly known parameters have a great impact on the results. One is the probability of life appearing on terrestrial planets and eventually evolving a into CETI ($f_c$), and the other determines at what stage of their host star's evolution CETIs would be born ($F$). In order to ensure the completeness of the simulation, we consider a variety of combinations of $f_c$ and $F$. Our results indicate that for optimistic situations (e.g. $F=25\%$ and $f_c=0.1\%$), there could be $42777_{-369}^{+267}$ CETIs and they need to survive for $3_{-2}^{+17}$ yr ($2000_{-1400}^{+2000}$ yr) to achieve one-way communication (two-way communication). In this case, human beings need to survive $0.3_{-0.298}^{+0.6}$ Myr to receive one alien signal. For pessimistic situations (e.g. $F=75\%$ and $f_c=0.001\%$), only $111_{-17}^{+28}$ CETIs could be born and they need to survive for $0.8_{-0.796}^{+1.2}$ Myr ($0.9_{-0.88}^{+4.1}$ Myr) to achieve one-way communication (two-way communication). In this case, human beings need to survive $50_{-49.6}^{+250}$ Myr to receive one signal from other CETIs. Our results may quantitatively explain why we have not detected any alien signals so far. The uncertainty of the results has been discussed in detail and would be alleviated with the further improvement of our astronomical observation ability in the future., Comment: Published in ApJ

Enhancement-mode (E-mode) p-channel gallium nitride (GaN) field-effect transistors (p-FETs) are essential components for GaN-based complementary logic circuits. For the ease of integration with n-FETs, they could be fabricated on the commercial p-GaN gate high-electronmobility-transistor (HEMT) platform, on which the two-dimensional electron gas at the AlGaN/GaN hetero-interface is completely depleted in as-grown epi-structures. However, under the gated region where p-GaN is recessed and depleted at thermal equilibrium, a parasitic electron channel (PEC) could appear at the AlGaN/GaN interface. This Letter reports experimental investigations on the PEC with specifically designed structures, confirming that the PEC does exist but imposes limited impacts on electrical characteristics of p-FETs. When connected with an external contact, the PEC could act as a back gate to modulate the overlaying p-channel. If isolated from external contacts, which is the case of p-FETs under normal operations, electrons in the PEC would redistribute under the active region of p-FETs in the horizontal direction (i.e., parallel to the surface) under different biases but are mostly confined near the AlGaN/GaN interface in the vertical direction (i.e., perpendicular to the surface).

A tunnel-oxide-free GaN-based non-volatile memory (NVM) device is proposed to untangle the trilemma among speed, retention, and endurance in the implementation of conventional NVM. The program and erase (P/E) are based on bipolar charge injection controlled by individual junction barriers, whereas the data retention relies on bipolar charge trapping in an interfacial charge storage layer. The wide bandgap energy of GaN allows the formation of deep-level traps at a dielectric/GaN interface and high junction barriers in GaN, both of which benefit long-term retention. As such, the GaN-based NVM device could get rid of the tunnel oxide, thereby enabling faster P/E processes and facilitating to decouple the enhancement of endurance from that of speed and retention. The proposed device demonstrates a P/E time of 100 ns, endurance over 106 cycles, and long retention time. IEEE

The hybrid field-effect transistor (HyFET) superior for power electronic applications can be created by harnessing the merits of two representative wide-bandgap semiconductors, GaN and SiC. Yet, the incompactness in the epitaxy techniques hinders the development of the HyFET—GaN is usually grown on on-axis foreign substrates including SiC, whereas SiC homoepitaxy prefers off-axis substrates. This work presents a GaN-based heterostructure epitaxially grown on a conventional 4° off-axis 4H-SiC substrate and manifests its high quality and suitability for constructing GaN-based high electron mobility transistors (HEMTs), thereby suggesting a practical approach to realizing the HyFET. In the meanwhile, a distinct two-step biaxial strain relaxation process is proposed and studied with comprehensive characterizations.

p-channel GaN field-effect transistors (FETs) with a SiNx/GaON gate stack have been demonstrated with enhanced stability within a wide range of voltage bias and temperature. In this letter, the gate leakage characteristics and reliability of this unconventional staggered gate stack is investigated. At relatively low gate voltages, the gate current is suppressed owing to the buried-channel structure and the presence of GaON that presents an effective hole barrier. With more negative gate biases, the gate leakage was found to be dominated by the transport of holes that spillover from the p-channel through the SiNx via Poole-Frenkel emission. Based on this gate leakage mechanism at large gate bias, √ model was used for gate lifetime prediction. The maximum applicable ON-state gate voltage of -7.3 V is obtained for a 10-year lifetime with a 1% gate failure rate. IEEE

As the only known intelligent civilization, human beings are always curious about the existence of other communicating extraterrestrial intelligent civilizations (CETIs). Based on the latest astrophysical information, we carry out Monte Carlo simulations to estimate the number of possible CETIs within our Galaxy and the communication probability among them. Two poorly known parameters have a great impact on the results. One is the probability of life appearing on terrestrial planets and eventually evolving a into CETI ($f_c$), and the other determines at what stage of their host star's evolution CETIs would be born ($F$). In order to ensure the completeness of the simulation, we consider a variety of combinations of $f_c$ and $F$. Our results indicate that for optimistic situations (e.g. $F=25\%$ and $f_c=0.1\%$), there could be $42777_{-369}^{+267}$ CETIs and they need to survive for $3_{-2}^{+17}$ yr ($2000_{-1400}^{+2000}$ yr) to achieve one-way communication (two-way communication). In this case, human beings need to survive $0.3_{-0.298}^{+0.6}$ Myr to receive one alien signal. For pessimistic situations (e.g. $F=75\%$ and $f_c=0.001\%$), only $111_{-17}^{+28}$ CETIs could be born and they need to survive for $0.8_{-0.796}^{+1.2}$ Myr ($0.9_{-0.88}^{+4.1}$ Myr) to achieve one-way communication (two-way communication). In this case, human beings need to survive $50_{-49.6}^{+250}$ Myr to receive one signal from other CETIs. Our results may quantitatively explain why we have not detected any alien signals so far. The uncertainty of the results has been discussed in detail and would be alleviated with the further improvement of our astronomical observation ability in the future., Comment: Published in ApJ

Enhancement-mode (E-mode) p-channel gallium nitride (GaN) field-effect transistors (p-FETs) are essential components for GaN-based complementary logic circuits. For the ease of integration with n-FETs, they could be fabricated on the commercial p-GaN gate high-electronmobility-transistor (HEMT) platform, on which the two-dimensional electron gas at the AlGaN/GaN hetero-interface is completely depleted in as-grown epi-structures. However, under the gated region where p-GaN is recessed and depleted at thermal equilibrium, a parasitic electron channel (PEC) could appear at the AlGaN/GaN interface. This Letter reports experimental investigations on the PEC with specifically designed structures, confirming that the PEC does exist but imposes limited impacts on electrical characteristics of p-FETs. When connected with an external contact, the PEC could act as a back gate to modulate the overlaying p-channel. If isolated from external contacts, which is the case of p-FETs under normal operations, electrons in the PEC would redistribute under the active region of p-FETs in the horizontal direction (i.e., parallel to the surface) under different biases but are mostly confined near the AlGaN/GaN interface in the vertical direction (i.e., perpendicular to the surface).

The hybrid field-effect transistor (HyFET) superior for power electronic applications can be created by harnessing the merits of two representative wide-bandgap semiconductors, GaN and SiC. Yet, the incompactness in the epitaxy techniques hinders the development of the HyFET—GaN is usually grown on on-axis foreign substrates including SiC, whereas SiC homoepitaxy prefers off-axis substrates. This work presents a GaN-based heterostructure epitaxially grown on a conventional 4° off-axis 4H-SiC substrate and manifests its high quality and suitability for constructing GaN-based high electron mobility transistors (HEMTs), thereby suggesting a practical approach to realizing the HyFET. In the meanwhile, a distinct two-step biaxial strain relaxation process is proposed and studied with comprehensive characterizations.

A tunnel-oxide-free GaN-based non-volatile memory (NVM) device is proposed to untangle the trilemma among speed, retention, and endurance in the implementation of conventional NVM. The program and erase (P/E) are based on bipolar charge injection controlled by individual junction barriers, whereas the data retention relies on bipolar charge trapping in an interfacial charge storage layer. The wide bandgap energy of GaN allows the formation of deep-level traps at a dielectric/GaN interface and high junction barriers in GaN, both of which benefit long-term retention. As such, the GaN-based NVM device could get rid of the tunnel oxide, thereby enabling faster P/E processes and facilitating to decouple the enhancement of endurance from that of speed and retention. The proposed device demonstrates a P/E time of 100 ns, endurance over 106 cycles, and long retention time.

A cost-effective engineered bulk silicon (EBUS) substrate technology is presented, featuring p-n junction implemented on bulk Si substrates using mainstream ion implantation and thermal annealing processes. Standard p-GaN/AlGaN/GaN heterostructures are successfully grown on the EBUS substrate and used to fabricate 200-V enhancement-mode p-GaN gate HEMTs. By creating deep trenches in the EBUS substrate to isolate the local P+ silicon regions underneath the high-side (HS) and low-side (LS) power switches, adverse effects (e.g., back-gating and dynamic on-resistance degradation) in the use of conventional bulk Si substrate are all eliminated. The mechanism of crosstalk suppression in the GaN-on-EBUS platform is revealed in comparison with conventional GaN-on-Si platform and verified by a series of designed tests. IEEE

GaN p-channel field-effect transistors (p-FETs) are essential components for implementing the energy-efficient complementary logic circuitry for monolithic GaN power integration. This letter reports the threshold voltage (VTH) instability of p-channel GaN MOSFETs with Al2O3 as the gate dielectric. When the gate-to-source bias sweeps toward the negative direction, the VTH exhibits a shift toward more negative values. The impacts of such VTH instability on GaN complementary logic circuits are characterized using logic inverters and ring oscillators. It is shown that impacts on circuit functions are limited with an operating voltage swing below 5 V. However, the propagation delay could be gradually prolonged, as a result of drifting VTH. IEEE

The surface of the p-GaN layer in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) can be reinforced with enhanced immunity to hot electron bombardment by reconstructing the surface region of p-GaN into GaON. The surface region of p-GaN is treated by remote oxygen plasma and subsequently annealed at 800 °C, thereby becoming a thin crystalline gallium oxynitride (GaON) layer that will be in direct contact with the Schottky metal. The GaON exhibits a lower valence band maximum energy than that of the p-GaN, which leads to a higher Schottky barrier at the metal/GaON interface to holes and, thus, greatly suppresses the forward gate leakage. More importantly, with higher thermodynamic stability and a larger bandgap of ∼4.1 eV, the GaON reinforces the susceptible metal/p-GaN interface against the hot electrons and, thus, substantially enhances the long-term gate reliability of p-GaN gate HEMTs under forward bias stress. The high-temperature thermal process is indispensable for the surface reconstruction, without which the plasma oxidation only reduces the gate leakage but fails to prolong the time-dependent gate breakdown lifetime. © 2021 Author(s).

Owing to its energy efficiency, silicon complementary metal–oxide–semiconductor (CMOS) technology is the current driving force of the integrated circuit industry. Silicon’s narrow bandgap has led to the advancement of wide-bandgap semiconductor materials, such as gallium nitride (GaN), being favoured in power electronics, radiofrequency power amplifiers and harsh environment applications. However, the development of GaN CMOS logic circuits has proved challenging because of the lack of a suitable strategy for integrating n-channel and p-channel field-effect transistors on a single substrate. Here we report the monolithic integration of enhancement-mode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits. We construct a family of elementary logic gates—including NOT, NAND, NOR and transmission gates—and show that the inverters exhibit rail-to-rail operation, suppressed static power dissipation, high thermal stability and large noise margins. We also demonstrate latch cells and ring oscillators comprising cascading logic inverters. © 2021, The Author(s), under exclusive licence to Springer Nature Limited.

Magnons (the quanta of spin waves), unlike electrons, do not suffer from Ohmic losses, which makes them an attractive information carrier in communication and data processing. The possibility of nonreciprocal magnon propagation is of great practical relevance to directional communications, particularly when the nonreciprocity is steerable through magnons themselves in a monologic magnonic device. This work demonstrates explicitly such nonreciprocity in the mode profiles of magnons in Ni79Fe21 thin films. Evidence of nonreciprocal emergence of hybridized dipole-exchange spin waves at two surfaces of Ni79Fe21 nanofilms deposited on a surface oxide silicon substrate is provided by studying magnon transmission and asymmetry via Brillouin light scattering measurements. The dipole-dominated spin wave and exchange-dominated spin wave are found to be localized near the top and bottom surfaces, respectively, and travel along opposite directions. The nonreciprocity and the localization can be tuned by an in-plane magnetic field. Our findings provide a simple and flexible approach to nonreciprocal all-magnon logic devices highly compatible with silicon-based integrated circuit technology.

We report a processing technique to form a surface reinforcement layer (SRL) in GaN metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) with the aim to suppress device dynamic on-resistance (RON) degradation caused by long-Term hot-electron stress. The SRL is a crystalline (Al)GaON layer formed by reconstruction of the heterojunction surface through plasma oxidation and high temperature annealing. MIS-HEMTs with SRL exhibit substantially suppressed dynamic RON degradation than the conventional devices without SRL, after long-Term hot-electron stress. The (Al)GaON SRL exhibits substantially enhanced thermal stability and strong immunity to energetic carriers. The SRL-enabled suppression of hot-electron-induced degradation is further verified by the electroluminescence characterizations.

GaN-based complementary logic (CL) integrated circuits (ICs) for the prospective power integration have been demonstrated on the commercial p-GaN gate power HEMT (high-electron-mobility transistor) platform. This work reports a delicately designed gate structure featuring a SiNx/in-situ-GaOxN1-x staggered gate stack on GaN p-channel field-effect transistors (p-FETs) for stability enhancement. The threshold voltage of GaN p-FETs with such a novel gate stack is barely changed within wide ranges of negative and positive voltage bias and temperature, which thereby enables the implementation of stable GaN CL ICs. The optimized monolithic GaN CL inverters and ring oscillators preserve decent performances and exhibit high stability over long-period operations and across a temperature range from 25 °C to 400 °C. As such, it becomes much more feasible for energy-efficient GaN-based CL functional blocks to be integrated into GaN power ICs. © 2021 IEEE.

A novel GaN power IC platform on engineered bulk Si (EBUS) substrate is demonstrated for monolithic integration of 200-V high-side and low-side p-GaN HEMTs of a half-bridge circuit. The engineered substrate features a P+-N-doping profile realized by P-Type implantation into an N-Type (111) Si wafer. The P+ Si layer is then split into P+ islands using deep trenches and are effectively isolated through back-To-back PN junctions. The P+ island provides a local electrical substrate for the overlaying GaN HEMT, while all GaN HEMTs share the same bulk Si wafer; such configuration enables monolithic GaN power integration with eliminated crosstalk associated with conventional bulk Si that serves as a common electrical substrate.

Owing to its energy efficiency, silicon complementary metal–oxide–semiconductor (CMOS) technology is the current driving force of the integrated circuit industry. Silicon’s narrow bandgap has led to the advancement of wide-bandgap semiconductor materials, such as gallium nitride (GaN), being favoured in power electronics, radiofrequency power amplifiers and harsh environment applications. However, the development of GaN CMOS logic circuits has proved challenging because of the lack of a suitable strategy for integrating n-channel and p-channel field-effect transistors on a single substrate. Here we report the monolithic integration of enhancement-mode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits. We construct a family of elementary logic gates—including NOT, NAND, NOR and transmission gates—and show that the inverters exhibit rail-to-rail operation, suppressed static power dissipation, high thermal stability and large noise margins. We also demonstrate latch cells and ring oscillators comprising cascading logic inverters. © 2021, The Author(s), under exclusive licence to Springer Nature Limited.

We report a processing technique to form a surface reinforcement layer (SRL) in GaN metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) with the aim to suppress device dynamic on-resistance (RON) degradation caused by long-Term hot-electron stress. The SRL is a crystalline (Al)GaON layer formed by reconstruction of the heterojunction surface through plasma oxidation and high temperature annealing. MIS-HEMTs with SRL exhibit substantially suppressed dynamic RON degradation than the conventional devices without SRL, after long-Term hot-electron stress. The (Al)GaON SRL exhibits substantially enhanced thermal stability and strong immunity to energetic carriers. The SRL-enabled suppression of hot-electron-induced degradation is further verified by the electroluminescence characterizations.

The surface of the p-GaN layer in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) can be reinforced with enhanced immunity to hot electron bombardment by reconstructing the surface region of p-GaN into GaON. The surface region of p-GaN is treated by remote oxygen plasma and subsequently annealed at 800 °C, thereby becoming a thin crystalline gallium oxynitride (GaON) layer that will be in direct contact with the Schottky metal. The GaON exhibits a lower valence band maximum energy than that of the p-GaN, which leads to a higher Schottky barrier at the metal/GaON interface to holes and, thus, greatly suppresses the forward gate leakage. More importantly, with higher thermodynamic stability and a larger bandgap of ∼4.1 eV, the GaON reinforces the susceptible metal/p-GaN interface against the hot electrons and, thus, substantially enhances the long-term gate reliability of p-GaN gate HEMTs under forward bias stress. The high-temperature thermal process is indispensable for the surface reconstruction, without which the plasma oxidation only reduces the gate leakage but fails to prolong the time-dependent gate breakdown lifetime. © 2021 Author(s).

GaN p-channel field-effect transistors (p-FETs) are essential components for implementing the energy-efficient complementary logic circuitry for monolithic GaN power integration. This letter reports the threshold voltage (VTH) instability of p-channel GaN MOSFETs with Al2O3 as the gate dielectric. When the gate-to-source bias sweeps toward the negative direction, the VTH exhibits a shift toward more negative values. The impacts of such VTH instability on GaN complementary logic circuits are characterized using logic inverters and ring oscillators. It is shown that impacts on circuit functions are limited with an operating voltage swing below 5 V. However, the propagation delay could be gradually prolonged, as a result of drifting VTH.

Magnons (the quanta of spin waves), unlike electrons, do not suffer from Ohmic losses, which makes them an attractive information carrier in communication and data processing. The possibility of nonreciprocal magnon propagation is of great practical relevance to directional communications, particularly when the nonreciprocity is steerable through magnons themselves in a monologic magnonic device. This work demonstrates explicitly such nonreciprocity in the mode profiles of magnons in Ni79Fe21 thin films. Evidence of nonreciprocal emergence of hybridized dipole-exchange spin waves at two surfaces of Ni79Fe21 nanofilms deposited on a surface oxide silicon substrate is provided by studying magnon transmission and asymmetry via Brillouin light scattering measurements. The dipole-dominated spin wave and exchange-dominated spin wave are found to be localized near the top and bottom surfaces, respectively, and travel along opposite directions. The nonreciprocity and the localization can be tuned by an in-plane magnetic field. Our findings provide a simple and flexible approach to nonreciprocal all-magnon logic devices highly compatible with silicon-based integrated circuit technology.

GaN-based complementary logic (CL) integrated circuits (ICs) for the prospective power integration have been demonstrated on the commercial p-GaN gate power HEMT (high-electron-mobility transistor) platform. This work reports a delicately designed gate structure featuring a SiNx/in-situ-GaOxN1-x staggered gate stack on GaN p-channel field-effect transistors (p-FETs) for stability enhancement. The threshold voltage of GaN p-FETs with such a novel gate stack is barely changed within wide ranges of negative and positive voltage bias and temperature, which thereby enables the implementation of stable GaN CL ICs. The optimized monolithic GaN CL inverters and ring oscillators preserve decent performances and exhibit high stability over long-period operations and across a temperature range from 25 °C to 400 °C. As such, it becomes much more feasible for energy-efficient GaN-based CL functional blocks to be integrated into GaN power ICs. © 2021 IEEE.

GaN p-channel field-effect transistors (p-FETs) are essential components for implementing the energy-efficient complementary logic circuitry for monolithic GaN power integration. This letter reports the threshold voltage (VTH) instability of p-channel GaN MOSFETs with Al2O3 as the gate dielectric. When the gate-to-source bias sweeps toward the negative direction, the VTH exhibits a shift toward more negative values. The impacts of such VTH instability on GaN complementary logic circuits are characterized using logic inverters and ring oscillators. It is shown that impacts on circuit functions are limited with an operating voltage swing below 5 V. However, the propagation delay could be gradually prolonged, as a result of drifting VTH.

Owing to its energy efficiency, silicon complementary metal–oxide–semiconductor (CMOS) technology is the current driving force of the integrated circuit industry. Silicon’s narrow bandgap has led to the advancement of wide-bandgap semiconductor materials, such as gallium nitride (GaN), being favoured in power electronics, radiofrequency power amplifiers and harsh environment applications. However, the development of GaN CMOS logic circuits has proved challenging because of the lack of a suitable strategy for integrating n-channel and p-channel field-effect transistors on a single substrate. Here we report the monolithic integration of enhancement-mode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits. We construct a family of elementary logic gates—including NOT, NAND, NOR and transmission gates—and show that the inverters exhibit rail-to-rail operation, suppressed static power dissipation, high thermal stability and large noise margins. We also demonstrate latch cells and ring oscillators comprising cascading logic inverters. © 2021, The Author(s), under exclusive licence to Springer Nature Limited.

Magnons (the quanta of spin waves), unlike electrons, do not suffer from Ohmic losses, which makes them an attractive information carrier in communication and data processing. The possibility of nonreciprocal magnon propagation is of great practical relevance to directional communications, particularly when the nonreciprocity is steerable through magnons themselves in a monologic magnonic device. This work demonstrates explicitly such nonreciprocity in the mode profiles of magnons in Ni79Fe21 thin films. Evidence of nonreciprocal emergence of hybridized dipole-exchange spin waves at two surfaces of Ni79Fe21 nanofilms deposited on a surface oxide silicon substrate is provided by studying magnon transmission and asymmetry via Brillouin light scattering measurements. The dipole-dominated spin wave and exchange-dominated spin wave are found to be localized near the top and bottom surfaces, respectively, and travel along opposite directions. The nonreciprocity and the localization can be tuned by an in-plane magnetic field. Our findings provide a simple and flexible approach to nonreciprocal all-magnon logic devices highly compatible with silicon-based integrated circuit technology.

The surface of the p-GaN layer in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) can be reinforced with enhanced immunity to hot electron bombardment by reconstructing the surface region of p-GaN into GaON. The surface region of p-GaN is treated by remote oxygen plasma and subsequently annealed at 800 °C, thereby becoming a thin crystalline gallium oxynitride (GaON) layer that will be in direct contact with the Schottky metal. The GaON exhibits a lower valence band maximum energy than that of the p-GaN, which leads to a higher Schottky barrier at the metal/GaON interface to holes and, thus, greatly suppresses the forward gate leakage. More importantly, with higher thermodynamic stability and a larger bandgap of ∼4.1 eV, the GaON reinforces the susceptible metal/p-GaN interface against the hot electrons and, thus, substantially enhances the long-term gate reliability of p-GaN gate HEMTs under forward bias stress. The high-temperature thermal process is indispensable for the surface reconstruction, without which the plasma oxidation only reduces the gate leakage but fails to prolong the time-dependent gate breakdown lifetime. © 2021 Author(s).

A novel GaN power IC platform on engineered bulk Si (EBUS) substrate is demonstrated for monolithic integration of 200-V high-side and low-side p-GaN HEMTs of a half-bridge circuit. The engineered substrate features a P+-N-doping profile realized by P-Type implantation into an N-Type (111) Si wafer. The P+ Si layer is then split into P+ islands using deep trenches and are effectively isolated through back-To-back PN junctions. The P+ island provides a local electrical substrate for the overlaying GaN HEMT, while all GaN HEMTs share the same bulk Si wafer; such configuration enables monolithic GaN power integration with eliminated crosstalk associated with conventional bulk Si that serves as a common electrical substrate.

We report a processing technique to form a surface reinforcement layer (SRL) in GaN metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) with the aim to suppress device dynamic on-resistance (RON) degradation caused by long-Term hot-electron stress. The SRL is a crystalline (Al)GaON layer formed by reconstruction of the heterojunction surface through plasma oxidation and high temperature annealing. MIS-HEMTs with SRL exhibit substantially suppressed dynamic RON degradation than the conventional devices without SRL, after long-Term hot-electron stress. The (Al)GaON SRL exhibits substantially enhanced thermal stability and strong immunity to energetic carriers. The SRL-enabled suppression of hot-electron-induced degradation is further verified by the electroluminescence characterizations.

GaN power IC's are expected to help unlock the full potential of GaN power electronics, especially in terms of promoting the high-frequency power switching applications. This paper first discusses a GaN power integration technology platform based on commercially available p-GaN gate HEMT technology. An integrated gate driver is presented as an example of GaN power IC with enhanced performance, in which a bootstrap unit is adopted to realize rail-to-rail output voltage and fast switching speed. To deal with GaN-specific design issues such as the unique dynamic VTH, a SPICE model of p-GaN gate HEMT is developed to improve design accuracy. Future prospects for GaN power integration are discussed by extending the integration's landscape to multi-functional GaN power devices, GaN CMOS technology, and GaN/SiC hybrid power IC's. © 2020 IEEE.

Spin waves (SWs) in coupled Co/FeNi bilayers are probed by the Brillouin light-scattering technique. Two types of SWs, magnetostatic surface spin waves (MSSWs) and perpendicular standing SWs, are identified. The dispersion relations of MSSWs obtained from the Stokes and anti-Stokes measurements display, respectively, positive and negative group velocities. The anti-Stokes branch with positive phase velocities and negative group velocities is called the backward magnetostatic surface mode that originates from the magnetostatic interaction in the bilayer. Experimental data agree well with our theoretical calculations. Our results are used to understand SWs propagation. © 2020 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

A 700-V normally-off p-GaN gate power transistor with distributed built-in Schottky barrier diode (SBD) is demonstrated in this work. The transistor cell and diode cell are alternately arrayed along the device width and are locally isolated using ion implantations. The built-in SBD provides a low reverse turn-on voltage which is independent of the threshold voltage and gate bias of the transistor. Compared to the two-device scheme consisting of an anti-parallel p-GaN gate HEMT/SBD pair, the proposed transistor exploits the common access region in both forward conduction and reverse conduction, thus a significant reduction in chip area is obtained. © 1980-2012 IEEE.

Enhancement-mode (E-mode) buried p-channel GaN metal-oxide-semiconductor field-effect-transistors (p-GaN-MOSFET's) with threshold voltage (VTH) of-1.7 V, maximum ON-state current (ION) of 6.1 mA/mm and ION/IOFF ratio of 107 are demonstrated on a standard p-GaN/AlGaN/GaN-on-Si power HEMT substrate. An oxygen plasma treatment (OPT) was deployed to the gated p-GaN region where a relatively thick (i.e. 31 nm) GaN is retained without aggressive gate recess. The OPT converts the top portion of the GaN layer to be free of holes so that only the bottom portion remains p-type while being spatially separated from the etched GaN surface and gate-oxide/GaN interface. As a result, E-mode operation is enabled while a high-quality ${p}$-channel is retained. Multi-energy fluorine ion implantation was implemented for planar isolation of GaN p-channel FETs with mesa edges and sidewalls eliminated. Consequently, high ION/IOFF ratio is obtained. © 2019 IEEE.

Enhancement-mode (E-mode) buried p-channel GaN metal-oxide-semiconductor field-effect-transistors (p-GaN-MOSFET's) with threshold voltage (VTH) of-1.7 V, maximum ON-state current (ION) of 6.1 mA/mm and ION/IOFF ratio of 107 are demonstrated on a standard p-GaN/AlGaN/GaN-on-Si power HEMT substrate. An oxygen plasma treatment (OPT) was deployed to the gated p-GaN region where a relatively thick (i.e. 31 nm) GaN is retained without aggressive gate recess. The OPT converts the top portion of the GaN layer to be free of holes so that only the bottom portion remains p-type while being spatially separated from the etched GaN surface and gate-oxide/GaN interface. As a result, E-mode operation is enabled while a high-quality ${p}$-channel is retained. Multi-energy fluorine ion implantation was implemented for planar isolation of GaN p-channel FETs with mesa edges and sidewalls eliminated. Consequently, high ION/IOFF ratio is obtained. © 2019 IEEE.

GaN power IC's are expected to help unlock the full potential of GaN power electronics, especially in terms of promoting the high-frequency power switching applications. This paper first discusses a GaN power integration technology platform based on commercially available p-GaN gate HEMT technology. An integrated gate driver is presented as an example of GaN power IC with enhanced performance, in which a bootstrap unit is adopted to realize rail-to-rail output voltage and fast switching speed. To deal with GaN-specific design issues such as the unique dynamic VTH, a SPICE model of p-GaN gate HEMT is developed to improve design accuracy. Future prospects for GaN power integration are discussed by extending the integration's landscape to multi-functional GaN power devices, GaN CMOS technology, and GaN/SiC hybrid power IC's. © 2020 IEEE.

A 700-V normally-off p-GaN gate power transistor with distributed built-in Schottky barrier diode (SBD) is demonstrated in this work. The transistor cell and diode cell are alternately arrayed along the device width and are locally isolated using ion implantations. The built-in SBD provides a low reverse turn-on voltage which is independent of the threshold voltage and gate bias of the transistor. Compared to the two-device scheme consisting of an anti-parallel p-GaN gate HEMT/SBD pair, the proposed transistor exploits the common access region in both forward conduction and reverse conduction, thus a significant reduction in chip area is obtained. © 1980-2012 IEEE.

Spin waves (SWs) in coupled Co/FeNi bilayers are probed by the Brillouin light-scattering technique. Two types of SWs, magnetostatic surface spin waves (MSSWs) and perpendicular standing SWs, are identified. The dispersion relations of MSSWs obtained from the Stokes and anti-Stokes measurements display, respectively, positive and negative group velocities. The anti-Stokes branch with positive phase velocities and negative group velocities is called the backward magnetostatic surface mode that originates from the magnetostatic interaction in the bilayer. Experimental data agree well with our theoretical calculations. Our results are used to understand SWs propagation. © 2020 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

A 700-V normally-off p-GaN gate power transistor with distributed built-in Schottky barrier diode (SBD) is demonstrated in this work. The transistor cell and diode cell are alternately arrayed along the device width and are locally isolated using ion implantations. The built-in SBD provides a low reverse turn-on voltage which is independent of the threshold voltage and gate bias of the transistor. Compared to the two-device scheme consisting of an anti-parallel p-GaN gate HEMT/SBD pair, the proposed transistor exploits the common access region in both forward conduction and reverse conduction, thus a significant reduction in chip area is obtained. © 1980-2012 IEEE.

Enhancement-mode (E-mode) buried p-channel GaN metal-oxide-semiconductor field-effect-transistors (p-GaN-MOSFET's) with threshold voltage (VTH) of-1.7 V, maximum ON-state current (ION) of 6.1 mA/mm and ION/IOFF ratio of 107 are demonstrated on a standard p-GaN/AlGaN/GaN-on-Si power HEMT substrate. An oxygen plasma treatment (OPT) was deployed to the gated p-GaN region where a relatively thick (i.e. 31 nm) GaN is retained without aggressive gate recess. The OPT converts the top portion of the GaN layer to be free of holes so that only the bottom portion remains p-type while being spatially separated from the etched GaN surface and gate-oxide/GaN interface. As a result, E-mode operation is enabled while a high-quality ${p}$-channel is retained. Multi-energy fluorine ion implantation was implemented for planar isolation of GaN p-channel FETs with mesa edges and sidewalls eliminated. Consequently, high ION/IOFF ratio is obtained. © 2019 IEEE.

GaN power IC's are expected to help unlock the full potential of GaN power electronics, especially in terms of promoting the high-frequency power switching applications. This paper first discusses a GaN power integration technology platform based on commercially available p-GaN gate HEMT technology. An integrated gate driver is presented as an example of GaN power IC with enhanced performance, in which a bootstrap unit is adopted to realize rail-to-rail output voltage and fast switching speed. To deal with GaN-specific design issues such as the unique dynamic VTH, a SPICE model of p-GaN gate HEMT is developed to improve design accuracy. Future prospects for GaN power integration are discussed by extending the integration's landscape to multi-functional GaN power devices, GaN CMOS technology, and GaN/SiC hybrid power IC's. © 2020 IEEE.

Spin waves (SWs) in coupled Co/FeNi bilayers are probed by the Brillouin light-scattering technique. Two types of SWs, magnetostatic surface spin waves (MSSWs) and perpendicular standing SWs, are identified. The dispersion relations of MSSWs obtained from the Stokes and anti-Stokes measurements display, respectively, positive and negative group velocities. The anti-Stokes branch with positive phase velocities and negative group velocities is called the backward magnetostatic surface mode that originates from the magnetostatic interaction in the bilayer. Experimental data agree well with our theoretical calculations. Our results are used to understand SWs propagation. © 2020 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Fengzhi Yang,1,* Jialin Ding,1,* Ruqing Ma,1 Wenjie Song,2 Yajing Jia,1 Jinfeng Zhao,3 Xiaoshi Yang1 1Department of Social Medicine, School of Public Health, China Medical University, Shenyang, Liaoning Province 110122, People’s Republic of China; 2Office of Clinical Quality Improvement, Children’s Hospital of Philadelphia, Philadelphia, PA 19147, USA; 3Faculty of Medical and Health Sciences, The University of Auckland, Auckland 1142, New Zealand*These authors contributed equally to this workCorrespondence: Xiaoshi YangDepartment of Social Medicine, School of Public Health, China Medical University, No. 77 Puhe Road, Shenyang North New Area, Shenyang, Liaoning Province 110122, People’s Republic of ChinaTel +86-18900910796Fax +862431939406Email xsyang@cmu.edu.cnPurpose: Nurses are high-risk groups for job burnout, which affect their quality of life (QOL). Recovery experience, a conceptualization of positive psychological resources, can combat the negative impacts of job burnout on health and QOL. The aim of this study was to examine the mediating effect of recovery experience on the relationship between job burnout and QOL among female nurses in China.Participants and Methods: QOL information was captured from 1068 female nurses from December 2017 to February 2018 in tertiary hospitals in Shenyang, Liaoning Province of China. A structural equation model was employed to examine the mediating effect of recovery experience on the relationship between job burnout and QOL.Results: Job burnout had a significant impact on both the mental component summary and the physical component summary of a 36-item Short-Form Health Survey. However, mental component summary scores were significantly lower than physical component summary scores in female nurses. Recovery experience played a mediating role in the relationship between job burnout and QOL.Conclusion: Job burnout could result in a reduction in QOL among Chinese female nurses. Recovery experience

Junwen Zhang,* Sheng Fang,* Wenjie Song, Bo Zhang, Wenhua Fan, Guishan Jin, Fusheng Liu Brain Tumor Research Center, Beijing Neurosurgical Institute, Beijing Laboratory of Biomedical Materials, Beijing Tiantan Hospital Affiliated to Capital Medical University, Beijing 100070, People’s Republic of China*These authors contributed equally to this workCorrespondence: Fusheng LiuBrain Tumor Research Center, Beijing Neurosurgical Institute, Department of Neurosurgery, Beijing Tiantan Hospital Affiliated to Capital Medical University, No. 119 Nansihuanxilu, Fengtai District, Beijing 100070, People’s Republic of ChinaTel +86-10-59975626Email liufusheng@ccmu.edu.cnPurpose: Gliomas are common intracranial tumors, of which 70% are malignant gliomas. Glioblastoma multiforme (GBM) is the most aggressive tumor, and patients with GBM have a median survival time of only 9– 12 months; extracranial recurrence of GBM is very rare. A therapeutic strategy for this kind of recurrent tumor is lacking.Materials and Methods: We present a case of a patient with extracranial recurrence of subscalp GBM. The subscalp tumor was resected and xenotransplanted into BALB/C nude mice. Then, glioma cells were isolated from the xenograft models and passaged in vitro. HE staining, immunohistochemistry, CCK-8 assays, karyotypic analysis, short tandem repeat STR analysis and flow cytometry were used to analyze the biological characteristics and malignant phenotype of these established cells. The cells and xenografts were then used as preclinical models to evaluate the antitumor efficacy of oncolytic herpes simplex virus 1 (oHSV-1).Results: The isolated cells, which were named BT-01, were positive for Nestin and GFAP. The main characteristics of BT-01 cells were that they harbored glioblastoma stem-like cells (GSCs) and that they possessed highly aggressive migration capacities compared with the existing cell lines U87-MG and U251-MG. Moreover, BT-01 cells tolerated the chemot

A 1200-V/100-mΩ GaN/SiC cascode device is demonstrated with small capacitances for fast switching speed, no dynamic ON-resistance (R ON) degradation, and stable high-temperature threshold voltage (V TH). To identify its safe operation in the OFF-state with a high drain bias, the middle point voltage (V M) between the GaN and SiC devices is investigated under static and dynamic modes. An adequately low V M is achieved at both static and dynamic states. A voltage distribution process found that the OFF-state V M is capacitance-dependent during the turn-off transient and turns to be resistance-dependent to match the leakage current with a steady drain bias. © 2019 The Japan Society of Applied Physics.

A 0.5-um-gate GaN double-channel high-electron-mobility transistor (DC-HEMT) with enhanced linearity was demonstrated. The device delivers an fT of 36.5 GHz and an fMAX of 66.5 GHz. The device was deployed on a GaN-on-Si platform, featuring a second 2DEG channel formed by inserting a 1.5-nm AlN insertion layer (AlN-ISL) several nanometers underneath the conventional 2DEG channel at the AlGaN/GaN interface. The lower and upper channels could be turned on sequentially by increasing VGS. When the DC-HEMT is biased with a large VGS to obtain high drive current, the field-effect mobility of the lower channel could be maintained at a high level because it is shielded by the upper channel that is fully turn-on. As a result, a broad GM-VGS curve with two peaks was obtained. fT was almost flat and maintained higher than 30 GHz within a wide range of gate bias.

A 0.5-um-gate GaN double-channel high-electron-mobility transistor (DC-HEMT) with enhanced linearity was demonstrated. The device delivers an fT of 36.5 GHz and an fMAX of 66.5 GHz. The device was deployed on a GaN-on-Si platform, featuring a second 2DEG channel formed by inserting a 1.5-nm AlN insertion layer (AlN-ISL) several nanometers underneath the conventional 2DEG channel at the AlGaN/GaN interface. The lower and upper channels could be turned on sequentially by increasing VGS. When the DC-HEMT is biased with a large VGS to obtain high drive current, the field-effect mobility of the lower channel could be maintained at a high level because it is shielded by the upper channel that is fully turn-on. As a result, a broad GM-VGS curve with two peaks was obtained. fT was almost flat and maintained higher than 30 GHz within a wide range of gate bias.

A 0.5-um-gate GaN double-channel high-electron-mobility transistor (DC-HEMT) with enhanced linearity was demonstrated. The device delivers an fT of 36.5 GHz and an fMAX of 66.5 GHz. The device was deployed on a GaN-on-Si platform, featuring a second 2DEG channel formed by inserting a 1.5-nm AlN insertion layer (AlN-ISL) several nanometers underneath the conventional 2DEG channel at the AlGaN/GaN interface. The lower and upper channels could be turned on sequentially by increasing VGS. When the DC-HEMT is biased with a large VGS to obtain high drive current, the field-effect mobility of the lower channel could be maintained at a high level because it is shielded by the upper channel that is fully turn-on. As a result, a broad GM-VGS curve with two peaks was obtained. fT was almost flat and maintained higher than 30 GHz within a wide range of gate bias.

Most of existing correlation filter-based tracking approaches only estimate simple axis-aligned bounding boxes, and very few of them is capable of recovering the underlying similarity transformation. To tackle this challenging problem, in this paper, we propose a new correlation filter-based tracker with a novel robust estimation of similarity transformation on the large displacements. In order to efficiently search in such a large 4-DoF space in real-time, we formulate the problem into two 2-DoF sub-problems and apply an efficient Block Coordinates Descent solver to optimize the estimation result. Specifically, we employ an efficient phase correlation scheme to deal with both scale and rotation changes simultaneously in log-polar coordinates. Moreover, a variant of correlation filter is used to predict the translational motion individually. Our experimental results demonstrate that the proposed tracker achieves very promising prediction performance compared with the state-of-the-art visual object tracking methods while still retaining the advantages of high efficiency and simplicity in conventional correlation filter-based tracking methods., Comment: Accepted by AAAI 2019