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Your search keyword '"William J. Dally"' showing total 26 results
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26 results on '"William J. Dally"'

1. A bandwidth-efficient architecture for a streaming media processor

Author

William J. Dally., Massachusetts Institute of Technology. Department Electrical Engineering and Computer Science., Rixner, Scott, William J. Dally., Massachusetts Institute of Technology. Department Electrical Engineering and Computer Science., and Rixner, Scott

Abstract

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2001., Includes bibliographical references (p. 143-146)., by Scott Rixner., Ph.D.

Published
2014

2. A bandwidth-efficient architecture for a streaming media processor

Author

William J. Dally., Massachusetts Institute of Technology. Department Electrical Engineering and Computer Science., Rixner, Scott, William J. Dally., Massachusetts Institute of Technology. Department Electrical Engineering and Computer Science., and Rixner, Scott

Abstract

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2001., Includes bibliographical references (p. 143-146)., by Scott Rixner., Ph.D.

Published
2014

3. A subspace optimizing data parallel complier

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., Dampier, Todd O. (Todd Orion), William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., and Dampier, Todd O. (Todd Orion)

Abstract

Thesis (M.Eng. and B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 1995., Includes bibliographical references (p. 96)., Scientific programs with large data sets are an important class of computer application, requiring large amounts of memory and computational power. Massively parallel processing hardware and data parallel programming techniques are increasingly used to meet these requirements. A new approach to data parallel compilation, the Subspace compilation model, is introduced. This model is based on the idea that the shapes of data objects and how these shapes change represent higher-level performance considerations that the alignment of individual data elements. This model also removes the ad hoc restrictions of the prevalent Single Program, Multiple Data (SPMD) model. A Subspace compiler is designed based on the Subspace model, employing subspace trees as its program representation. A significant part of this compiler is implemented, with the CM-5 CM Fortran platform as its target. The implementation is tested on benchmark code, and the results discussed., by Todd O. Dampier., M.Eng.and B.S.

Published
2007

4. A subspace optimizing data parallel complier

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., Dampier, Todd O. (Todd Orion), William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., and Dampier, Todd O. (Todd Orion)

Abstract

Thesis (M.Eng. and B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 1995., Includes bibliographical references (p. 96)., Scientific programs with large data sets are an important class of computer application, requiring large amounts of memory and computational power. Massively parallel processing hardware and data parallel programming techniques are increasingly used to meet these requirements. A new approach to data parallel compilation, the Subspace compilation model, is introduced. This model is based on the idea that the shapes of data objects and how these shapes change represent higher-level performance considerations that the alignment of individual data elements. This model also removes the ad hoc restrictions of the prevalent Single Program, Multiple Data (SPMD) model. A Subspace compiler is designed based on the Subspace model, employing subspace trees as its program representation. A significant part of this compiler is implemented, with the CM-5 CM Fortran platform as its target. The implementation is tested on benchmark code, and the results discussed., by Todd O. Dampier., M.Eng.and B.S.

Published
2007

5. A video controller and distributed frame buffer for the J-machine

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, McDonald, Eric Lawrence, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and McDonald, Eric Lawrence

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995., Includes bibliographical references (p. 201-202)., by Eric Lawrence McDonald., M.S.

Published
2006

6. A video controller and distributed frame buffer for the J-machine

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, McDonald, Eric Lawrence, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and McDonald, Eric Lawrence

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995., Includes bibliographical references (p. 201-202)., by Eric Lawrence McDonald., M.S.

Published
2006

7. A video controller and distributed frame buffer for the J-machine

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, McDonald, Eric Lawrence, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and McDonald, Eric Lawrence

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995., Includes bibliographical references (p. 201-202)., by Eric Lawrence McDonald., M.S.

Published
2006

8. Asynchronous event handing

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, Chatterjee, Sandeep, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and Chatterjee, Sandeep

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997., Includes bibliographical references (p. 55-56)., by Sandeep Chatterjee., M.S.

Published
2005

9. A network element based fault tolerant processor

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, Abler, Todd A. (Todd Alan), William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and Abler, Todd A. (Todd Alan)

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988., Includes bibliographical references (leaves 147-149)., by Todd A. Abler., M.S.

Published
2005

10. A message passing system for a fault tolerant parallel processor

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., Heyda, Russell Lawrence, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., and Heyda, Russell Lawrence

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1987., Bibliography: leaves 130-131., by Russell Lawrence Heyda., M.S.

Published
2005

11. A reconfigurable arithmetic processor

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., Fiske, James Alexander Stuart, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., and Fiske, James Alexander Stuart

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1989., Includes bibliographical references., by James Alexander Stuart Fiske., M.S.

Published
2005

12. Asynchronous event handing

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, Chatterjee, Sandeep, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and Chatterjee, Sandeep

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997., Includes bibliographical references (p. 55-56)., by Sandeep Chatterjee., M.S.

Published
2005

13. A message passing system for a fault tolerant parallel processor

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., Heyda, Russell Lawrence, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., and Heyda, Russell Lawrence

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1987., Bibliography: leaves 130-131., by Russell Lawrence Heyda., M.S.

Published
2005

14. VLSI datapath choices : cell-based versus full-custom

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, Chang, Andrew Liang Ping, 1965, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and Chang, Andrew Liang Ping, 1965

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998., Includes bibliographical references (leaves 138-146)., by Andrew Liang Ping Chang., M.S.

Published
2005

15. A reconfigurable arithmetic processor

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., Fiske, James Alexander Stuart, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., and Fiske, James Alexander Stuart

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1989., Includes bibliographical references., by James Alexander Stuart Fiske., M.S.

Published
2005

16. PHD--a hierarchical cache coherent protocol

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, Wallach, Deborah A. (Deborah Anne), William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and Wallach, Deborah A. (Deborah Anne)

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1992., Includes bibliographical references (p. 155-157)., by Deborah A. Wallach., M.S.

Published
2005

17. The reliable router : an architecture for fault tolerant interconnect

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, Dennison, Larry R. (Larry Robert), William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and Dennison, Larry R. (Larry Robert)

Abstract

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996., Includes bibliographical references (p. 152-154)., by Larry R. Dennison., Ph.D.

Published
2005

18. A network element based fault tolerant processor

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, Abler, Todd A. (Todd Alan), William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and Abler, Todd A. (Todd Alan)

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988., Includes bibliographical references (leaves 147-149)., by Todd A. Abler., M.S.

Published
2005

19. VLSI datapath choices : cell-based versus full-custom

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, Chang, Andrew Liang Ping, 1965, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and Chang, Andrew Liang Ping, 1965

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998., Includes bibliographical references (leaves 138-146)., by Andrew Liang Ping Chang., M.S.

Published
2005

20. Asynchronous event handing

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, Chatterjee, Sandeep, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and Chatterjee, Sandeep

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997., Includes bibliographical references (p. 55-56)., by Sandeep Chatterjee., M.S.

Published
2005

21. The subspace model : shape-based compilation for parallel systems

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, Knobe, Kathleen Beth, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and Knobe, Kathleen Beth

Abstract

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997., Includes bibliographical references (p. 207-211)., by Kathleen B. Knobe., Ph.D.

Published
2005

22. A numerical engine for distributed sparse matrices

Author

Jacob K. White, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, Telichevesky, Ricardo, Jacob K. White, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and Telichevesky, Ricardo

Abstract

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994., Includes bibliographical references (p. 169-173)., by Ricardo Telichevesky., Ph.D.

Published
2005

23. PHD--a hierarchical cache coherent protocol

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, Wallach, Deborah A. (Deborah Anne), William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and Wallach, Deborah A. (Deborah Anne)

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1992., Includes bibliographical references (p. 155-157)., by Deborah A. Wallach., M.S.

Published
2005

24. A reconfigurable arithmetic processor

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., Fiske, James Alexander Stuart, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., and Fiske, James Alexander Stuart

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1989., Includes bibliographical references., by James Alexander Stuart Fiske., M.S.

Published
2005

25. A message passing system for a fault tolerant parallel processor

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., Heyda, Russell Lawrence, William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science., and Heyda, Russell Lawrence

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1987., Bibliography: leaves 130-131., by Russell Lawrence Heyda., M.S.

Published
2005

26. PHD--a hierarchical cache coherent protocol

Author

William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, Wallach, Deborah A. (Deborah Anne), William J. Dally., Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, and Wallach, Deborah A. (Deborah Anne)

Abstract

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1992., Includes bibliographical references (p. 155-157)., by Deborah A. Wallach., M.S.

Published
2005

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