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During the last two decades, the topic of the Internet of Things (IoT) has become very popular. It provides an idea that everything in the real world should be connected with the internet in the future. Integrating sensors into small wireless networked nodes is a huge challenge due to the low power/energy budget in wireless sensor systems. An integrated sensor normally consumes significant power and has complex design which increases the cost. The core part of the sensor is the sensor interface which consumes major power especially for a capacitor-based sensor. Capacitive sensors and voltage sensors are two frequently used sensor types in the wireless sensor family. Capacitive sensors, that transform capacitance values into digital outputs, can be used in areas such as biomedical, environmental, and mobile applications. Voltage sensors are also widely used in many modern areas such as Energy Harvesting (EH) systems. Both of these sensors may make use of sensor interfaces to transform a measured analogue signal into a frequency output or a digital code for use in a digital system. Existing sensor interfaces normally use complex analog-to-digital converter (ADC) techniques that consume high power and suffers from slow sensing response. This thesis proposes a smart all-digital dual-use capacitorbased sensor interface called charge to digital converter (QDC). This QDC is capable of not only sensing capacitance but also sensing voltages by using fully digital solutions based on iterative delay chain discharge. Unlike the conventional methods vii that only treats the sensed capacitance only as the input signal, this thesis proposes a method that can directly use the stored energy from the sensed capacitance as well to power parts of the circuit, which simplifies the design and saves power. By playing with the capacitance and input voltage, it can be used as a capacitance-to-digital converter (CDC) to sense capacitance under fixed input voltage and it also can be used as a capacitorbased voltage sensor interface to measure voltage level under fixed capacitance. The new method achieves the same accuracy with less than half the circuit size, and 25% and 33% savings on power and energy consumption compared with the state of art benchmark. The method has been validated by experimenting with a chip fabricated in 350nm process, in addition to extensive simulation analysis.