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Chemical looping combustion technology is essential to achieve efficient decarbonized electricity generation for fossil-fueled power plants. However, the existing chemical looping hydrogen generation (CLHG)-driven cogeneration systems have complex refrigeration units and energy-consuming carbon capture. This study proposes a novel solid oxide fuel cell (SOFC)-based combined cooling, heating, and power (CCHP) system, which is integrated with the CLHG and fueled by a liquid natural gas (LNG) regasification process. The system is designed to enhance the overall performance by directly recovering LNG cold energy for cooling and liquefying the resulting CO2. The energy and exergy performance of the system under the baseline design case are evaluated. Subsequently, we discuss the impact of key design parameters on system performance and weigh between cooling/heating power and net power generation for the system dominated by the combined heat and power (CHP)/combined cooling and power (CCP) mode. Our findings reveal that the proposed system exhibits an electrical efficiency of 66.92 % and an exergy efficiency of 53.94 % under the baseline design case. The exergy loss ratio for condenser1 is identified as the highest among all components, accounting for 29.50 %. The constituent unit with the largest exergy loss contribution is the LNG regasification unit, followed by the SOFC unit, CLHG unit, transcritical CO2 cycle unit, and heating unit. More hydrogen needs to be replenished when fuel flow in the CLHG and fuel utilization in the SOFC are used to improve system performance. The optimal electrical and exergy efficiencies of the system predominantly designed in CCP mode surpass those in CHP mode by 4.27 % and 0.57 %, respectively. The results can guide potential applications of CLHG-based cogeneration systems. © 2024 Elsevier Ltd

As the third-generation neural network, the Spiking Neural Network (SNN) has the advantages of low power consumption and high energy efficiency, making it suitable for implementation on edge devices. More recently, the most advanced SNN, Spikformer, combines the self-attention module from Transformer with SNN to achieve remarkable performance. However, it adopts larger channel dimensions in MLP layers, leading to an increased number of redundant model parameters. To effectively decrease the computational complexity and weight parameters of the model, we explore the Lottery Ticket Hypothesis (LTH) and discover a very sparse ($\ge$90%) subnetwork that achieves comparable performance to the original network. Furthermore, we also design a lightweight token selector module, which can remove unimportant background information from images based on the average spike firing rate of neurons, selecting only essential foreground image tokens to participate in attention calculation. Based on that, we present SparseSpikformer, a co-design framework aimed at achieving sparsity in Spikformer through token and weight pruning techniques. Experimental results demonstrate that our framework can significantly reduce 90% model parameters and cut down Giga Floating-Point Operations (GFLOPs) by 20% while maintaining the accuracy of the original model.

Spiking Neural Networks (SNNs) are a biologically plausible neural network model with significant advantages in both event-driven processing and spatio-temporal information processing, rendering SNNs an appealing choice for energyefficient object detection. However, the non-differentiability of the biological neuronal dynamics model presents a challenge during the training of SNNs. Furthermore, a suitable decoding strategy for object detection in SNNs is currently lacking. In this study, we introduce the Current Mean Decoding (CMD) method, which solves the regression problem to facilitate the training of deep SNNs for object detection tasks. Based on the gradient surrogate and CMD, we propose the SNN-YOLOv3 model for object detection. Our experiments demonstrate that SNN-YOLOv3 achieves a remarkable performance with an mAP of 61.87% on the PASCAL VOC dataset, requiring only 6 time steps. Compared to SpikingYOLO, we have managed to increase mAP by nearly 10% while reducing energy consumption by two orders of magnitude.

Spiking Neural Network (SNN), as a brain-inspired approach, is attracting attention due to its potential to produce ultra-high-energy-efficient hardware. Competitive learning based on Spike-Timing-Dependent Plasticity (STDP) is a popular method to train an unsupervised SNN. However, previous unsupervised SNNs trained through this method are limited to a shallow network with only one learnable layer and cannot achieve satisfactory results when compared with multi-layer SNNs. In this paper, we eased this limitation by: 1)We proposed a Spiking Inception (Sp-Inception) module, inspired by the Inception module in the Artificial Neural Network (ANN) literature. This module is trained through STDP-based competitive learning and outperforms the baseline modules on learning capability, learning efficiency, and robustness. 2)We proposed a Pooling-Reshape-Activate (PRA) layer to make the Sp-Inception module stackable. 3)We stacked multiple Sp-Inception modules to construct multi-layer SNNs. Our algorithm outperforms the baseline algorithms on the hand-written digit classification task, and reaches state-of-the-art results on the MNIST dataset among the existing unsupervised SNNs., Comment: Published at the 2020 International Joint Conference on Neural Networks (IJCNN); Extended from arXiv:2001.01680

Spiking neural networks (SNNs) receive widespread attention because of their low-power hardware characteristic and brain-like signal response mechanism, but currently, the performance of SNNs is still behind Artificial Neural Networks (ANNs). We build an information theory-inspired system called Stochastic Probability Adjustment (SPA) system to reduce this gap. The SPA maps the synapses and neurons of SNNs into a probability space where a neuron and all connected pre-synapses are represented by a cluster. The movement of synaptic transmitter between different clusters is modeled as a Brownian-like stochastic process in which the transmitter distribution is adaptive at different firing phases. We experimented with a wide range of existing unsupervised SNN architectures and achieved consistent performance improvements. The improvements in classification accuracy have reached 1.99% and 6.29% on the MNIST and EMNIST datasets respectively., Comment: Published at the 25th International Conference on Pattern Recognition (ICPR2020)

Spiking Neural Networks (SNNs) are brain-inspired, event-driven machine learning algorithms that have been widely recognized in producing ultra-high-energy-efficient hardware. Among existing SNNs, unsupervised SNNs based on synaptic plasticity, especially Spike-Timing-Dependent Plasticity (STDP), are considered to have great potential in imitating the learning process of the biological brain. Nevertheless, the existing STDP-based SNNs have limitations in constrained learning capability and/or slow learning speed. Most STDP-based SNNs adopted a slow-learning Fully-Connected (FC) architecture and used a sub-optimal vote-based scheme for spike decoding. In this paper, we overcome these limitations with: 1) a design of high-parallelism network architecture, inspired by the Inception module in Artificial Neural Networks (ANNs); 2) use of a Vote-for-All (VFA) decoding layer as a replacement to the standard vote-based spike decoding scheme, to reduce the information loss in spike decoding and, 3) a proposed adaptive repolarization (resetting) mechanism that accelerates SNNs' learning by enhancing spiking activities. Our experimental results on two established benchmark datasets (MNIST/EMNIST) show that our network architecture resulted in superior performance compared to the widely used FC architecture and a more advanced Locally-Connected (LC) architecture, and that our SNN achieved competitive results with state-of-the-art unsupervised SNNs (95.64%/80.11% accuracy on the MNIST/EMNISE dataset) while having superior learning efficiency and robustness against hardware damage. Our SNN achieved great classification accuracy with only hundreds of training iterations, and random destruction of large numbers of synapses or neurons only led to negligible performance degradation., Comment: Published at Neurocomputing

QC 20150807

To better understand the multiphase fluid dynamics and associated transport processes of cavitating flows at the capillary number of 0.74 and 0.54, and to validate the numerical results, a combined computational and experimental investigation of flows around a hydrofoil is studied based on flow visualizations and time-resolved interface movement. The computational model is based on a modified RNG k-ε model as turbulence closure, along with a vapor-liquid mass transfer model for treating the cavitation process. Overall, favorable agreement between the numerical and experimental results is observed. It is shown that the cavitation structure depends on the interaction of the water-vapor mixture and the vapor among the whole cavitation stage, the interface between the vapor and the two-phase mixture exhibits substantial unsteadiness. And, the adverse motion of the interface relates to pressure and velocity fluctuations inside the cavity. In particular, the velocity in the vapor region is lower than that in the two-phase region. © 2008 The Chinese Society of Theoretical and Applied Mechanics and Springer-Verlag GmbH.

A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock domains is presented. The architecture supports correct operation in applications where multiple clock cycles of latency exist between the data producer, FIFO, and the data consumer; and with arbitrary clock frequency changes, halting, and restarting in either or both clock domains. The architecture is demonstrated in both a 0.18 um CMOS full-custom design and a 0.18 um CMOS standard cell design used in a globally asynchronous locally synchronous array processor. It achieves 580 MHz operation and 10.3 mW power dissipation while performing simultaneous FIFO READ and WRITE operations at 1.8 V.

A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock domains is presented. The architecture supports correct operation in applications where multiple clock cycles of latency exist between the data producer, FIFO, and the data consumer; and with arbitrary clock frequency changes, halting, and restarting in either or both clock domains. The architecture is demonstrated in both a 0.18 um CMOS full-custom design and a 0.18 um CMOS standard cell design used in a globally asynchronous locally synchronous array processor. It achieves 580 MHz operation and 10.3 mW power dissipation while performing simultaneous FIFO READ and WRITE operations at 1.8 V.