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The Path Computation Element (PCE) is a network entity utilized for network path computation operations, especially useful in optical networks based on wavelength division multiplexing (WDM). In the PCE paradigm, the communication between a node and the PCE is specified by the Path Computation Element Communication Protocol (PCEP). According to PCEP protocol, multiple LSP (Label Switched Path) requests can be bundled together before being sent to the PCE in order to reduce the control overhead. Multiple bundles received by the PCE can then be provisioned at once as a single bulk. Enabling bulk provisioning of LSP requests at the PCE in a concurrent manner can bring significant improvements in terms of higher network resource utilization and control plane overhead reduction. However, these advantages come at a cost of a longer connection setup-time and of an instantaneous increase in the network load, which may lead to a degradation of the network performance, e.g. blocking probability. In this study pros and cons of bulk provisioning are explored in shared path protection (SPP) by comparing sequential and concurrent path computation strategies. An efficient meta-heuristic named GRASP-SPP-BP (Greedy Random Adoptive Search Procedure for Shared Path Protection with Bulk Provisioning) is proposed for concurrent provisioning of primary and shared backup path pairs. GRASP-SPP-BP minimizes the backup resource consumption while requiring minimal path computation time. The presented results demonstrate that, in a SPP network scenario, a significant reduction in the PCEP control overhead, network blocking probability and backup resource consumption can be achieved via LSP bulk provisioning at the PCE with the proposed GRASP-SPP-BP approach., QC 20111219

The host-multi-SIMD chip multiprocessor (CMP) architecture has been proved to be an efficient architecture for high performance signal processing which explores both task level parallelism by multi-core processing and data level parallelism by SIMD processors. Different from the cache-based memory subsystem in most general purpose processors, this architecture uses on-chip scratchpad memory (SPM) as processor local data buffer and allows software to explicitly control the data movements in the memory hierarchy. This SPM-based solution is more efficient for predictable signal processing in embedded systems where data access patterns are known at design time. The predictable performance is especially important for real time signal processing. According to Amdahl¡¯s law, the nonparallelizable part of an algorithm has critical impact on the overall performance. Implementing an algorithm in a parallel platform usually produces control and communication overhead which is not parallelizable. This paper presents the architectural support in an embedded multiprocessor platform to maximally reduce the parallel processing overhead. The effectiveness of these architecture designs in boosting parallel performance is evaluated by an implementation example of 64x64 complex matrix multiplication. The result shows that the parallel processing overhead is reduced from 369% to 28%., ePUMA

The host-multi-SIMD chip multiprocessor (CMP) architecture has been proved to be an efficient architecture for high performance signal processing which explores both task level parallelism by multi-core processing and data level parallelism by SIMD processors. Different from the cache-based memory subsystem in most general purpose processors, this architecture uses on-chip scratchpad memory (SPM) as processor local data buffer and allows software to explicitly control the data movements in the memory hierarchy. This SPM-based solution is more efficient for predictable signal processing in embedded systems where data access patterns are known at design time. The predictable performance is especially important for real time signal processing. According to Amdahl¡¯s law, the nonparallelizable part of an algorithm has critical impact on the overall performance. Implementing an algorithm in a parallel platform usually produces control and communication overhead which is not parallelizable. This paper presents the architectural support in an embedded multiprocessor platform to maximally reduce the parallel processing overhead. The effectiveness of these architecture designs in boosting parallel performance is evaluated by an implementation example of 64x64 complex matrix multiplication. The result shows that the parallel processing overhead is reduced from 369% to 28%., ePUMA

The host-multi-SIMD chip multiprocessor (CMP) architecture has been proved to be an efficient architecture for high performance signal processing which explores both task level parallelism by multi-core processing and data level parallelism by SIMD processors. Different from the cache-based memory subsystem in most general purpose processors, this architecture uses on-chip scratchpad memory (SPM) as processor local data buffer and allows software to explicitly control the data movements in the memory hierarchy. This SPM-based solution is more efficient for predictable signal processing in embedded systems where data access patterns are known at design time. The predictable performance is especially important for real time signal processing. According to Amdahl¡¯s law, the nonparallelizable part of an algorithm has critical impact on the overall performance. Implementing an algorithm in a parallel platform usually produces control and communication overhead which is not parallelizable. This paper presents the architectural support in an embedded multiprocessor platform to maximally reduce the parallel processing overhead. The effectiveness of these architecture designs in boosting parallel performance is evaluated by an implementation example of 64x64 complex matrix multiplication. The result shows that the parallel processing overhead is reduced from 369% to 28%., ePUMA

The host-multi-SIMD chip multiprocessor (CMP) architecture has been proved to be an efficient architecture for high performance signal processing which explores both task level parallelism by multi-core processing and data level parallelism by SIMD processors. Different from the cache-based memory subsystem in most general purpose processors, this architecture uses on-chip scratchpad memory (SPM) as processor local data buffer and allows software to explicitly control the data movements in the memory hierarchy. This SPM-based solution is more efficient for predictable signal processing in embedded systems where data access patterns are known at design time. The predictable performance is especially important for real time signal processing. According to Amdahl¡¯s law, the nonparallelizable part of an algorithm has critical impact on the overall performance. Implementing an algorithm in a parallel platform usually produces control and communication overhead which is not parallelizable. This paper presents the architectural support in an embedded multiprocessor platform to maximally reduce the parallel processing overhead. The effectiveness of these architecture designs in boosting parallel performance is evaluated by an implementation example of 64x64 complex matrix multiplication. The result shows that the parallel processing overhead is reduced from 369% to 28%., ePUMA

The host-multi-SIMD chip multiprocessor (CMP) architecture has been proved to be an efficient architecture for high performance signal processing which explores both task level parallelism by multi-core processing and data level parallelism by SIMD processors. Different from the cache-based memory subsystem in most general purpose processors, this architecture uses on-chip scratchpad memory (SPM) as processor local data buffer and allows software to explicitly control the data movements in the memory hierarchy. This SPM-based solution is more efficient for predictable signal processing in embedded systems where data access patterns are known at design time. The predictable performance is especially important for real time signal processing. According to Amdahl¡¯s law, the nonparallelizable part of an algorithm has critical impact on the overall performance. Implementing an algorithm in a parallel platform usually produces control and communication overhead which is not parallelizable. This paper presents the architectural support in an embedded multiprocessor platform to maximally reduce the parallel processing overhead. The effectiveness of these architecture designs in boosting parallel performance is evaluated by an implementation example of 64x64 complex matrix multiplication. The result shows that the parallel processing overhead is reduced from 369% to 28%., ePUMA

The EU WINNER projects have studied OFDM-based packet data systems beyond 3G that use adaptivity on all time-scales to obtain high flexibility and performance. The adaptive transmission in both downlink and uplink is scheduled and controlled at base stations and relay nodes and requires frequent transmission of control information over the downlink. The use of scheduling, adaptive modulation and coding, with fine granularity in both time and space, could potentially result in unrealistic bandwidth demands for such downlink control signaling. The present paper describes how this problem has been handled within WINNER in two cases: Frequency-adaptive transmission, which allows individual link adaptation within time-frequency resource units and non-frequency adaptive transmission, which averages over the channel variations in the frequency domain. An important tool for limiting the associated control information is to broadcast only a small essential set of control data to all user terminals, using a safe but therefore bandwidth-demanding code rate. The remaining control information is multicast to groups of users with different signal to interference and noise ratios (SINRs). The modulation and code rates of these transmissions are adjusted to the SINRs of these groups. The over-all coded data rate of the control transmission can thereby be reduced to acceptable levels.