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High speed TSV signals can penetrate through the dielectric liner material, transfer in the silicon substrate and degrade the performance of FEOL devices. In this paper we investigate TSV noise coupling to active device including both FinFET and planar transistors. Calibrated TCAD models are used to perform time domain analysis and understand the mechanisms of substrate noise interaction with active device. Parametric simulations are performed in order to understand the tradeoffs among different design parameters. The results demonstrate superior substrate noise immunity of FinFETs over equivalent planar transistors. In addition we show that a scaled TSV diameter, a novel TSV architecture with thick polymer liner, placing the substrate contact closer to active device and a TSV guard ring helps to mitigate the TSV noise. Finally the importance of electromagnetic coupling effects on Keep Out Zone (KOZ) extraction is illustrated.

With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit performance are likely to suffer the most from this phenomena. While Statistical static timing analysis (SSTA) is used extensively for this purpose, it does not account for dynamic conditions during operation. In this paper, we present a multivariate regression based technique that computes the propagation delay of circuits subject to manufacturing process variations in the presence of temporal variations like temperature. It can be used to predict the dynamic behavior of circuits under changing operating conditions. The median error between the proposed model and circuit-level simulations is below 5%. With this model, we ran a study of the effect of temperature on access time delays for 500 cache samples. The study was run in 0.557 seconds, compared to the 20h and 4min of the SPICE simulation achieving a speedup of over 1??105. As a case study, we show that the access times of caches can vary as much as 2.03?? at high temperatures in future technologies under process variations., Peer Reviewed, Postprint (published version)

This paper presents VHDL-AMS models and simulation results for a complex, self-organizing neural system based on the adaptive resonance theory. Such neural systems exhibit both discrete and continuous dynamic behavior and consist of a large number of analog equations, a digital controller with analog and digital feedback paths resulting in the complexity that would prohibit analysis with conventional mixed-signal simulation tools.

Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling tendencies of IC scaling are analysed, following interest in advanced technologies. The potential for permanent errors is shown in the case of a RAM cell. A circuit-level model for the coupling mechanism is proposed. The implementation of an IC for experimentation, and the measurements obtained, are discussed, Peer Reviewed, Postprint (published version)

The principles of an automated cross-talk extractor from the mask-level description of a CMOS integrated circuit are detailed. The physical extraction principles, the techniques for parasitic coupling evaluation and modeling, the technique for back-annotating the schematic diagram of the integrated circuit are presented. A model for mixed-level simulation is proposed, covering various parasitic effects of the cross-talk phenomenon. The efficiency of the cross-talk extractor is demonstrated through the analysis of mixed digital/analog CMOS integrated circuits where critical couplings are predicted and eliminated, Peer Reviewed, Postprint (published version)