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In this study, we demonstrate the implementation of programmable threshold logics using a 32 × 32 memristor crossbar array. Thanks to forming-free characteristics obtained by the annealing process, its accurate programming characteristics are presented by a 256-level grayscale image. By simultaneous subtraction between weighted sum and threshold values with a differential pair in an opposite way, 3-input and 4-input Boolean logics are implemented in the crossbar without additional reference bias. Also, we verify a full-adder circuit and analyze its fidelity, depending on the device programming accuracy. Lastly, we successfully implement a 4-bit ripple carry adder in the crossbar and achieve reliable operations by read-based logic operations. Compared to stateful logic driven by device switching, a 4-bit ripple carry adder on a memristor crossbar array can perform more reliably in fewer steps thanks to its read-based parallel logic operation.

In the year of 1991, I was a senior student at Seoul National University of Korea. I saw a young new professor working at a computer room of the Inter-university Semiconductor Research Center (ISRC). He brought his own Macintosh with a tiny 9-in monochrome monitor into the computer room, and he was making documents. He did not have any lab, and he didn’t have any students at that time. After I talked to him, I really wanted to become his student. He accepted me as one of the first lab members.

Synaptic devices store the synaptic weight in spiking neural networks (SNNs). However, because synaptic devices are based on memory cells, their synaptic weights are vulnerable to temperature variations, which significantly degrade network accuracy. To implement temperature-robust asynchronous SNNs, neurons with captive synaptic devices (CSD neurons) are proposed in this study. Captive synaptic devices that mimic the temperature characteristics of synaptic devices are located parallel to the integration capacitors. By using the captive synaptic devices for the membrane potential reset, the CSD neurons are inherently equipped to counteract temperature-induced variations. The validity of the CSD neurons was experimentally confirmed using two types of synaptic devices: poly Si-channel charge-trap flash synaptic devices and resistive random access memory devices. When applied to the street view house numbers (SVHN) dataset, the SNNs with CSD neurons successfully maintained a constant inference accuracy value (95.00 %) from 300 to 360 K, even if the output current of the synaptic devices doubled.

We propose a hardware-friendly architecture of a convolutional neural network using a 32 × 32 memristor crossbar array having an overshoot suppression layer. The gradual switching characteristics in both set and reset operations enable the implementation of a 3-bit multilevel operation in a whole array that can be utilized as 16 kernels. Moreover, a binary activation function mapped to the read voltage and ground is introduced to evaluate the result of training with a boundary of 0.5 and its estimated gradient. Additionally, we adopt a fixed kernel method, where inputs are sequentially applied to a crossbar array with a differential memristor pair scheme, reducing unused cell waste. The binary activation has robust characteristics against device state variations, and a neuron circuit is experimentally demonstrated on a customized breadboard. Thanks to the analogue switching characteristics of the memristor device, the accurate vector–matrix multiplication (VMM) operations can be experimentally demonstrated by combining sequential inputs and the weights obtained through tuning operations in the crossbar array. In addition, the feature images extracted by VMM during the hardware inference operations on 100 test samples are classified, and the classification performance by off-chip training is compared with the software results. Finally, inference results depending on the tolerance are statistically verified through several tuning cycles.