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In this work, we propose a gate structure to enhance the memory window (MW) of Si-channel Hf0.5Zr0.5O2 FeFETs. We achieve an MW of 10.04 V by inserting an Al2O3/HfO2/Al2O3 (AHA) top dielectric interlayer between the ferroelectric Hf0.5Zr0.5O2 layer and the metal gate, where the gate-stack thickness is 14.8 nm. The physical origin is that the Al2O3/HfO2, HfO2/Al2O3, and Al2O3/Hf0.5Zr0.5O2 interfaces can trap charges from the metal gate, contributing to the MW enhancement. This AHA top dielectric multilayer effectively suppresses charge loss compared with a single Al2O3 top dielectric interlayer. Moreover, the de-trapping of charges injected from the metal gate is the primary factor for the degradation of the MW in this structure. Our work provides a guide for improving the MW of FeFET.

We study the impact of top SiO2 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistor (FeFET) with TiN/SiO2/ Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. We find that the MW increases with the increasing thickness of the top SiO2 interlayer, and such an increase exhibits a two-stage linear dependence. The physical origin is the presence of the different interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface. Moreover, we investigate the dependence of endurance characteristics on initial MW. We find that the endurance characteristic degrades with increasing the initial MW. Meanwhile, we study the impact of the top SiO2 interlayer thickness on the retention characteristics of the MIFIS structure. The results of retention characteristics show that the MIFIS structure with thicker top SiO2 has poorer retention characteristics. This is attributed to the de-trapping of interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface and the depolarization field of the ferroelectric. By inserting a 3.4 nm SiO2 dielectric interlayer between the gate metal TiN and the ferroelectric Hf0.5Zr0.5O2, we achieve a MW of 6.3 V and retention over 10 years. Our work is helpful in the device design of FeFET.

In this work, we demonstrate the enlargement of the memory window of Si channel FeFET with ferroelectric Hf0.5Zr0.5O2 by gate-side dielectric interlayer engineering. By inserting a 3 nm Al2 O3 dielectric interlayer between TiN gate metal and ferroelectric Hf0.5Zr0.5O2, we achieve a memory window of 4.1 V with endurance of ~104 cycles and retention over 10 years. The physical origin of memory window enlargement is clarified to be charge trapping at the Al2O3/Hf0.5Zr0.5O2 interface, which has an opposite charge polarity to the trapped charges at the Hf0.5Zr0.5O2/SiOx interface.