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We demonstrate the first successful growth of large-area (200 × 200 μm2) bilayer, Bernal stacked, epitaxial graphene (EG) on atomically flat, 4H-SiC (0001) step-free mesas (SFMs) . The use of SFMs for the growth of graphene resulted in the complete elimination of surface step-bunching typically found after EG growth on conventional nominally on-axis SiC (0001) substrates. As a result heights of EG surface features are reduced by at least a factor of 50 from the heights found on conventional substrates. Evaluation of the EG across the SFM using the Raman 2D mode indicates Bernal stacking with low and uniform compressive lattice strain of only 0.05%. The uniformity of this strain is significantly improved, which is about 13-fold decrease of strain found for EG grown on conventional nominally on-axis substrates. The magnitude of the strain approaches values for stress-free exfoliated graphene flakes. Hall transport measurements on large area bilayer samples taken as a function of temperature from 4.3 to 300 K revealed an n-type carrier mobility that increased from 1170 to 1730 cm2V–1s–1, and a corresponding sheet carrier density that decreased from 5.0 × 1012cm–2to 3.26 × 1012cm–2. The transport is believed to occur predominantly through the top EG layer with the bottom layer screening the top layer from the substrate. These results demonstrate that EG synthesized on large area, perfectly flat on-axis mesa surfaces can be used to produce Bernal-stacked bilayer EG having excellent uniformity and reduced strain and provides the perfect opportunity for significant advancement of epitaxial graphene electronics technology.

Epitaxial graphene (EG) has attracted considerable interest because of its extraordinary properties and ability to be synthesized on the wafer scale. These attributes have enabled EG to be applied in field-effect transistors with extrinsic operating frequencies in the hundreds-of-gigahertz range. Although the quality of EG grown on SiC has improved, there are still obstacles, such as low carrier mobility and large-area thickness nonuniformity, that limit applications in a wide range of truly wafer-scale technologies. In this article, key elements of epitaxial graphene synthesis are highlighted and discussed with regard to impacts on large-area uniformity, structure, and electrical properties. The effects of specific components such as growth-reactor design and substrate quality are examined in an effort to provide a pathway for future advancements in EG production. Finally, key future directions for research in EG are briefly discussed.

Traps responsible for gate-induced current transients and rate-dependent transport properties in gallium nitride nanowire field-effect transistors have been investigated. Our results suggest these traps are acceptor states located ∼0.85 eV above the valence band and are at or near the nanowire surface. Deposition of a 40 nm SiNxpassivation layer reduces trap density by a factor of ∼4 resulting in a lower limit estimate of surface state density of 1.2 × 1011cm−2/eV.

High density plasma etching of mercury cadmium telluride using CH4/H2/Ar plasma chemistries is investigated. Mass spectrometry is used to identify and monitor etch products evolving from the surface during plasma etching. The identifiable primary etch products are elemental Hg, TeH2, and Cd(CH3)2. Their relative concentrations are monitored as ion and neutral fluxes (both in intensity and composition), ion energy and substrate temperature are varied. General insights are made into surface chemistry mechanisms of the etch process. These insights are evaluated by examining etch anisotropy and damage to the remaining semiconductor material. Regions of process parameter space best suited to moderate rate, anisotropic, low damage etching of HgCdTe are identified.

Although food handlers are often implicated as the source of infection in outbreaks of food-borne viral gastroenteritis, little is known about the timing of infectivity in relation to illness. We investigated a gastroenteritis outbreak among employees of a manufacturing company and found an association (RR=14·1, 95% CI=2·0–97·3) between disease and eating sandwiches prepared by 6 food handlers, 1 of whom reported gastroenteritis which had subsided 4 days earlier. Norwalk-like viruses were detected by electron microscopy or reverse transcriptase-polymerase chain reaction (RT-PCR) in stool specimens from several company employees, the sick food handler whose specimen was obtained 10 days after resolution of illness, and an asymptomatic food handler. All RT-PCR product sequences were identical, suggesting a common source of infection. These data support observations from recent volunteer studies that current recommendations to exclude food handlers from work for 48–72 h after recovery from illness may not always prevent transmission of Norwalk-like viruses because virus can be shed up to 10 days after illness or while exhibiting no symptoms.

The effects of nitrogen-beam voltage on the structure, stress, energy band gap and hardness of AIN thin films deposited on Si (111), Si (100) and sapphire (0001) by ion beam assisted deposition (IBAD) are reported. As the nitrogen-beam voltage was increased from 50 to 200 V, the stress and disorder in the AIN films increased as determined by X-ray diffraction, FTIR and Raman spectroscopy. The preferred orientation of the film's c-axis changed from completely normal to the film at 100 V, to a mixture of normal and in the plane of the film at 200 V. For AIN films deposited under the same conditions, the films were more highly oriented on sapphire (0001) than in Si (111). The hardness of the films increased from 18.2 to 23.7 GPa with the nitrogen-beam voltage, and possible reasons for this change in hardness are considered.

An equation is presented that predicts the number of inputs required to produce a step-function (frontal) output in countercurrent distribution (CCD). When a portion of both phases is transported during experiments, the published equations for CCD are inappropriate. Expressions have been derived that predict the properties of elution and frontal outputs when biphasic flow occurs. When phase volumes and partition coefficients vary during the course of the distribution, computer simulation of the process, using the appropriate ternary phase diagram becomes necessary for adequate prediction of solute profiles. Shifts in position, shape, and height of frontal outputs and the nature of excess lower phase in the effluent are predicted and compare well with experimental results.

Reduced performance in Gallium Nitride (GaN)-based high electron mobility transistors (HEMTs) as a result of self-heating has been well-documented. To mitigate this effect, the incorporation of high thermal conductivity diamond heat spreading films or substrates has been proposed. A mid-process integration scheme, termed “gate-after-diamond,” is shown to improve the thermal budget for NCD deposition and enables scalable, large-area diamond coating without degrading the Schottky gate metal. The optimization of this process step is presented in this work. Nanocrystalline (NCD)-capped devices had a 20% lower channel temperature at equivalent power dissipation. Improved electrical characteristics were also observed, notably improved on-resistance and breakdown voltage, and reduced gate leakage.

The properties of thick GaN layers grown by metal organic chemical vapor deposition on 2″HVPE substrates were investigated. Although the epilayer is smooth on a microscopic scale with high quality layers as evidenced by X-ray diffraction and photoluminescence, macroscopic morphological variations are observed on the wafer surface. These variations correspond to disparities in leakage current in fabricated Schottky barrier diodes, with rougher macroscopic morphology resulting in increased leakage current.

This paper reports on the influence of deposition temperature on the structure, composition, and electrical properties of TiO2thin films deposited on n-type silicon (100) by plasma-assisted atomic layer deposition (PA-ALD). TiO2layers ∼20 nm thick, deposited at temperatures ranging from 100 to 300°C, were investigated. Samples deposited at 200°C and 250°C had the most uniform coverage as determined by atomic force microscopy. The average carbon concentration throughout the oxide layer and at the TiO2/Si interface was lowest at 200°C. Metal oxide semiconductor capacitors (MOSCAPs) were fabricated, and profiled by capacitance-voltage techniques. The sample prepared at 200°C had negligible hysteresis (from a capacitance-voltage plot) and the lowest interface trap density (as extracted using the conductance method). Current-voltage measurements were carried out with top-to-bottom structures. At −2 V gate bias voltage, the smallest leakage current was 1.22 × 10−5A/cm2for the 100°C deposited sample.